Chemical Etching Patents (Class 438/8)
  • Publication number: 20140345683
    Abstract: Provided are methods and systems for treating shunts on solar cell substrates. Also provided are solar cells including such substrates. A shunt detected on a substrate proximate to a metallized grid pattern is electrically disconnected from at least the bus portion of the grid, which reduces shunt's impact on performance on the solar cell. An antireflective layer may be disposed between the shunt and a portion of the grid extending over the shunt. The exposure pattern of a photoresist used to form the antireflective layer may be adjusted accordingly to achieve this result. In some embodiments, the metallized grid may be modified by adjusting the exposure pattern of a photoresist used to form this grid. The grid may be modified to avoid any contact between the grid and the shunt or to disconnect a portion of the grid contacting the shunt from the bus portion area of the grid.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Applicant: The Boeing Company
    Inventors: Philip Chiu, Shoghig Mesropian, Dimitri D. Krut
  • Publication number: 20140346647
    Abstract: A monitoring structure and a relevant monitoring method for the silicon wet etching depth are provided. The structure includes a wet etched groove formed on a monocrystalline silicon material with at least two top surfaces thereof being rectangular; and the top surface widths of the grooves are Wu and Wl respectively, Wu=du/0.71, and Wl=du/0.71, where du is the maximum wet etching depth to be monitored, and dl is the minimum of the wet etching depth to be monitored. The method includes: performing anisotropic wet etching on a monocrystalline silicon wafer according to a pattern with a monitoring pattern, forming an etched groove to be monitored and a structure for monitoring the depth of the groove, and then monitoring the structure to monitor the wet etching depth. The etching depth of the groove can be monitored with low costs, and a higher monitoring accuracy is obtained.
    Type: Application
    Filed: November 20, 2012
    Publication date: November 27, 2014
    Inventors: Xinwei Zhang, Changfeng Xia, Chengjian Fan, Wei Su
  • Patent number: 8892568
    Abstract: A method of controlling polishing includes storing a library having a plurality of reference spectra, polishing a substrate, measuring a sequence of spectra of light from the substrate during polishing, for each measured spectrum of the sequence of spectra, finding a best matching reference spectrum using a matching technique other than sum of squared differences to generate a sequence of best matching reference spectra, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on the sequence of best matching reference spectra. Finding a best matching reference spectrum may include performing a cross-correlation of the measured spectrum with each of two or more of the plurality of reference spectra from the library and selecting a reference spectrum with the greatest correlation to the measured spectrum as a best matching reference spectrum.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: November 18, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey Drue David, Dominic J. Benvegnu, Xiaoyuan Hu
  • Publication number: 20140315331
    Abstract: Candidate wet processes for native oxide removal from, and passivation of, germanium surfaces can be screened by high-productivity combinatorial variation of different process parameters on different site-isolated regions of a single substrate. Variable process parameters include the choice of hydrohalic acid used to remove the native oxide, the concentration of the acid in the solution, the exposure time, and the use of an optional sulfur passivation step. Measurements to compare the results of the process variations include attenuated total reflectance Fourier transform infrared spectroscopy (ATR-FTIR), contact angle, atomic force microscopy (AFM), scanning electron microscopy (SEM), and X-ray fluorescence (XRF). A sample screening experiment indicated somewhat less native oxide regrowth using HCl or HBr without sulfur passivation, compared to using HF with sulfur passivation.
    Type: Application
    Filed: March 11, 2014
    Publication date: October 23, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Sandip Niyogi, Shuogang Huang, Chi-I Lang
  • Patent number: 8852967
    Abstract: A multiple channel site-isolated reactor system and method are described. The system contains a reactor block with a plurality of reactors. Input lines are coupled to each reactor to provide a fluid to the respective reactors. A sealing element associated with each reactor contacts a surface of a substrate disposed below the reactor block, which defines isolated regions on the surface of the substrate. A dissolution rate monitor extends into each reactor to monitor a rate of real-time dissolution of one or more layers on the surface of the substrate when it is disposed proximate to the surface of the substrate.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: October 7, 2014
    Assignee: Intermolecular, Inc.
    Inventor: George Mirth
  • Publication number: 20140273297
    Abstract: In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: SAMER BANNA, OLIVIER JOUBERT, LEI LIAN, MAXIME DARNON, NICOLAS POSSEME, LAURENT VALLIER
  • Publication number: 20140273296
    Abstract: A method of controlling polishing of a substrate is described. A controller stores a library having a plurality of reference spectra. The controller polishes a substrate and measures a sequence of spectra of light from the substrate during polishing. For each measured spectrum of the sequence of spectra, the controller finds a best matching reference spectrum from the plurality of reference spectra and generates a sequence of best matching reference spectra. The controller uses a cell counting technique for finding the best matching reference spectrum. The controller determines at least one of a polishing endpoint or an adjustment for a polishing rate based on the sequence of best matching reference spectra.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Applied Materials, Inc.
    Inventor: Kiran Lall Shrestha
  • Patent number: 8828745
    Abstract: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: September 9, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Che Tsao, Chia-Lin Hsu, Jen-Chieh Lin, Teng-Chun Tsai, Hsin-Kuo Hsu, Ya-Hsueh Hsieh, Ren-Peng Huang, Chih-Hsien Chen, Wen-Chin Lin, Yung-Lun Hsieh
  • Publication number: 20140242730
    Abstract: An optical model for a layer stack has a plurality of input parameters, the plurality of input parameters defining a parameter space. A plurality of model spectra are generated by calculating a model spectrum using the optical model for each of a first plurality of different points in the parameter space. A test spectrum of a test substrate is measured. For each model spectrum of the plurality of model spectra, the test spectrum is compared to the model spectrum to determine a difference value, thereby generating a plurality of difference values. A plurality of minima in the plurality of difference values are determined. Reference spectra can be generated clustered around points in the parameter space corresponding to a local minimum from the plurality of minima, or the local minimum can be used as a seed value in fitting the optical model to a measured spectrum.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Inventor: Jeffrey Drue David
  • Publication number: 20140242731
    Abstract: A system and method for performing a wet etching process is disclosed. The system includes multiple processing stations accessible by a transfer device, including a measuring station to optically measure the thickness of a substrate, a controller to calculate an etch recipe for the substrate, in real time, and cause a single wafer wet etching station to etch the substrate according to the recipe. In addition, the system can measure the after etch thickness and calculate etch recipes, in real time, as a function of the final measurements of a previous substrate. The system can also include an in situ end point detection device for detecting the TSV reveal point while etching TSVs substrates. The system provides an automated solution to adjust etch recipe parameters in real time according to feedback concerning previously etched wafers and precisely control the TSV reveal height and etch duration using end point detection.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 28, 2014
    Applicant: Solid State Equipment LLC
    Inventors: Laura Mauer, Elena Lawrence, John Taddei, Ramey Youssef
  • Patent number: 8808559
    Abstract: A method and apparatus for etching a photomask substrate with enhanced process monitoring, for example, by providing for optical monitoring at different regions of the photomask to obtain desired etch rate or thickness loss is provided. In one embodiment, the method includes performing an etching process on a reflective multi-material layer that includes at least one molybdenum layer and one silicon layer through a patterned mask, directing radiation having a wavelength from about 170 nm and about 800 nm to an area of the multi-material layer uncovered by the patterned mask, collecting an optical signal reflected from the area uncovered by the patterned mask, analyzing a waveform obtained from the reflected optical signal, and determining a first endpoint of the etching process when an intensity of the reflected optical signal is between about 60 percent and about 90 percent less than an initial reflected optical signal.
    Type: Grant
    Filed: July 8, 2012
    Date of Patent: August 19, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Michael Grimbergen
  • Publication number: 20140196782
    Abstract: Disclosed is a method for yield enhancement of making a semiconductor device. The method for yield enhancement of making a semiconductor device comprises the steps of: providing the semiconductor device comprising an epitaxial layer including a defect; forming a dielectric layer on the epitaxial layer; detecting and identifying a location of the defect; and etching the dielectric layer and leaving a part of the dielectric layer to cover an area substantially corresponding to the detected defect. The semiconductor device made by the method is also disclosed.
    Type: Application
    Filed: January 10, 2014
    Publication date: July 17, 2014
    Applicant: EPISTAR CORPORATION
    Inventors: Yi Hung LIN, Yu Chih YANG, Wu Tsung LO
  • Patent number: 8772054
    Abstract: A method comprises providing a semiconductor substrate having at least one layer of a material over the substrate. A sound is applied to the substrate, such that a sound wave is reflected by a top surface of the layer of material The sound wave is detected using a sensor. A topography of the top surface is determined based on the detected sound wave. The determined topography is used to control an immersion lithography process.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: July 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Pan Wang, Chien-Hsuan Liu, Ching-Hsien Chen, Chao-Chi Chen
  • Patent number: 8753896
    Abstract: A method of monitoring a surfactant in a microelectronic process is disclosed. Specifically, the monitoring of a surfactant occurs by studying the fluorescence or electromagnetic emission of a sample collected from a microelectronic process.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: June 17, 2014
    Assignee: Nalco Company
    Inventors: Brian V. Jenkins, John E. Hoots, Amy M. Tseng
  • Publication number: 20140147942
    Abstract: According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.
    Type: Application
    Filed: February 4, 2014
    Publication date: May 29, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenji AOYAMA, Kazuhiko YAMAMOTO, Satoshi ISHIKAWA, Shigeto OSHINO
  • Patent number: 8716028
    Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: May 6, 2014
    Assignee: Nalco Company
    Inventors: Amy Tseng, Brian V. Jenkins, Robert M. Mack
  • Publication number: 20140106475
    Abstract: A method for etching a polysilicon gate is disclosed, wherein the polysilicon gate includes an undoped polysilicon portion and a doped polysilicon portion that is situated on the undoped polysilicon portion. The method includes: obtaining a thickness of the undoped polysilicon portion and a thickness of the doped polysilicon portion by using an optical linewidth measurement device; and etching the undoped polysilicon portion and the doped polysilicon portion by using two respective steps with different parameters, respective etching time for the undoped polysilicon portion and the doped polysilicon portion of every wafer being adjusted in real time by using an advanced process control system. This method enables the doped and undoped polysilicon portions of each polysilicon gate on every wafer to have substantially consistent profiles between each other.
    Type: Application
    Filed: December 28, 2012
    Publication date: April 17, 2014
    Applicant: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventor: SHANGHAI HUALI MICROELECTRONICS CORPORATION
  • Patent number: 8699038
    Abstract: Apparatus for monitoring a thickness of a silicon wafer with a highly-doped layer at least at a backside of the silicon wafer is provided. The apparatus has a source configured to emit coherent light of multiple, wavelengths. Moreover, the apparatus comprises a measuring head configured to be contactlessly positioned adjacent the silicon wafer and configured to illuminate at least a portion of the silicon wafer with the coherent light and to receive at least a portion of radiation reflected by the silicon wafer. Additionally, the apparatus comprises a spectrometer, a beam splitter and an evaluation device. The evaluation device is configured to determine a thickness of the silicon wafer by analyzing the radiation reflected by the silicon wafer by an optical coherence tomography process. The coherent light is emitted multiple wavelengths in a bandwidth b around a central wavelength wc.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: April 15, 2014
    Assignee: Precitec Optronik GmbH
    Inventors: Martin Schoenleber, Christoph Dietz
  • Publication number: 20140099737
    Abstract: The present invention provides a method for monitoring a contact hole etching process of a TFT substrate, which includes: (1) providing a substrate having a first metal layer and a monitoring machine; (2) providing a target value of reflection rate of the substrate having the first metal layer; (3) applying a masking operation to patternize the first metal layer for forming a gate terminal; (4) forming a gate insulation layer on the gate terminal; and (5) forming a contact hole in the gate insulation layer through etching and simultaneously operating the monitoring machine to measure the reflection rate of a bottom of the contact hole, whereby when the reflection rate of the bottom of the contact hole is substantially equal to the target value, the etching operation is stopped. The variation of reflection rate of the metal layer is monitored to identify if the insulation layer is completely etched away.
    Type: Application
    Filed: October 24, 2012
    Publication date: April 10, 2014
    Applicant: Shenzhen China Star Optoelectronics Technology Co., LTD.
    Inventor: Xiangdeng Que
  • Patent number: 8685825
    Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: April 1, 2014
    Assignee: Advanced Ion Beam Technology, Inc.
    Inventors: Daniel Tang, Tzu-Shih Yen
  • Publication number: 20140080232
    Abstract: A polishing system receives one or more target parameters for a selected peak in a spectrum of light, polishes a substrate, measures a current spectrum of light reflected from the substrate while the substrate is being polished, identifies the selected peak in the current spectrum, measures one or more current parameters of the selected peak in the current spectrum, compares the current parameters of the selected peak to the target parameters, and ceases to polish the substrate when the current parameters and the target parameters have a pre defined relationship.
    Type: Application
    Filed: November 25, 2013
    Publication date: March 20, 2014
    Applicant: Applied Materials, Inc.
    Inventors: Dominic J. Benvegnu, Boguslaw A. Swedek, David J. Lischka
  • Publication number: 20140065733
    Abstract: System, method and computer program product for configuring and controlling a facility to perform a manufacturing process and updating a tool controlling the process according to a model employed for mapping calculated coefficients that characterize non-linear variations observed of a product to actual control parameters governing the processes/tools used by the facility during the manufacturing process. The method enables real-time control of variation in an exposure step of a patterning process using an exposure tool to minimize a nonlinear variation in one or more pattern attributes by adjusting the exposure tool or the patterning process corresponding to the calculated coefficients. In the method, measurements of product attributes, obtained by finite sampling over a well defined domain, are projected onto a predefined reference mesh spanning the domain, using a physically based model comprised of functions constructed to be orthogonal and normalized over a discrete set of reference mesh locations.
    Type: Application
    Filed: November 13, 2013
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Christopher P. Ausschnitt
  • Publication number: 20140065732
    Abstract: According to one embodiment, a wafer processing device includes a processed number counting unit that counts a number of processed wafers, and a maintenance post-processing unit that executes a dummy lot process and a QC lot process after a maintenance process. A wafer preparation device prepares the dummy lot and the QC lot, when a first processed number is counted by the processed number counting unit. When a second processed number is counted by the processed number counting unit, a carrier device carries the dummy lot and the QC lot to the wafer processing device simultaneous with the maintenance process, before the maintenance process is completed.
    Type: Application
    Filed: March 12, 2013
    Publication date: March 6, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Eiichi OKADA
  • Patent number: 8652971
    Abstract: A MEMS device having a device cavity in a substrate has a cavity etch monitor proximate to the device cavity. An overlying layer including dielectric material is formed over the substrate. A monitor scale is formed in or on the overlying layer. Access holes are etched through the overlying layer and a cavity etch process forms the device cavity and a monitor cavity. The monitor scale is located over a lateral edge of the monitor cavity. The cavity etch monitor includes the monitor scale and monitor cavity, which allows visual measurement of a lateral width of the monitor cavity; the lateral dimensions of the monitor cavity being related to lateral dimensions of the device cavity.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: February 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Ricky Alan Jackson, Walter Baker Meinel, Karen Hildegard Ralston Kirmse
  • Patent number: 8647892
    Abstract: A method for process control is disclosed. The method includes performing an etching process on a semiconductor substrate forming a structure and a test structure having a pattern and a releasing mechanism coupled to the pattern; and monitoring the pattern of the test structure to determine whether the etching process is complete.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: February 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chih Liang, Wen-Chuan Tai, Chun-Ren Cheng
  • Publication number: 20140038316
    Abstract: The invention relates to a method for examining a wire-sawn silicon substrate for a solar cell. The method includes irradiating the silicon substrate with an infrared radiation, detecting the infrared radiation transmitted through the silicon substrate, and analyzing the detected infrared radiation for characterizing the crystal orientation of the silicon substrate. The invention in addition relates to a device for carrying out such a method, and a method for manufacturing a solar cell.
    Type: Application
    Filed: July 15, 2013
    Publication date: February 6, 2014
    Inventors: Alexander FULLE, Andreas KRAUSE, Lamine SYLLA
  • Publication number: 20140015107
    Abstract: Closed loop control may be used to improve uniformity of within wafer uniformity using chemical mechanical planarization. For example, closed loop control may be used to determine a control profile for a chemical mechanical planarization process to more uniformly and consistently achieve the desired extent of variation of within wafer uniformity of a semiconductor wafer.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ching-Kun Chen, Chun-Fu Chen, Chin-Ta Su
  • Publication number: 20140011303
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method may comprise: forming a gate stack on a substrate; depositing a first dielectric layer and a second dielectric layer sequentially on the substrate and the gate stack; and etching the second dielectric layer and the first dielectric layer sequentially with an etching gas containing helium to form a second spacer and a first spacer, respectively. According to the method disclosed herein, a dual-layer complex spacer configuration is achieved, and two etching operations where the etching gas comprises the helium gas are performed. As a result, it is possible to reduce damages to the substrate and also to reduce the process complexity. Further, it is possible to optimize a threshold voltage, effectively reduce an EOT, and enhance a gate control capability and a driving current.
    Type: Application
    Filed: September 5, 2012
    Publication date: January 9, 2014
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Lingkuan Meng
  • Publication number: 20130344625
    Abstract: Methods and apparatus for spectrum-based endpointing. An endpointing method includes selecting a reference spectrum. The reference spectrum is a spectrum of white light reflected from a film of interest on a first substrate and has a thickness greater than a target thickness. The reference spectrum is empirically selected for particular spectrum-based endpoint determination logic so that the target thickness is achieved when endpoint is called by applying the particular spectrum-based endpoint logic. The method includes obtaining a current spectrum. The current spectrum is a spectrum of white light reflected from a film of interest on a second substrate when the film of interest is being subjected to a polishing step and has a current thickness that is greater than the target thickness. The method includes determining, for the second substrate, when an endpoint of the polishing step has been achieved. The determining is based on the reference and current spectra.
    Type: Application
    Filed: August 26, 2013
    Publication date: December 26, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Dominic J. Benvegnu, Jeffrey Drue David, Boguslaw A. Swedek
  • Publication number: 20130316470
    Abstract: The present invention relates to the field of semiconductor integrated circuits, and particularly relates to a method which can form a contact hole in a wafer of semiconductor material. The invention has proposed a method which can form a contact hole in a wafer of semiconductor: measuring and comparing a Critical Dimension (CD) of a position corresponding to the contact hole in the hard mask with the CD required in the technology, and then, based on the measurement, adjusting the CD of the position corresponding to the contact hole in the hard mask, by conformal deposition or etching technology, to fit a requirement of the technology; the method can reduce process costs while improving production capacity.
    Type: Application
    Filed: December 6, 2012
    Publication date: November 28, 2013
    Applicant: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventor: Jun ZHOU
  • Patent number: 8581411
    Abstract: A semiconductor device comprises a GaAs substrate having a first major surface and a second major surface opposite to each other; a first metal layer composed of at least one of Pd, Ta, and Mo on the first major surface of the GaAs substrate; and a second metal layer composed of a Ni alloy or Ni on the first metal layer.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: November 12, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Koichiro Nishizawa
  • Patent number: 8580585
    Abstract: A method for forming identical isotropic etch patterns in an etch system is disclosed. The method comprises providing a wafer paddle, a wafer, a plurality of identical etch systems, utilizing identical etch recipes within each of the plurality of etch systems, providing a fixed temperature stability time FTST for each system so that the heat transfer from the paddle to the wafer is constant, wherein the FTST is the same on each of the plurality of etch systems; and utilizing the plurality of identical etch systems to produce identical etches on each of the wafers based upon the FTST, wherein a five-second preheat step in the etch process is not utilized.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: November 12, 2013
    Assignee: Micrel, Inc.
    Inventor: Howard Kurasaki
  • Patent number: 8562848
    Abstract: Disclosed is an end point detecting method of metal etching and a device thereof. The end point detecting method of metal etching comprises: performing scan to a metal film to acquire a proportion of a transparency area of the metal film in a scanned area; judging whether the proportion of the transparency area reaches a predetermined value or not; and confirming a current etching time of the metal film as an etching end point time when the predetermined value is reached. The device comprises an acquirement module, a judgment module and a confirmation module. The acquirement module performs scan to the metal film to acquire the proportion of the transparency area. The judgment module judges whether the proportion reaches the predetermined value or not. The confirmation module confirms the current etching time of the metal film as the etching end point time when the proportion reaches the predetermined value.
    Type: Grant
    Filed: August 28, 2011
    Date of Patent: October 22, 2013
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Chin-wen Wang, Chengming He
  • Patent number: 8563335
    Abstract: A method of controlling a polishing operation includes polishing a substrate, during polishing obtaining a sequence over time of measured spectra from the substrate with an in-situ optical monitoring system, for each measured spectrum from the sequence of measured spectra applying a Fourier transform to the measured spectrum to generate a transformed spectrum thus generating a sequence of transformed spectra, for each transformed spectrum identifying a peak of interest from a plurality of peaks in the transformed spectrum, for each transformed spectrum determining a position value for the peak of interest in the transformed spectrum thus generating a sequence of position values, and determining at least one of a polishing endpoint or an adjustment of a pressure to the substrate from the sequence of position values.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: October 22, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Dominic J. Benvegnu, Boguslaw A. Swedek
  • Patent number: 8557613
    Abstract: A method for designing, fabricating, and predicting a desired structure in and/or on a host material through defining etch masks and etching the host material is provided. The desired structure can be micro- or nanoscale structures, such as suspended nanowires and corresponding supporting pillars, and can be defined one layer at a time. Arbitrary desired structures can also be defined and obtained through etching. Further, given the desired structure, a starting structure can be predicted where etching of the starting structure yields the desired structure.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: October 15, 2013
    Assignee: California Institute of Technology
    Inventors: Michael Shearn, Michael David Henry, Axel Scherer
  • Patent number: 8557612
    Abstract: A method to determine minimum etch mask dosage or thickness as a function of etch depth or maximum etch depth as a function of etch mask implantation dosage or thickness, for fabricating structures in or on a substrate through etch masking via addition or removal of a masking material and subsequent etching.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: October 15, 2013
    Assignee: California Institute of Technology
    Inventors: Michael David Henry, Michael Shearn, Axel Scherer
  • Publication number: 20130256844
    Abstract: Disclosed are a method for fabricating a semiconductor device and the associated semiconductor structure. The method includes exposing a photoresist layer disposed on a semiconductor wafer utilizing a grating mask having a plurality of grating lines to produce exposed lines and unexposed lines in the photoresist layer. The method further includes exposing the photoresist layer utilizing a trim mask having a blocking portion situated over a selected one of the unexposed lines. The photoresist layer may be developed after exposing the photoresist layer utilizing the trim mask. A line may then be etched into the semiconductor wafer where the selected one of the unexposed lines was blocked by the blocking portion of the trim mask. The width of the unexposed lines may be controlled by adjusting an exposure time or an exposure power for the photoresist layer while utilizing the grating mask.
    Type: Application
    Filed: December 12, 2012
    Publication date: October 3, 2013
    Applicant: Newport Fab, LLC dba Jazz Semiconductor
    Inventors: George Talor, Edward Preisler, David J. Howard
  • Patent number: 8546152
    Abstract: A method of fabricating non-volatile memory is provided for memory cells employing a charge storage element with multiple charge storage regions. A first charge storage layer is formed over a tunnel dielectric layer at both a memory array region and an endpoint region of a semiconductor substrate. The first charge storage layer is removed from the endpoint region to expose the tunnel dielectric region. A second charge storage layer is formed over the first charge storage layer at the memory array region and over the tunnel dielectric layer at the endpoint region. When etching the second charge storage layer to form the stem regions of the memory cells, the tunnel dielectric layer provides a detectable endpoint signal to indicate that etching for the second charge storage layer is complete.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: October 1, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Takashi Orimoto, George Matamis, James Kai, Vinod Robert Purayath
  • Patent number: 8538572
    Abstract: A method for automatically identifying an optimal endpoint algorithm for qualifying a process endpoint during substrate processing within a plasma processing system is provided. The method includes receiving sensor data from a plurality of sensors during substrate processing of at least one substrate within the plasma processing system, wherein the sensor data includes a plurality of signal streams from a plurality of sensor channels. The method also includes identifying an endpoint domain, wherein the endpoint domain is an approximate period within which the process endpoint is expected to occur. The method further includes analyzing the sensor data to generate a set of potential endpoint signatures. The method yet also includes converting the set of potential endpoint signatures into a set of optimal endpoint algorithms. The method yet further includes importing one optimal endpoint algorithm of the set of optimal endpoint algorithms into production environment.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: September 17, 2013
    Assignee: Lam Research Corporation
    Inventors: Jiangxin Wang, Andrew James Perry, Vijayakumar C Venugopal
  • Publication number: 20130224890
    Abstract: A method of controlling polishing includes storing a desired ratio representing a ratio for a clearance time of a first zone of a substrate to a clearance time of a second zone of the substrate. During polishing of a first substrate, an overlying layer is monitored, a sequence of measurements is generated, and the measurements are sorted a first group associated with the first zone of the substrate and a second group associated with the second zone on the substrate. A first time and a second time at which the overlying layer is cleared is determined based on the measurements from the first group and the second group, respectively. At least one adjusted polishing pressure is calculated for the first zone based on a first pressure applied in the first zone during polishing the first substrate, the first time, the second time, and the desired ratio.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 29, 2013
    Inventors: Kun Xu, Ingemar Carlsson, Tzu-Yu Liu, Shih-Haur Shen, Boguslaw A. Swedek, Wen-Chiang Tu, Lakshmanan Karuppiah
  • Patent number: 8518721
    Abstract: A method is provided including depositing a layer of material on a substrate, during deposition of the material, at a predetermined depth, laterally implanting a first dopant and a second dopant in the material, the second dopant being different from the first dopant, etching the material, during etching, detecting the positions and intensities of the first and second dopants, and calculating lateral homogeneity of the material in situ from the intensities of the first and second dopants.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: August 27, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Dmytro Chumakov, Peter Baars
  • Patent number: 8518285
    Abstract: A substrate section for a flexible display device is disclosed. The substrate section includes: a first substrate, a second substrate disposed above a center region of the first substrate, a reinforcing layer disposed between the first and second substrates, configured to reinforce adhesion between the first and second substrates, and a barrier layer disposed above the second substrate and surrounding side surfaces of the second substrate and of the reinforcing layer.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: August 27, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dong-Beom Lee
  • Publication number: 20130210172
    Abstract: A wafer thinning apparatus includes a first metrology tool configured to measure an initial thickness of the wafer. The wafer thinning apparatus further includes a controller connected to the first metrology tool, and configured to determine a polishing time based on the initial thickness, a predetermined thickness and a material removal rate. The wafer thinning apparatus further includes a polishing tool connected to the controller configured to polish the wafer for a period of time equal to the polishing time. The wafer thinning apparatus includes a second metrology tool connected to the controller and the polishing tool, and configured to measure a polished thickness. The controller is configured to update the material removal rate based on the polished thickness, the predetermined thickness and the polishing time.
    Type: Application
    Filed: February 10, 2012
    Publication date: August 15, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Hsuan Chen, Kei-Wei CHEN, Ying-Lang WANG, Kuo-Hsiu WEI
  • Publication number: 20130189801
    Abstract: A finishing operation for a workpiece involves supplying an organic boundary lubricant to an operative finishing interface located between a finishing apparatus finishing element finishing surface and a surface of the workpiece being finished, and sensing in situ finishing information with an operative sensor. A change for a process control parameter is determined using the in situ finishing information, information from metrology equipment operatively coupled to the finishing apparatus, and information related to the finishing apparatus. An operative controller thereafter changes the process control parameter to change a processing control at least in part related to the finishing operation.
    Type: Application
    Filed: January 14, 2013
    Publication date: July 25, 2013
    Applicant: SEMCON TECH, LLC
    Inventor: SEMCON TECH, LLC
  • Publication number: 20130183773
    Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 18, 2013
    Inventors: Amy M. Tseng, Brian V. Jenkins, Robert Mack
  • Publication number: 20130130409
    Abstract: A method and apparatus for etching a photomask substrate with enhanced process monitoring, for example, by providing for optical monitoring at different regions of the photomask to obtain desired etch rate or thickness loss is provided. In one embodiment, the method includes performing an etching process on a reflective multi-material layer that includes at least one molybdenum layer and one silicon layer through a patterned mask, directing radiation having a wavelength from about 170 nm and about 800 nm to an area of the multi-material layer uncovered by the patterned mask, collecting an optical signal reflected from the area uncovered by the patterned mask, analyzing a waveform obtained from the reflected optical signal, and determining a first endpoint of the etching process when an intensity of the reflected optical signal is between about 60 percent and about 90 percent less than an initial reflected optical signal.
    Type: Application
    Filed: July 8, 2012
    Publication date: May 23, 2013
    Inventor: Michael Grimbergen
  • Publication number: 20130065328
    Abstract: A method comprises providing a semiconductor substrate having at least one layer of a material over the substrate. A sound is applied to the substrate, such that a sound wave is reflected by a top surface of the layer of material The sound wave is detected using a sensor. A topography of the top surface is determined based on the detected sound wave. The determined topography is used to control an immersion lithography process.
    Type: Application
    Filed: September 8, 2011
    Publication date: March 14, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Pan WANG, Chien-Hsuan Liu, Ching-Hsien Chen, Chao-Chi Chen
  • Publication number: 20130050686
    Abstract: A device includes one or more reflector components. Each reflector component comprises layer pairs of epitaxially grown reflective layers and layers of a non-epitaxial material, such as air. Vias extend through at least some of the layers of the reflector components. The device may include a light emitting layer.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Applicant: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Thomas Wunderer, Christopher L. Chua, Brent S. Krusor, Noble M. Johnson
  • Publication number: 20130034918
    Abstract: According to the invention, a monitoring device (12) is created for monitoring a thinning of at least one semiconductor wafer (4) in a wet etching unit (5), wherein the monitoring device (12) comprises a light source (14), which is designed to emit coherent light of a light wave band for which the semiconductor wafer (4) is optically transparent. The monitoring device (12) further comprises a measuring head (13), which is arranged contact-free with respect to a surface of the semiconductor wafer (4) to be etched, wherein the measuring head (13) is designed to irradiate the semiconductor wafer (4) with the coherent light of the light wave band and to receive radiation (16) reflected by the semiconductor wafer (4). Moreover, the monitoring device (12) comprises a spectrometer (17) and a beam splitter, via which the coherent light of the light wave band is directed to the measuring head (13) and the reflected radiation is directed to the spectrometer (17).
    Type: Application
    Filed: January 10, 2011
    Publication date: February 7, 2013
    Applicants: DUSEMUND PTE. LTD, PRECITEC OPTRONIC GMBH
    Inventors: Claus Dusemund, Martin Schoenleber, Berthold Michelt, Christoph Dietz
  • Patent number: 8369978
    Abstract: A computer-implemented method includes receiving a sequence of current spectra of reflected light from a substrate; comparing each current spectrum from the sequence of current spectra to a plurality of reference spectra from a reference spectra library to generate a sequence of best-match reference spectra; determining a goodness of fit for the sequence of best-match reference spectra; and determining at least one of whether to adjust a polishing rate or an adjustment for the polishing rate, based on the goodness of fit.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: February 5, 2013
    Assignee: Applied Materials
    Inventors: Jeffrey Drue David, Dominic J. Benvegnu, Harry Q. Lee, Boguslaw A. Swedek