Abstract: A CD-SEM (critical dimension-scanning electron microscope) system may utilize a technique for characterizing and reducing shrinkage carryover due to CD-SEM measurements. The system may identify the affects of CD-SEM measurements on the resist and adjust the operating parameters for a particular resist to avoid or significantly reduce shrinkage carryover. In this manner, the system may obtain more reliable CD measurements and avoid damage to the measured feature.

Abstract: A method of forming an opening through a substrate having a first side and a second side opposite the first side includes forming spaced etch stops in the first side of the substrate, etching into the substrate from the second side toward the first side to the spaced etch stops, and etching into the substrate between the spaced etch stops from the second side. Etching into the substrate to the spaced etch stops includes forming a first portion of the opening and etching into the substrate between the spaced etch stops includes forming a second portion of the opening.

Abstract: A solid state nanopore device including two or more materials and a method for fabricating the same. The device includes a solid state insulating membrane having an exposed surface, a conductive material disposed on at least a portion of the exposed surface of the solid state membrane, and a nanopore penetrating an area of the conductive material and at least a portion of the solid state membrane. During fabrication a conductive material is applied on a portion of a solid state membrane surface, and a nanopore of a first diameter is formed. When the surface is exposed to an ion beam, material from the membrane and conductive material flows to reduce the diameter of the nanopore. A method for evaluating a polymer molecule using the solid state nanopore device is also described. The device is contacted with the polymer molecule and the molecule is passed through the nanopore, allowing each monomer of the polymer molecule to be monitored.

Abstract: A method for determining metrology sampling rates for workpieces in a process flow includes determining a current status of the process flow. Future processing of the workpieces in the process flow is simulated based on the current status of the process flow over a predetermined time horizon to predict sampling rates for the workpieces. During the simulating, sampling rules are implemented that consider capacity constraints of a metrology resource in the process flow. Actual workpieces in the process flow are sampled based on the predicted metrology sampling rates.

Abstract: A method for forming a LOCOS layer in a semiconductor device includes steps of oxidizing a high voltage region of the semiconductor device to form a LOCOS layer in the high voltage region; and etching the LOCOS layer according to a pattern.

Abstract: Process exhaust gas is sampled, and the components of the process exhaust gas are analyzed by a Fourier-transform infrared spectroscope (FT-IR) (26). The analysis result is compared with a reference analysis result obtained from an analysis of process exhaust gas generated in an operation performed under reference process conditions. If the amount of a gas component changes to an amount that is outside a predetermined range set around a reference value obtained from the reference analysis result, a signal indicating a process error is outputted. Instead of the output of the signal indicating a process error, the process conditions can be automatically adjusted.

Abstract: A method of fabricating a thin film resistor (100). The resistor material (104), e.g., NiCr, is deposited. A hard mask material (106), e.g., TiW, may be deposited over the resistor material (104). The resistor material (104) and hard mask material (106) are patterned and sputter etched to form the resistor body. For example, a sputter etch chemistry comprising BCl3, Cl2, and Ar may be used to etch the resistor material.

Abstract: Processes for the removal of a layer or region from a workpiece material by contact with a process gas in the manufacture of a microstructure are enhanced by the ability to accurately determine the endpoint of the removal step. A vapor phase etchant is used to remove a material that has been deposited on a substrate, with or without other deposited structure thereon. By creating an impedance at the exit of an etching chamber (or downstream thereof), as the vapor phase etchant passes from the etching chamber, a gaseous product of the etching reaction is monitored, and the endpoint of the removal process can be determined. The vapor phase etching process can be flow through, a combination of flow through and pulse, or recirculated back to the etching chamber.

Abstract: A chemical mechanical polishing pad. The pad contains a water-insoluble matrix and Water-soluble particles dispersed in the water-insoluble matrix material and has a polishing surface and a non-polishing surface on a side opposite to the polishing surface. The pad has a light transmitting area which optically communicates from the polishing surface to the non-polishing surface. The non-polishing surface of the light transmitting area has a surface roughness (Ra) of 10 pm or less.

Abstract: A wet-etch composition may include: peracetic acid (PAA); and a fluorinated acid; a relative amount of the PAA in the composition being sufficient to ensure an etch rate of (P-doped-SiGe):(P-doped-Si) that is substantially the same as an etch rate of (N-doped-SiGe):(N-doped-Si). Such a wet-etch composition is hereafter referred to as a PAA-based etchant and can be used to make, e.g., a CMOS MBCFET, an electrode of a capacitor, etc.

Abstract: In order to reliably remove, by wet etching, a compound containing a metal and silicon, e.g., a silicate (101a) containing hafnium metal, the silicate (101a) is oxidized and then the oxidized silicate (101a) is wet-etched.

Abstract: In an etching method, an etching amount is controlled on the basis of the number of times an etching process is performed under the condition that an etching amount is determined independently of an etching time. Accordingly, the etching can be performed in step-by-step manner, whereby enabling the control of the etching amount at high precision.

Abstract: Methods and systems for preparing a substrate for analysis are provided. One method includes removing a portion of a copper structure on the substrate using an etch chemistry in combination with an electron beam. The etch chemistry is substantially inert with respect to the copper structure except in the presence of the electron beam. Other methods involve forming masking layers on a substrate that will protect the substrate during etching. For example, one method includes exposing a first portion of the substrate to an electron beam. A second portion of the substrate not exposed to the electron beam includes a copper structure. The method also includes exposing the substrate to a fluorine containing chemical. The fluorine containing chemical bonds to the first portion but not the second portion to form a fluorine containing layer on the first portion.

Abstract: In a method of opening of a housing of a plastic-housed electronic module by a laser, the electronic module is protected from the effects of the laser beam and the laser beam is stopped at a suitable time by providing an end point signal detection due to the laser beam impinging on a protective layer. Thereby, after opening the housing, electrical measurements can be carried out on the electronic module.

Abstract: The present invention provides, in one embodiment, a method method of monitoring a process for forming a nitridated oxide gate dielectric. A nitrided oxide dielectric layer is formed on a test substrate (110). The nitrided oxide dielectric layer is exposed to an etch process (120). A change in a property of the nitrided oxide dielectric layer is measured as a function of the etch process (130). Other embodiments advantageously incorporate the method into methods for making semiconductor devices and integrated circuits.

Abstract: A method for forming a trench in a semiconductor silicon substrate. An anti-reflective coating layer and a photoresist layer are formed over the substrate and patterned in accordance with a location for the trench. During the trench etch into the silicon substrate, the etch environment is monitored to detect the material of the anti-reflective coating layer. The etch process is controlled in response to detecting the removal of this material and the known etch rate differential between the anti-reflective coating material layer and the silicon substrate.

Abstract: Methods for detecting the endpoint of a photoresist stripping process provide O for reaction with the photoresist for a wafer to be stripped of photoresist. NO is also supplied for reaction with O not reacted with the photoresist. After substantially all the photoresist is stripped from the wafer, the rate of a reaction of O and NO to form NO2 increases, which increases the intensity of emitted light. An operation of detecting this increase in light intensity signals the endpoint of the photoresist stripping process.

Abstract: A method for controlling a process includes determining incoming state information associated with the process. A plurality of control models associated with the process is provided. A confidence metric is determined for each of the control models based on the incoming state information. The one of the plurality of control models having the highest associated confidence metric is selected. A control action for determining at least one parameter in an operating recipe used to implement the process is generated using the selected control model. A system includes a process tool and a process controller. The process tool is configured to process a workpiece in accordance with an operating recipe.

Abstract: A method for improving fluidic flow for a microfluidic device having a through hole or slot therein. The method includes the steps of forming one or more openings through at least part of a thickness of a substrate from a first surface to an opposite second surface using a reactive ion etching process whereby an etch stop layer is applied to side wall surfaces in the one or more openings during alternating etching and passivating steps as the openings are etched through at least a portion of the substrate. Substantially all of the etch stop layer coating is removed from the side wall surfaces by treating the side wall surfaces using a method selected from chemical treatment and mechanical treatment, whereby a surface energy of the treated side wall surfaces is increased relative to a surface energy of the side wall surfaces containing the etch stop layer coating.

Abstract: A semiconductor device includes a first insulation layer including a first conductor pattern, a second insulation layer formed on the first insulation layer and including a second conductor pattern, and a third conductor pattern formed on the second insulation layer, wherein there is formed a first alignment mark part in the first insulation layer by a part of the first conductor pattern, the third conductor pattern is formed with a second alignment mark part corresponding to the first alignment mark part, the first and second alignment marks forming a mark pair for detecting alignment of the first conductor pattern and the third conductor pattern, the second conductor pattern being formed in the second insulation layer so as to avoid the first alignment mark part.

Abstract: Methods and systems for monitoring a parameter of a measurement device during polishing, damage to a specimen during polishing, a characteristic of a polishing pad, or a characteristic of a polishing tool are provided. One method includes scanning a specimen with a measurement device during polishing of a specimen to generate output signals at measurement spots on the specimen. The method also includes determining if the output signals are outside of a range of output signals. Output signals outside of the range may indicate that a parameter of the measurement device is out of control limits. In a different embodiment, output signals outside of the range may indicate damage to the specimen. Another method includes scanning a polishing pad with a measurement device to generate output signals at measurement spots on the polishing pad. The method also includes determining a characteristic of the polishing pad from the output signals.

Abstract: A method for controlling CD of etch process defines difference between designed dimension and etched dimension as dimensional displacement and defines target value of the dimensional displacement. A plurality of samples are prepared in each group having different exposure ratios. The plurality of samples of each group are etched until etch end point is detected and then over-etched for uniform time interval after detecting the etch end point. Using etch end point and over-etch time, correlation function of the over-etch time to the etch end point time is determined and the over-etch time to the etch end point is determined using the correlation function.

Abstract: A mask layer and a to-be-processed layer are irradiated with light to measure interference light formed of reflected lights from the mask layer and reflected lights from the to-be-processed layer. Thereafter, an interference component brought by the mask layer is removed from the waveform of the measured interference light, thereby calculating the waveform of the interference light brought by the to-be-processed layer. The thickness of the remaining to-be-processed layer is determined on the basis of the calculated waveform of the interference light and the thickness of the remaining to-be-processed layer is compared with a desired thickness thereof. In this way, an end point of processing on the to-be-processed layer is detected.

Abstract: A method for detecting a passivation pinhole includes forming an oxide vertical cavity surface-emitting laser (VCSEL) having an oxidation cavity, forming a passivation layer over a surface of the oxidation cavity, exposing the oxide VCSEL to an etchant vapor, and inspecting the oxide VCSEL for a defect caused by the etchant vapor.

Abstract: A method of fabricating final spacers having a target width comprises the following steps. Initial spacers, each having an initial width that is less than the target width, are formed over the opposing side walls of a gate electrode portion. The difference between the initial spacer width and the target width is determined. A second spacer layer having a thickness equal to the determined difference between the initial width of the initial spacers and the target width is formed upon the initial spacers and the structure. The second spacer layer is etched to leave second spacer layer portions extending from the initial spacers to form the final spacers.

Abstract: Concerning a plurality of wafers which compose one lot, amounts of misalignment between alignment marks of these wafers and alignment patterns transferred on photoresists are measured in advance, and then, a mutual relation between a thickness of an interlayer dielectric film and a value of Wafer Scaling is calculated. When exposure is actually executed, first, an interlayer dielectric film is formed on the alignment marks in a lot and planarized. After that, the thickness of the interlayer dielectric film after planarization is measured. The value of the Wafer Scaling is estimated from an average value of the thicknesses of the interlayer dielectric films in the lot and the above-mentioned mutual relation. Then, photoresists are coated on the interlayer dielectric films in the lot, and the photoresists are exposed while the correction is executed so as to compensate the value of the Wafer Scaling.

Abstract: In a new method of plating metal onto dielectric layers including small diameter vias and large diameter trenches, a surface roughness is created at least on non-patterned regions of the dielectric layer to enhance the uniformity of material removal in a subsequent chemical mechanical polishing (CMP) process.

Abstract: Chemical-mechanical polishing (“CMP”) processes performed on bodies (10), each having areas (16 and 18) of different depression pattern densities, are compared by correlating polishing data accumulated, for one such body, on an area (16) of one pattern density to polishing data accumulated, for that body, on an area of another pattern density for each of the CMP processes.

Abstract: An apparatus and method for etching a feature in a wafer with improved depth control and reproducibility is described. The feature is etched at a first etching rate and then at a second etching rate, which is slower than the first etching rate. An optical end point device is used to determine the etching depth and etching is stopped so that the feature has the desired depth. Two different etching rates provides high throughput with good depth control and reproducibility. The apparatus includes an etching tool in which a chuck holds the wafer to be etched. An optical end point device is positioned to measure the feature etch depth. An electronic controller communicates with the optical end point device and the etching tool to control the tool to reduce the etch rate part way through etching the feature and to stop the etching tool, so that that the feature is etched to the desired depth.

Abstract: An improved CMP controller allows the calculation of the polish time required for removing a patterned layer stack to a desired final thickness, wherein the initial layer thickness of each layer contained in the layer stack is employed. Moreover, a topography factor characterizing the surface structure of the layer stack and a selectivity characterizing the ratio of removal rates between adjacent material layers are used. Furthermore, a state variable of the controller represented by the removal rate of one of the layers may periodically be updated on the basis of the previously calculated polish time and a measurement value of the finally obtained layer thickness. The improved controller is particularly advantageous in the CMP process for STI isolation structures, in which the final thickness of a CMP stop layer, having a significantly reduced removal rate compared to the overlying dielectric layer, has to be precisely controlled.

Abstract: CMP process control array groups are fabricated upon the surface of the wafer for viewing through an optical microscope. The array groups include a plurality of test arrays, where each array includes a plurality of projecting test features. Each of the projecting test features are formed with the same projecting height and have a hard upper surface layer, such as diamond-like-carbon (DLC). All of the projecting test features within an array are formed with the same diameter, and the diameter of projecting test features of a particular array differs from the diameter of projecting test features in another array. The diameters are chosen such that the DLC surface is removed in specifically designed time increments, such as 5 seconds, from array to array, where projecting test features with the DLC surface removed appear as bright white, while the arrays with test features that retain some DLC surface are significantly darker.

Abstract: One aspect of the present invention relates to a system and method for controlling defect formation during a resist strip process. The system includes a reaction chamber comprising a patterned resist layer overlying a semiconductor structure wherein the resist layer is being exposed to a plasma material flowing into the chamber in order to facilitate removing the resist layer from the structure, a plasma-resist particle monitoring system connected to the reaction chamber and programmed to determine a particle count in the reaction chamber during the resist strip process, and a reaction controller coupled to the chamber and to the monitoring system, the reaction controller being programmed to receive particle data from the monitoring system to facilitate determining whether the counted particles in the chamber are within a tolerable limit. The method involves continuing to expose the structure and the chamber to the plasma until an acceptable particle count is obtained.

Abstract: An evaluating pattern includes a conductive pattern formed on a substrate, an insulating layer which is formed on the conductive pattern, a plurality of contact holes formed in a rectangular area through the insulating layer, and a conductive material filled into the contact holes to the conductive pattern.

Abstract: A method of aligning a second layer to a first layer of a semiconductor structure by forming a first layer of a wafer having a distinguished feature via a first etching process that employs a first ionized gas generating machine. Forming a second layer having a circuit pattern via a second etching process that employs a second ionized gas generating machine, wherein the forming the second layer includes minimizing relative shifting between the distinguished feature located at an edge of the wafer for the first layer and the second circuit pattern located at the edge of the wafer for the second layer.

Abstract: A method and apparatus for processing a semiconductor wafer is provided for reducing dimensional variation by feeding forward information relating to photoresist mask CD and profile to adjust the next process the inspected wafer will undergo (e.g., a photoresist trim process). After the processing step, dimensions of a structure formed by the process, such as the CD of a gate formed by the process, are measured, and this information is fed back to the process tool to adjust the process for the next wafer to further reduce dimensional variation. By taking into account photoresist CD and profile variation when choosing a resist trim recipe, post-etch CD is decoupled from pre-etch CD and profile. With automatic compensation for pre-etch CD, a very tight distribution of post-etch CD is achieved. In certain embodiments, the CD and profile measurements, trim, etch processing and post-etch cleaning are performed at a single module in a controlled environment.

Abstract: A method for isolating SAC pads of a semiconductor device, including determining a chemical mechanical polishing process time necessary to isolate the SAC pads a desired amount by referring to a relationship equation between the extent of isolation of the self-aligned contact pads and the chemical-mechanical polishing process time. The chemical mechanical polishing process is performed for the determined process time on the semiconductor device to isolate the self-aligned contact pads the desired amount. The relationship equation is determined using a test semiconductor device.

Abstract: A method for determining an endpoint for etching a layer includes steps of estimating the etch endpoint and, during etch, directing radiant energy at two or more wavelengths onto the layer to be etched, detecting the last intensity maximum reflected at a first wavelength prior to the estimated etch endpoint, and detecting the intensity maximum reflected at a second wavelength first occurring after the last intensity maximum at the first wavelength.

Abstract: A device manufacturing method capable of imaging structures on both sides of a substrate, is presented herein. One embodiment of the present invention comprises a device manufacturing method that etches reversed alignment markers on a first side of a substrate to a depth of 10 ?m, the substrate is flipped over, and bonded to a carrier wafer and then lapped or ground to a thickness of 10 ?m to reveal the reversed alignment markers as normal alignment markers. The reversed alignment markers may comprise normal alignment patterns overlaid with mirror imaged alignment patterns.

Abstract: A method for determining the anti-reflective coating (or bottom anti-reflective coating) over-etch time adjust with real-time process feedback is presented. The critical dimension CDresist of the patterned photoresist is measured and a first wafer with median values chosen (101) from a lot. A first time t★ is found (102) and used to form the desired structure. Using the measured critical dimension of the formed structure on the first wafer a second time tlot is found (104). Finally, an over-etch time t(x) is found and used to etch the remaining wafers in the lot (106).

Abstract: The present invention is directed to a system, method and software product for creating a predictive model of the endpoint of etch processes using Partial Least Squares Discriminant Analysis (PLS-DA). Calibration data is collected from a calibration wafer using optical emission spectroscopy (OES). The data may be non-periodic or periodic with time and periodic signals may be sampled synchronously or non-synchronously. The OES data is arranged in a spectra matrix X having one row for each data sample. The OES data is processed depending upon whether or not it is synchronous. Synchronous data is arranged in an unfolded spectra matrix X having one row for each period of data samples. A previewed endpoint signal is plotted using wavelengths known to exhibit good endpoint characteristics. Regions of stable intensity values in the endpoint plot that are associated with either the etch region or the post-etch region are identified by sample number.

Abstract: The present invention provides, in one embodiment, a method method of monitoring a process for forming a nitridated oxide gate dielectric. A nitrided oxide dielectric layer is formed on a test substrate (110). The nitrided oxide dielectric layer is exposed to an etch process (120). A change in a property of the nitrided oxide dielectric layer is measured as a function of the etch process (130). Other embodiments advantageously incorporate the method into methods for making semiconductor devices and integrated circuits.

Abstract: A system and method for determining endpoint detection in semiconductor wafer planarization is provided. The system and method provide a flexible solution that can compensate for baseline variability induced errors that may otherwise occur in endpoint detection. The system uses an endpoint detection signal that monitors the optical characteristics of the wafer being planarized. The system and method continue to monitor the detection signal during planarization until it meets endpoint criterion that indicates endpoint completion. When the endpoint criterion is reached, a new snapshot is taken from a previous time period and a new baseline is calculated. The endpoint detection signal is then recalculated based upon the new baseline and the recalculated detection signal is again compared to the endpoint criterion. If the recalculated endpoint detection signal again substantially meets the endpoint criterion then the detection of endpoint is confirmed.

Abstract: A method for determining an endpoint of an in-situ cleaning process of a semiconductor processing chamber is provided. The method initiates with providing an optical emission spectrometer (OES) configured to monitor selected wavelength signals. Then, baseline OES threshold signal intensities are determined for each of the selected wavelength signals. Next, an endpoint time of each step of the in-situ cleaning process is determined. Determining an endpoint time includes executing a process recipe to process a semiconductor substrate within the processing chamber. Executing the in-situ cleaning process and recording the endpoint time for each step of the in-situ cleaning process are also included in determining the endpoint time. Then, nominal operating times are established for each step of the in-situ cleaning process. A plasma processing system for executing a two step in-situ cleaning process is also provided.

Abstract: A method for monitoring plasma parameters during a plasma process such as a plasma etching process, comparing the measured plasma parameters to predetermined parameter specifications, and either terminating the plasma process or modifying the plasma process in progress to re-establish the plasma parameters within the parameter specifications. The plasma parameters may be measured by the self-excited electron resonance spectroscopy (SEEKS) technique or by microwave interferometry.

Abstract: The present invention provides a method for determining resist trim times in an etch process. In one embodiment of the invention, the method for determining resist trim times includes obtaining resist profile data and critical dimension (CD) data of a patterned resist layer using a scatterometer, in a step 520, and then obtaining an estimated trim time of the patterned resist layer using the resist profile data and critical dimension data, in steps 530-550.

Abstract: An optical window structure for use in chemical mechanical planarization is provided. The optical window structure includes a polishing pad and an optical window opening in the polishing pad. The optical window structure also includes a molded optical window attached to an underside of the polishing pad, a molded portion of the optical window at least partially protruding into the optical window opening in the polishing pad.

Abstract: A test structure includes a plurality of lines and a plurality of contact openings defined in the lines. A method for determining contact opening dimensions includes providing a wafer having a test structure comprising a plurality of lines and a plurality of contact openings defined in the lines; illuminating at least a portion of the contact openings with a light source; measuring light reflected from the illuminated portion of the contact openings to generate a reflection profile; and determining a dimension of the contact openings based on the reflection profile. A metrology tool adapted to receive a wafer having a test structure comprising a plurality of lines and a plurality of contact openings defined in the lines includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the contact openings. The detector is adapted to measure light reflected from the illuminated portion of the contact openings to generate a reflection profile.

Abstract: A MOS ring oscillator includes a number of serially connected inverter stages with each stage comprising a MOS transistor pair. At least one of the transistors also comprises a scatterometry grate array, which is used during manufacturing of the ring oscillator to obtain scatterometry measurements that allow polysilicon lines of the MOS ring oscillator to have widths of less than 60 nm. A method includes forming at least one grate array above a substrate, illuminating the grate array, measuring light reflected off of the grate array to generate an optical characteristic trace for the grate array, and comparing the generated optical characteristic trace to a target optical characteristic trace that corresponds to a grate array having a desired profile.

Abstract: A processing system and method for chemical oxide removal (COR) is presented, wherein the processing system comprises a first treatment chamber and a second treatment chamber, wherein the first and second treatment chambers are coupled to one another. The first treatment chamber comprises a chemical treatment chamber that provides a temperature controlled chamber, and an independently temperature controlled substrate holder for supporting a substrate for chemical treatment. The substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. The second treatment chamber comprises a heat treatment chamber that provides a temperature controlled chamber, thermally insulated from the chemical treatment chamber. The heat treatment chamber provides a substrate holder for controlling the temperature of the substrate to thermally process the chemically treated surfaces on the substrate.

Abstract: In the method for determining a preceding wafer, at least one semiconductor wafer is determined as a preceding wafer among a plurality of semiconductor wafers constituting one lot. The preceding wafer is then subjected to a given process among a plurality of processes for fabrication of a semiconductor device. The determination of the preceding wafer is based on processing results of an upstream process among the plurality of processes performed for the plurality of semiconductor wafers prior to the given process. After examination of processing results of the given process on the preceding wafer, the given process is performed for the plurality of semiconductor wafers other than the preceding wafer.

Abstract: A method of producing prepolymeric materials from lignin is disclosed. The method uses lignin which has been hydroxyalkyl modified, such that the lignin is substantially non-phenolic and solvent soluble and/or liquid. The modified lignin is reacted with materials which yield prepolymers which may be polymerized according to known methods to produce useful polymers.