Abstract: An integrated circuit system that includes: providing a substrate and a material layer; measuring a parameter of the material layer; and correlating the thickness of an anti-reflective layer to the measured parameter of the material layer for critical dimension control.

Abstract: A method for manufacturing a floating gate includes: forming a tunnel oxide film on a semiconductor substrate; forming a polysilicon layer on a surface of the tunnel oxide film; forming a photosensitive film pattern on a surface of the polysilicon layer; depositing a by-product on the photosensitive film to generate a by-product mask; and using the by-product mask as an etching mask to etch the polysilicon layer, completing fabrication of the floating gate. The polysilicon layer may be etched by a simplified process using a by-product mask so as to fabricate the floating gate, the etch rate of the polysilicon layer may be increased to improve productivity, poly bridge problems may be eliminated, and total amount of a gas used in etching the polysilicon layer may be reduced, resulting in an increase in hardware margin and a decrease in the amount of the gas used in this method.

Abstract: Processes and apparatuses are disclosed for detecting and characterizing SiCOH-based dielectric materials during integrated circuit fabrication. The processes generally include chromatographically analyzing a fluid stream generated during a process employed for device fabrication, e.g., during a wet strip, a chemical mechanical planarization process and the like.

Abstract: A method of fabricating non-volatile memory is provided for memory cells employing a charge storage element with multiple charge storage regions. A first charge storage layer is formed over a tunnel dielectric layer at both a memory array region and an endpoint region of a semiconductor substrate. The first charge storage layer is removed from the endpoint region to expose the tunnel dielectric region. A second charge storage layer is formed over the first charge storage layer at the memory array region and over the tunnel dielectric layer at the endpoint region. When etching the second charge storage layer to form the stem regions of the memory cells, the tunnel dielectric layer provides a detectable endpoint signal to indicate that etching for the second charge storage layer is complete.

Abstract: Dimensions of structures in integrated circuits are shrinking with each new fabrication technology generation. Maintaining control of profiles of structures in transistors and interconnects is becoming more important to sustaining profitable integrated circuit production facilities. Measuring profiles of structures with many elements in integrated circuits, such as MOS transistor gates with recessed regions for Si—Ge epitaxial layers, is not cost effective for the commonly used metrology techniques: SEM, TEM and AFM. Scatterometry is technically unfeasible due to the number of elements and optical constants. The instant invention is a simplified scatterometry structure which reproduces the profiles of a structure to be profiled in a simpler structure that is compatible with conventional scatterometric techniques. A method of fabricating a transistor and an integrated circuit using the inventive simplified scatterometry structure are also disclosed.

Abstract: Methods for processing a substrate in a processing chamber using dual RF frequencies are provided herein. In some embodiments, a method of processing a substrate includes forming a plasma of a polymer forming chemistry to etch a feature into a substrate disposed on a substrate support in a process chamber while depositing a polymer on at least portions of the feature being etched. A low frequency and a high frequency RF signal are applied to an electrode disposed in the substrate support. The method further includes controlling the level of polymer formation on the substrate, wherein controlling the level of polymer formation comprises adjusting a power ratio of the high frequency to the low frequency RF signal.

Abstract: Method for processing at least one spacer structure in a manufacturing process of a semiconductor device, wherein the at least one spacer structure is subjected to at least one etch process step with an isotropic component and the spacer structure comprises at least one point on the surface with a large solid angle opening towards the environment. Method of manufacturing an integrated circuit, including a regional removal of a spacer structure, wherein the removal is determined by a pattern density in the vicinity of the spacer structure.

Abstract: A film structure of a ferroelectric single crystal which can be beneficially used in the fabrication of high-performance electric or electronic parts or devices is prepared by adhering a ferroelectric single crystal plate to a substrate by a conductive adhesive or metal layer, the ferroelectric single crystal plate being polished before or after the adhesion with the substrate.

Abstract: A chemical processing bath and system used in semiconductor manufacturing utilizes a dynamic spiking model that essentially constantly monitors chemical concentration in the processing bath and adds fresh chemical on a regular basis to maintain chemical concentrations at desirable levels. Etch rates and etch selectivities are maintained at desirable levels and contamination from undesirable precipitation is avoided. The system and method automatically compare concentration levels to a plurality of control limits associated with various technologies and identify the technology or technologies that may undergo processing.

Abstract: A system and method is disclosed for measuring a germanium concentration in a semiconductor wafer for manufacturing control of BiCMOS films. Germanium is deposited over a silicon substrate layer to form a silicon germanium film. Then a rapid thermal oxidation (RTO) procedure is performed to create a layer of thermal oxide over the silicon germanium film. The thickness of the layer of thermal oxide is measured in real time using an interferometer, an ellipsometer, or a spectroscopic ellipsometer. The measured thickness of the layer of thermal oxide is correlated to a germanium concentration of the silicon germanium film using an approximately linear correlation. The correlation enables a value of the germanium concentration in the silicon germanium film to be provided in real time.

Abstract: A method for designing an etch recipe is provided. An etch is performed, comprising providing an etch gas with a set halogen to carbon ratio, forming a plasma from the etch gas, and etching trenches over via. Via faceting is measured. The halogen to carbon ratio is reset according to the measured via faceting, where the halogen to carbon ratio is increased if too much faceting is measured and the halogen to carbon ratio is decreased if too little faceting is measured. The previous steps are repeated until a desired amount of faceting is obtained.

Abstract: The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which capacitor container openings are incorporated into DRAM arrays. An exemplary method of forming a reticle includes formation of a radiation-imageable layer over a material. A lattice pattern is then formed within the radiation-imageable layer, with the lattice pattern defining a plurality of islands of the radiation-imageable layer. The lattice-patterned radiation-imageable layer is utilized as a mask while subjecting the material under the lattice-patterned layer to an etch which transfers the lattice pattern into the material. The etch forms a plurality of pillars which extend only partially into the material, with the pillars being spaced from one another by gaps. The gaps are subsequently narrowed with a second material which only partially fills the gaps.

Abstract: A semiconductor manufacturing apparatus includes a processing chamber for performing a manufacturing processing on a wafer. A gas supply line for introducing a purge gas is connected to an upper portion of the processing chamber, a valve being installed on the gas supply line. A rough pumping line with a valve is connected to a lower portion of the processing chamber. Installed on the rough pumping line are a dry pump for exhausting a gas in the processing chamber and a particle monitoring unit for monitoring particles between the valve and the dry pump. In the semiconductor manufacturing apparatus, after the valve is opened, the purge gas is supplied to apply physical vibration due to shock wave in the processing chamber so that deposits are detached therefrom to be monitored as particles.

Abstract: A method for manufacturing an optical device includes the steps of: forming a first multilayer film, including forming a first mirror above a substrate, forming an active layer above the first mirror, forming a second mirror above the active layer, forming a semiconductor layer on the second mirror, and forming a sacrificial layer on the semiconductor layer; conducting a first examination step of conducting a reflectance examination on the first multilayer film; forming a second multilayer film by removing the sacrificial layer from the first multilayer film; conducting a second examination step of conducting a reflection coefficient examination on the second multilayer film; and patterning the second multilayer film to form a surface-emitting laser section having the first mirror, the active layer and the second mirror, and a diode section having the semiconductor layer, wherein the sacrificial layer is formed to have an optical film thickness of an odd multiple of ?/4, where ? is a design wavelength of ligh

Abstract: An electronic device can include electronic components and an insulating layer overlying the electronic components. The electronic device can also include a capacitor overlying the insulating layer, wherein the capacitor includes a first electrode and a second electrode. The second electrode can include an opening, wherein from a top view, a defect lies within the opening. In another aspect, a process of forming an electronic device can include forming a first capacitor electrode layer over a substrate, forming a dielectric layer over the first capacitor electrode layer, and forming a second capacitor electrode layer over the dielectric layer. The process can also include detecting a defect and removing a first portion of the second capacitor electrode layer corresponding to the defect, wherein a second portion of the second capacitor electrode layer remains over the dielectric layer.

Abstract: Systems and methods for plasma processing of microfeature workpieces are disclosed herein. In one embodiment, a method includes generating a plasma in a chamber while a microfeature workpiece is positioned in the chamber, measuring optical emissions from the plasma, and determining a parameter of the plasma based on the measured optical emissions. The parameter can be an ion density or another parameter of the plasma.

Abstract: A manufacturing apparatus for a semiconductor device, treating a SiN film formed on a wafer with phosphoric acid solution, including a processing bath to store phosphoric acid solution provided for treatment of the wafer, a control unit for calculating integrated SiN etching amount of the phosphoric acid solation, determining necessity of quality adjustment of the phosphoric acid solution, based on correlation between the integrated SiN etching amount calculated and etching selectivity to oxide film, and calculating a quality adjustment amount of the phosphoric acid solution as needed, and also including a mechanism to adjust the quality of the phosphoric acid solution based on the quality adjustment amount calculated.

Abstract: A system and method for controlling resistivity uniformity in a Copper trench structure by controlling the CMP process is provided. A preferred embodiment comprises a system and a method in which a plurality of CMP process recipes may be created comprising at least a slurry arm position. A set of metrological data for at least one layer of the semiconductor substrate may be estimated, and an optimum CMP process recipe may be selected based on the set of metrological data. The optimum CMP process recipe may be implemented on the semiconductor substrate.

Abstract: For providing control of two-step or a multi-step deposition process, a method and a corresponding deposition system is provided comprising providing a deposition process having at least two sub-processes employing different sets of process parameters, wherein each set of process parameters comprises at least one process parameter. The method comprises controllably generating an actual value for at least one first process parameter by taking into account at least one previous value of the respective first process parameter, wherein each first process parameter is a process parameter of said at least two sets of process parameters.

Abstract: A structure for independently supporting a wafer and a mask in a processing chamber is provided. The structure includes a set of extensions for supporting the wafer and a set of extensions supporting the mask. The set of extensions for the wafer and the set of extensions for the mask enable independent movement of the wafer and the mask. In one embodiment, the extensions are affixed to an annular ring which is capable of moving in a vertical direction within the processing chamber. A processing chamber, a mask, and a method for combinatorially processing a substrate are also provided.

Abstract: Methods for removing poly silicon. In one example embodiment, a method for removing poly silicon that is formed on a silicon wafer includes the steps of growing the poly silicon as a silicon oxide through a thermal oxidation process and removing the silicon oxide using an etching solution.

Abstract: Disclosed herein is a fabrication method for a semiconductor device, including a lithography step of connecting a plurality of mask patterns to each other to form a pattern image of an area greater than the size of the mask patterns. The lithography step includes the steps of: assuring an overlapping exposure region to be exposed in an overlapping relationship by both of two mask patterns to be connected to each other, carrying out exposure transfer of the pattern portions of the two mask patterns to the overlapping exposure region to form a first measurement mark and a second measurement mark in the overlapping exposure region, and carrying out positional displacement measurement of pattern connection by the two mask patterns based on a manner of combination of main marks and sub marks of the measurement marks formed in the overlapping exposure region.

Abstract: A method for improving fluidic flow for a microfluidic device having a through hole or slot therein. The method includes the steps of forming one or more openings through at least part of a thickness of a substrate from a first surface to an opposite second surface using a reactive ion etching process whereby an etch stop layer is applied to side wall surfaces in the one or more openings during alternating etching and passivating steps as the openings are etched through at least a portion of the substrate. Substantially all of the etch stop layer coating is removed from the side wall surfaces by treating the side wall surfaces using a method selected from chemical treatment and mechanical treatment, whereby a surface energy of the treated side wall surfaces is increased relative to a surface energy of the side wall surfaces containing the etch stop layer coating.

Abstract: Disclosed is a plasma monitoring method for detecting the amount of atomic radicals generated by dissociation of a molecular raw material gas during a plasma processing conducted by introducing the molecular raw material gas and a rare gas into a process atmosphere, wherein the amount of the atomic radicals is predicted from the dissociation degree of the molecular raw material gas determined from the partial pressure of the molecular raw material gas in the process atmosphere, the luminous intensity of the rare gas, and the partial pressure of the rare gas in the process atmosphere, whereby the amount of the specific atomic radicals can be monitored easily and accurately.

Abstract: A method includes illuminating at least a portion of a first grid including a first plurality of stressed material regions formed at least partially in a semiconducting material. Light reflected from the illuminated portion of the first grid is measured to generate a first reflection profile. A characteristic of the first plurality of stressed material regions is determined based on the first reflection profile. A test structure includes a first plurality of stressed material regions recessed with respect to a surface of a semiconductor layer and defining a first grid. A first plurality of exposed portions of the semiconductor layer is disposed between each of the first plurality of stressed material regions.

Abstract: The method of manufacturing a semiconductor device has deciding an amount of a correction of a mask pattern for a size of an active region of a semiconductor substrate, correcting the mask pattern on the basis of the decided amount of the correction, and exposing a resist film by using an exposure mask having the corrected mask pattern.

Abstract: A method for forming a semiconductor laser chip is provided that can suppress layer discontinuity and simultaneously reduce fabrication variations in the light radiation angle in the horizontal direction. The method includes a step of forming, on an n-type GaAs substrate, a semiconductor element layer composed of a plurality of semiconductor layers including an etching marker layer, a step of forming, in a contact layer in the semiconductor element layer, a depressed portion having a depth not reaching the etching marker layer, and a step of forming a ridge portion by etching the semiconductor element layer by dry etching while monitoring, with laser light, the etching depth in the bottom region of the depressed portion.

Abstract: An advanced process control (APC) method for semiconductor fabrication is provided. A first substrate and a second substrate are provided. The first substrate and the second substrate include a dielectric layer. A first etch process parameter for the first substrate is determined. A trench is etched in the dielectric layer of the first substrate using the first etch process parameter. At least one aspect of the etched trench of the first substrate is measured. A second etch process parameter for the second substrate is determined using the measured aspect of the etched trench of the first substrate. A planarization process parameter for the first substrate is determined also using the measured aspect of the etched trench of the first substrate.

Abstract: When a multi-layer structure is formed by forming the interconnect trenches or via holes having different patterns in a plurality of insulating films, an anti-reflective film and an upper resist film are stacked in this order over an insulating interlayer, and the anti-reflective film is etched through the upper resist film used as a mask, wherein the anti-reflective film is etched while varying a value of at least one etching condition correlative to ?(L2?L1), expressing dimensional shift of width L2 of opening of the recess formed in the insulating film, with respect to width L1 of opening of the upper resist film, so as to reduce the dimensional shift ?(L2?L1) as the aperture ratio of the opening to be formed in the upper resist film increases, depending on the aperture ratio.

Abstract: Embodiments herein present a method for a feed forward suicide control scheme based on spacer height controlling pre-clean time. The method forms field effect transistor gates over a substrate and then forms spacers on the gates. Next, the method measures the spacers using an atomic force microscope to determine a measured spacer height. The method then conducts a pre-cleaning etch, wherein a duration of the pre-cleaning is adjusted according to the measured spacer height. If the measured spacer height is below a predetermined amount, the duration of the pre-cleaning is reduced; and, if the measured spacer height is above a predetermined amount, the duration of the pre-cleaning is increased.

Abstract: During the patterning of respective contact etch stop layers having a different type of intrinsic stress, the deposition of an etch indicator layer between the first and the second contact etch stop layer may be omitted in order to avoid any undue effects of this layer during the subsequent processing. Local removal of the second stressed layer may be performed on the basis of an etch time controlled etch process, which in some aspects may include the provision of an etch indicator material, wherein feed forward and feed back measurement data may be used in an appropriately designed process controller.

Abstract: A method for forming bumps is disclosed. First, a substrate having an adhesive, a barrier, and a wetting layer thereon is provided. Next, a patterned photoresist is formed on the wetting layer, in which the patterned photoresist includes at least one opening for exposing a portion of the wetting layer. Next, a solder is deposited in the opening, and a stripping process is performed to remove the patterned photoresist. Next, a first etchant is utilized to perform a first etching process for etching a portion of the wetting and barrier layers by utilizing the solder as a mask, in which the first etchant is selected from the group consisting of: sulfuric acid, phosphoric acid, ferric chloride, ammonium persulfate, and potassium monopersulfate. Next, a second etchant is utilized to perform a second etching process removing a portion of the adhesive layer, and a reflow process is performed to form a bump.

Abstract: A semiconductor device and a method for controlling its patterns is described where the electrical characteristics of the patterns formed by a double patterning process may be individually controlled responsive to critical dimensions (CDs) of the patterns. The method includes controlling two or more patterns having different CDs to optimally operate the patterns. The patterns may be individually controlled by signals provided to the patterns on the basis of the pattern's CDs. The signals may be controlled by controlling the magnitudes or the application time of the signals provided to the respective patterns.

Abstract: A method of controlling a recess etch process for a multilayered substrate having a trench therein and a column of material deposited in the trench includes determining a first dimension from a surface of the substrate to a reference point in the substrate by obtaining a measured net reflectance of at least a portion of the substrate including the trench, computing a modeled net reflectance of the portion of the substrate as a weighted incoherent sum of reflectances from n?1 different regions constituting the portion of the substrate, determining a set of parameters that provides a close match between the measured net reflectance and the modeled net reflectance, and extracting the first dimension from the set of parameters; computing an endpoint of the process as a function of the first dimension and a desired recess depth measured from the reference point; and etching down from a surface of the column of material until the endpoint is reached.

Abstract: By evaluating a status signal on the basis of a fault detection classification mechanism in an electrochemical etch tool, a corresponding failure status of the tool may be obtained for each single substrate, thereby significantly reducing the risk of significant yield loss compared to conventional strategies. The fault detection and classification mechanism may be advantageously applied to the electrochemical removal of underbump metallization layers during the formation of solder bump structures.

Abstract: Recessing a trench using feed forward data is disclosed. In one embodiment, a method includes providing a region on a wafer including a trench area that includes a trench and a field area that is free of any trench, and a material applied over the region so as to fill the trench in the trench area and form a step between the trench area and the field area; etching to partially etch the trench; determining a target etch duration (tD) for etching to the target depth (DT); and etching the trench to the target depth (DT) for a period approximately equal to the target etch duration (tD). The target etch duration tD may be fed forward for recessing another trench to the target depth DT. The method does not require a send ahead wafer, is fully compatible with conventional automated processes and provides in-situ etch time correction to each wafer.

Abstract: Methods of etching a semiconductor substrate may include providing a first gas that is chemically reactive with respect to the semiconductor substrate, and while providing the first gas, providing a second gas different than the first gas. More particularly, a molecule of the second gas may include a hydrogen atom, and the second gas may lower a temperature at which the first gas chemically reacts with the semiconductor substrate. The mixture of the first and second gases may be provided adjacent the semiconductor substrate to etch the semiconductor substrate.

Abstract: Rinsing nozzles 310a to 310e are moved on a wafer W while they are discharging rinsing solution 326. At that point, discharging openings 317a to 317e are contacted to developing solution 350 coated on the wafer W or rinsing solution 326 on the wafer W. Thus, the impact against the wafer W can be suppressed. As a result, pattern collapse can be prevented. In addition, a front portion of the developing solution 350 can push away the developing solution 350.

Abstract: A method of fabricating a semiconductor device according to an embodiment of the present invention includes: forming through a first material film a second material film above a semiconductor substrate; patterning the second material film to have a predetermined pattern; trimming a width of the second material film thus patterned by performing etching; transferring a pattern of the second material film having the trimmed width on the first material film by etching the first material film; measuring a width of the first material film thus etched; and adjusting the width of the first material film to a predetermined width based on the width of the first material film thus measured.

Abstract: A semiconductor device is fabricated to include one or more sets of calibration patterns used to measure line pitch and line focus.

Abstract: The surface of a gallium nitride single crystal substrate is processed, e.g., comprising steps by planarizing the top side and the bottom side of a gallium nitride original substrate positioned on a support bed; radiating light having wavelengths ranging from 370 to 800 nanometers (nm) onto the planarized gallium nitride original substrate; measuring transmittance of the gallium nitride original substrate; and confirming whether the transmittance is within the range of 65 to 90%. A gallium nitride single crystal substrate obtained through the method of processing the surface has high transmittance ranging from 65 to 90% measured using light having wavelengths of 370 to 800 nm. The thickness ratio (DLa/DLb) of the damage layers on the both sides of the gallium nitride single crystal substrate can be obtained within the range of 0.99 to 1.01.

Abstract: A method and system for reducing the variation in film thickness on a plurality of semiconductor wafers having multiple deposition paths in a semiconductor manufacturing process is disclosed. A film of a varying input thickness is applied to semiconductor wafers moving through various film deposition paths. The deposition path of each of the semiconductor wafers is recorded. A subset of semiconductor wafers is measured and an average film input thickness corresponding to each of the film deposition paths is calculated. If semiconductor wafer in the specific film deposition path does not have measurement data, by default it uses historical measurement data. The average film input thickness of the deposition path corresponding to a given semiconductor wafer is then used to modify the recipe of a process tool, such as a Chemical Mechanical Planarization (CMP) Process Tool. An improved manufacturing process is achieved without the use of excess measurements.

Abstract: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.

Abstract: A method of planar etching of dissimilar materials with a Focused Ion Beam (FIB) system such as the OptiFIB manufactured by Credence Systems. The method includes adjusting the selectivity between the two materials, which varies when the ratio of the assisting chemistry pressure to the ion dose rate changes. This method can be used in such applications as FIB circuit edit, failure analysis, and cross sectioning.

Abstract: Disclosed is a method for monitoring an edge bead removal process for a copper metal interconnection. The method includes the steps of (a) forming a copper metal layer on a semiconductor wafer, (b) performing the edge bead removal (EBR) process of removing the copper metal layer formed in an edge area of the semiconductor wafer, and (c) determining whether copper residues exist by measuring a reflection coefficient Rc of the copper metal layer formed in a center area of the semiconductor wafer and a reflection coefficient (Rb) in the edge area of the semiconductor wafer which is subject to the edge bead removal (EBR) process.

Abstract: Before forming a gate trench, a buried oxide film forming an element isolation region is selectively etched, thereby exposing a side-wall shoulder portion, having a rounded shape, of an active region. This reduces a range in which an end portion of the buried oxide film serves as a mask when forming the gate trench. After this, the gate trench is formed. This makes it possible to reduce silicon that remains on a side wall of the element isolation region adjacent to the gate trench.

Abstract: A method for configuring a plasma cluster tool is disclosed. The method includes generating a key file from option specifications, the key file encapsulating configuration restrictions specifically imposed on the plasma cluster tool. The method also includes generating at least one system-wide configuration file and at least one component-level configuration file using the key file. The method additionally includes generating run-time executable objects from a database of option definition files, the at least one system-wide configuration file and the at least one component-level configuration file. Furthermore, the method includes employing the run-time executable objects to configure the plasma cluster tool.

Abstract: A system and method is disclosed for measuring a germanium concentration in a semiconductor wafer for manufacturing control of BiCMOS films. Germanium is deposited over a silicon substrate layer to form a silicon germanium film. Then a rapid thermal oxidation (RTO) procedure is performed to create a layer of thermal oxide over the silicon germanium film. The thickness of the layer of thermal oxide is measured in real time using an interferometer, an ellipsometer, or a spectroscopic ellipsometer. The measured thickness of the layer of thermal oxide is correlated to a germanium concentration of the silicon germanium film using an approximately linear correlation. The correlation enables a value of the germanium concentration in the silicon germanium film to be provided in real time.

Abstract: A treatment method of a semiconductor wafer includes treating the semiconductor wafer in a first solution having at least one kind of an oxidative acid and an oxidizing agent and treating the semiconductor wafer in a second solution having at least one of HF and NH4F.

Abstract: The variability of immersion processes for treatment of semiconductor devices can be significantly lowered by initiating the termination of a treatment process according to a predetermined treatment termination protocol in a manner that takes into account the contribution of, in particular, the treatment that is carried out during the period of time in the treatment process in which the treatment process is being terminated. In a preferred embodiment, conditions that indicate the progress of the treatment on a real time basis are monitored, and the timing of the initiation of the termination process is additionally based on the calculated amount of treatment and treatment rate of the process in progress.