Abstract: A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.

Abstract: A semiconductor memory device may include: a memory cell region including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines; and a refresh control block suitable for performing a first refresh operation onto the plurality of the word lines in response to a refresh signal, counting the number of active signals that are inputted between at least two neighboring refresh signals and when the counted number of the active signals is equal to or greater than a reference number, performing a second refresh operation onto a word line corresponding to a target address.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a command/address signal. The second semiconductor device extracts an active signal, a pre-charge signal, and addresses from the command/address signal, performs an active operation on a memory cell corresponding to the addresses, and performs a refresh operation on the memory cell corresponding to counting signals generated by counting a number of pulses in a refresh signal.

Abstract: On-chip instruction RAM is leveraged as an extension of on-chip data RAM during normal use of a modified Harvard Architecture processor. Unused space in an instruction RAM is detected in a modified Harvard Architecture processor. During operation of the processor this unused space is used to load and store data normally loaded and stored in an on-chip data RAM. A performance penalty associated with swapping out to external memory is reduced. The type of data stored in the unused portion of the instruction RAM may be selected to optimize performance. In one implementation, the unused space in the instruction RAM is used to load and store only a single type of data, such as heap, stack, initialized or uninitialized data.

Abstract: Various embodiments comprise methods and apparatuses for selecting a randomly-chosen seed row from among a stream of available data in a memory system. A refresh operation is then performed on at least one selected row of memory in the memory system based on the randomly-chosen seed row. Additional apparatuses and methods are described.

Abstract: In one embodiment, a method for updating a DRAM memory array is disclosed. The method comprises: a) transitioning the DRAM memory array from an idle state to a self-refresh state after a period of inactivity; b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry; and c) during the refresh, performing an Error Correction Code (ECC) scrub operation of selected bits in an activated row of the DRAM memory array.

Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.

Abstract: A resistor calibration system includes a reference resistor, a first control circuit, a second control circuit, a comparator, a multiplexer and a de-multiplexer. The first control circuit calibrates a first resistor and a duplicated first resistor. The second control circuit calibrates a second resistor. The comparator includes a first input terminal receiving a reference voltage, a second input terminal and an output terminal. The multiplexer includes a first input terminal coupled to the reference resistor and the first resistor, a second input terminal coupled to the duplicated first resistor and the second resistor, and an output terminal coupled to the second input terminal of the comparator. The de-multiplexer includes an input terminal coupled to the output terminal of the comparator, a first output terminal coupled to the first control circuit, and a second output terminal coupled to the second control circuit.

Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.

Abstract: A method of refreshing a memory device includes performing normal refresh operations on memory cell rows in response to a refresh command and performing self-refresh operations on the memory cell rows according to a refresh clock signal in response during a self-refresh mode of the memory device between a self-refresh enter command and a self-refresh exit command. The refresh clock signal has a first self-refresh cycle before the self-refresh begins and a second self-refresh cycle, which may be longer than the first self-refresh cycle, after the self-refresh begins. In some examples, no self-refresh may be performed by the memory device during a self-refresh mode.

Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

Abstract: According to one embodiment of the invention, an integrated circuit device comprises one or more processor cores and a control unit coupled to the processor core(s). The control unit is adapted to control an operating frequency of at least one processor core based on an estimated activity level in lieu of a power level. The estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to that integrated circuit device.

Abstract: Described herein are system and methods for mitigating index contention issues in databases. The database server may generate additional storage locations to prevent overloading one or more current storage locations. A variety of database conditions may be used to trigger an increase or decrease in storage locations. In one embodiment, more storage locations may be generated when the amount of data records waiting to be written at a storage location exceeds or equals a threshold amount. Likewise, the database server may reduce the amount of current storage locations when the amount of data records is less than a threshold amount. The record identifiers may incorporate a location reference for their designated storage location. The reference may be a string that includes numbers, letters, or a combination thereof.

Abstract: In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device.

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

Abstract: A memory device may include: a target address generator suitable for storing one or more addresses for each time a refresh command is skipped, and for generating one or more target addresses for each of the stored addresses during a burst refresh operation; and a refresh controller suitable for refreshing a word line selected among a plurality of word lines of a memory bank based on the generated one or more target addresses during a target refresh operation.

Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

Abstract: The present invention discloses an erasure circuitry, a method for erasing a volatile memory, a volatile memory and a processing unit coupled with an operating system, where the erasure circuitry is adapted to erase the volatile memory at occurrence of a predefined event. The erasure circuitry includes a control unit for initiating a dummy operation to randomize data of one or more memory cells at the occurrence of a predefined event. The control unit is adapted to receive the addresses of the memory blocks from a processing unit via an operating system.

Abstract: A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die.

Abstract: Various embodiments of methods and systems for temperature compensated memory refresh (“TCMR”) of a dynamic random access memory (“DRAM”) component are disclosed. Embodiments of the solution leverage a memory refresh module located within a memory subsystem to apply a refresh power supply received from a source on the SoC. Advantageously, even though the refresh power supply is received from a source on the SoC according to a certain delivery rate that may not be optimal for each and every bank in the DRAM component, embodiments of the solution are able to apply an effective refresh power supply rate to each bank according to its optimal cycle.

Abstract: A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.

Abstract: An apparatus, method, and computer program for maintaining access times in a data processing system, wherein the data processing system comprises a plurality of storage devices, the apparatus including: a receive component, for receiving a command or an availability message, wherein an availability message indicates whether the storage device is available; an evaluate component for evaluating a plurality of first relationships between the storage devices and a plurality of first values, wherein each of the first values indicates whether a related storage device is a redundant; a send component, for sending a power message to one or more of the storage devices; and an update component for updating a second relationship between the redundant storage device and a plurality of second values, wherein each of the second values indicates whether a related redundant storage device is available.

Abstract: A self-refresh control device may be provided. The self-refresh control device may include a refresh signal output circuit configured to generate self-refresh signals with an oscillator and provide a refresh signal. The self-refresh control device may begin a self-refresh mode in response to a clock enable signal and a self-refresh signal within a self-refresh entry period, and may prevent performance of a new self-refresh operation by delaying an additional self-refresh signal until after the self-refresh entry period has ended.

Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

Abstract: Embodiments of the present invention relate to a latch circuit (L20) which latches a data mask signal (DM) in response to a one-shot signal (NS), and changes the data mask signal (DM) to an active level in response to an error signal (ERR), which indicates that an error is present in write data (DQ), being at an active level; a buffer circuit (BF2) which outputs the data mask signal (DM) that has been latched by the latch circuit (L20), said data mask signal (DM) being output in response to a write clock signal (WCLK2); and a main amplifier (80) which outputs the write data (DQ) to an internal circuit on the condition that the data mask signal (DM) which has been output from the buffer circuit (BF2) is at an inactive level. The present invention can prevent the writing of erroneous write data, and is capable of preventing increased chip surface area.

Abstract: Aspects of the disclosure provide an integrated circuit that includes a first memory controller, a second memory controller and at least a functional circuit coupled to the second memory controller. The first memory controller is configured to control memory access to a first memory. The second memory controller is configured to control memory access to a second memory that is able to be turned on/off. The functional circuit is configured to operate based on the second memory. The second memory controller is configured to cause the second memory to be turned on when an application requires an operation of the functional circuit.

Abstract: Methods and apparatus enabling a wireless network to optimize paging channel operation, based on mobile device context information. In one embodiment, the wireless network is a cellular network (e.g., LTE-Advanced), and both base stations and cellular user devices dynamically exchange and maintain a paging agreement. The paging agreement limits the paging channel operation, thereby minimizing unnecessary scanning and usage of irrelevant radio resources. Such paging mechanisms are limited to the air interface between the base station and the mobile device, and are compatible with existing legacy devices and network entities. Networks with appropriately enabled user devices may improve their resource utilization. Base stations may advantageously reclaim freed-up cellular resources to support other services.

Abstract: A memory circuit includes: a bistable circuit (30) that writes data; nonvolatile elements (MTJ1, MTJ2) that store the data written in the bistable circuit into the nonvolataole element in a nonvolatile manner, and restore the data stored in a nonvolatile manner into the bistable circuit; and a determining unit (50) that does not store the data written in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is the same as the data in the nonvolatile elements, but stores the data in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is not the same as the data in the nonvolatile elements.

Abstract: It is an object of the invention to provide a memory architecture that can handle data interleaving efficiently. This and other objects are achieved by the system according to the invention. The data handling system, is configured for receiving at an input a plurality of commands. The system comprises: a plurality of memory banks; a distributor connected to the input and having a plurality of distributor outputs. Each specific one of the plurality of memory banks (106) is connected to a specific one of the plurality of distributor outputs. The distributor comprises a permutator for designating for each specific command a specific distributor output. The distributor distributes the specific command to the specific designated distributor output. The permutator has a control input and the designating is reconfigurable under the control of reconfiguration data received at the control input.

Abstract: Some of the embodiments of the present disclosure provide a method comprising: storing volatile data in nonvolatile memory; over a time interval, periodically refreshing the volatile data by (i) reading the volatile data from the nonvolatile memory and (ii) rewriting the volatile data to the nonvolatile memory; determining a number of errors in the volatile data that is read during the periodic refresh of the volatile data; and based, at least in part, on the number of errors that is determined, modifying the time interval. The method may also comprise decreasing the time interval if the number of errors is determined to be greater than an error threshold value.

Abstract: Controlling accesses to target devices such as disk drives by modifying the duty cycle profile of those devices to improve device reliability is disclosed. The utilization of a target device is monitored, and if a device is being overused, that device is given a rest period by reserving it for a special initiator that does not send any commands to the device for a certain period of time. This reduced utilization has the effect of increasing the reliability of the target device. This period of time also adds a delay to the processing of commands for the target device being overutilized so that the device becomes less responsive. This performance penalty creates pressure on system administrators to reduce the number of commands sent to that target device and/or move data to proper devices (that can handle the high number of accesses).

Abstract: On the fly switching from one memory device refresh rate to another is provided. Control logic associated with the memory device detects a condition to switch from a currently-applied refresh rate to a different refresh rate. In response to the condition, the refresh rate is dynamically switched. The switching does not require a change of a mode register. Thus, a refresh rate for the memory device can be dynamically changed on the fly.

Abstract: Accessing data of varying-sized quanta in non-volatile memory provides improved storage efficiency in some situations. For example, a Solid-State Disk (SSD) controller receives (e.g. uncompressed) data from a computing host (e.g. a disk write command), compresses the data, and stores the compressed data into non-volatile (e.g. flash) memory. In response to a subsequent request from the host (e.g. a disk read command), the SSD controller reads and uncompresses the compressed data from the memory. The compressed data is stored in the memory according to varying-sized quanta, due to, e.g., compression algorithm, operating mode, and compression effectiveness on various data. The SSD controller uncompresses the data in part by consulting an included map table to locate header(s) stored in the memory, parsing the header(s) to locate appropriate (compressed) data stored in the memory, and uncompressing the appropriate data from the memory to produce the uncompressed data.

Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.

Abstract: A refresh address generator may include a lookup table including a first portion storing a first group of addresses associated with a first data retention time, and a second portion storing a second group of addresses associated with a second data retention time different from the first data retention time, wherein the addresses of the first portion are more frequently accessed than the addresses of the second portion to refresh the memory cells corresponding to the addresses. Systems and methods may also implement such refresh address generation.

Abstract: In a method of refreshing in a memory device having a plurality of pages, a candidate refresh address corresponding to a page scheduled to be refreshed after a monitoring period is generated. Whether an active command is processed for the candidate refresh address is monitored during the monitoring period. If an active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh for that page is skipped. If no active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh operation is performed.

Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.

Abstract: A smart refresh device includes an address control block configured to determine whether a specific row address is a row hammer address, and invert a first row hammer address and perform an addition/subtraction of an address; a repair control block configured to determine whether the row hammer address is a repaired address and output a stored repair address as a second repair control signal; a repair address storage block configured to store an output address of the address control block and output a stored address as a latch address; a fuse block configured to output a repair signal representing information on a repair address to the repair control block, and output a decoding signal according to the latch address; and an operator configured to add and subtract the decoding signal according to an addition signal and a subtraction signal.

Abstract: A memory includes a plurality of word lines, a target address generation unit generating one or more target addresses by using a stored address, a refresh control section activating a refresh signal in response to a refresh command that is periodically inputted and periodically activating the refresh signal in a self-refresh mode, a target refresh control section activating a target refresh signal when the refresh signal is activated M times, wherein the M is a natural number, and deactivating the target refresh signal in the self-refresh mode, and a row control section sequentially refresh a plurality of first word lines in response to the refresh signal and refreshing a second word line corresponding to the target address in response to the refresh signal when the target refresh signal is activated.

Abstract: A storage system and method for interleaving a plurality of logical sectors in the storage system is disclosed. The method includes: dividing each logical sector into a predetermined number of slices; sequentially indexing the logical sectors, wherein each logical sector is identified by a logical sector index; sequentially indexing the predetermined number of slices in each logical sector, wherein each slice of the predetermined number of slices is identified by a slice index within each logical sector; and interleaving the logical sectors according to a slice interleaving process. The interleaving step further includes: a) identifying a first indexed slice of a first indexed logical sector as an initial slice; and b) identifying a subsequent slice by advancing the slice index to a subsequent index in the slice index sequence and advancing the logical sector index to a subsequent index in the logical sector index sequence.

Abstract: A method can include determining at least one use characteristic for the memory cells comprising a solid electrolyte, the use characteristic corresponding to a number of times the memory cells have been programmed to at least one impedance level; and adjusting a read threshold level for the memory cells based on at least the use characteristic, the read threshold level determining data values stored in the memory cells in a read operation.

Abstract: Dynamic memory systems require each memory cell to be continually refreshed. During a memory refresh operation, the refreshed memory cells cannot be accessed by a memory read or write operation. In multi-bank dynamic memory systems, concurrent refresh systems allow memory refresh circuitry to refresh memory banks that are not currently involved in memory access operations. To efficiently refresh memory banks and advanced round robin refresh system refreshes memory banks in a nominal round robin manner but skips memory banks blocked by memory access operations. Skipped memory banks are prioritized and then refreshed when they are no longer blocked.

Abstract: In a particular embodiment, a device includes memory address remapping circuitry and a remapping engine. The memory address remapping circuitry includes a comparison circuit to compare a received memory address to one or more remapped addresses. The memory address remapping circuitry also includes a selection circuit responsive to the comparison circuit to output a physical address. The physical address corresponds to a location in a random-access memory (RAM). The remapping engine is configured to update the one or more remapped addresses to include a particular address in response to detecting that a number of occurrences of errors at a particular location satisfies a threshold.

Abstract: Provides is a multi-chip package including a plurality of semiconductor memory devices. Each of semiconductor memory devices includes a register and a control circuit. The register is configured to store start sequence information representing start of execution of a refresh operation in the multi-chip package. The control circuit is configured to control start of the execution of the refresh operation in response to the start sequence information stored in the register. Since the start of the execution of the refresh operation is performed in sequence of respective semiconductor memory devices according to the start sequence information stored in the register, consumption of peak current may be reduced in a power saving mode.

Abstract: A memory system includes a memory unit and a memory controller. The memory unit includes a plurality of memory banks, wherein an information stored in a memory bank is accessed via a word line and a bit line. The memory controller is configured to limit repetitive accessing of a same word line or a same bit line so that the number of consecutive access is less than a predetermined critical value.

Abstract: An approach for saving power in a memory subsystem that uses memory access idle timer to enable low power mode and memory scrub operation within computing system has been provided. The computing system determines that a memory subsystem is switched out of low power operation mode due to a memory scrub operation. In addition, the computing system bypasses the low power operation mode of an idle timer of the memory subsystem such that the memory subsystem is returned to the low power operation mode upon completion of the memory scrub operation. The computing system further sets a scrub flag of the memory subsystem to a high state, and clears the scrub flag to a low state to track if the idle timer should be bypassed.

Abstract: An approach for saving power in a memory subsystem that uses memory access idle timer to enable low power mode and memory scrub operation within computing system has been provided. The computing system determines that a memory subsystem is switched out of low power operation mode due to a memory scrub operation. In addition, the computing system bypasses the low power operation mode of an idle timer of the memory subsystem such that the memory subsystem is returned to the low power operation mode upon completion of the memory scrub operation. The computing system further sets a scrub flag of the memory subsystem to a high state, and clears the scrub flag to a low state to track if the idle timer should be bypassed.

Abstract: Signal processor for a GNSS receiver, in particular a GPS receiver, characterized by the use of un-refreshed volatile dynamic memory as a storage element for real-time digital data. The invention takes advantage from the fact that many memory units are used to store real-time data and are constantly overwritten at a rate which can conveniently be shorter than a mean retention time of a DRAM cell. Moreover several memories are used to store noise-dominated data which are then statistically analyzed in a way that can tolerate a small rate of retention errors. Thus the automatic refresh circuitry can be disposed of without adverse effect.

Abstract: Systems and methods of managing power in a computing platform may involve monitoring a runtime power consumption of two or more of a plurality of hardware components in the platform to obtain a plurality of runtime power determinations. The method can also include exposing one or more of the plurality of runtime power determinations to an operating system associated with the platform.

Abstract: The memory controller is provided with a refresh clock generation unit, a control signal generation unit, and a refresh request generation unit. The refresh clock generation unit generates a clock obtained by frequency dividing a system clock, as a refresh clock. The control signal generation unit issues a refresh command to a memory, based on the refresh clock. The refresh request generation unit curtails, based on a specified refresh count in a specified refresh period determined by the memory, a supply to the control signal generation unit of a redundant refresh clock generated exceeding the specified refresh count, the refresh clock being generated within the specified refresh period.