Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage devices, for data processing. One of the methods includes maintaining, by a storage system, a plurality of storage devices that include at least a first tier storage device and a second tier storage device. The storage system receives a write request of a ledger data, determines whether a type of the ledger data is block data, and, in response to determining that the type of the ledger data is block data, writes the ledger data into the second tier storage device.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory may include: a memory circuit comprising a plurality of memory cells; a read circuit configured to generate a first read data signal by reading data from a read target memory cell according to a first read control signal, the read target memory cell being among the plurality of memory cells; and a control circuit configured to control the read circuit to reread the data from the read target memory cell by generating a second read control signal, the second read control signal being based on a data value of the first read data signal.

Abstract: A method can include allowing re-use of a selected shareable tag storage location and thus updating a first shareable tag portion comprised therein to a second shareable tag portion; identifying one or more cache lines associated with individual tag portions comprising a pointer to the selected shareable tag storage location; and setting a given cache line status for each of the identified cache lines, wherein the given cache line status: a) allows a cache line to continue to be used in relation to a storage access instruction received before said given cache line status was set; and b) inhibits the cache line from being used in relation to a storage access instruction received after the given cache line status is set.

Abstract: A storage device includes multiple memory devices and a memory controller. The memory controller receives, from a host, values corresponding to data stored in the memory devices and keys for identifying the values, generates parities for inspecting the data for any errors based on the values, and manages key-value mapping information regarding a correspondence between the values and the keys. The memory devices include a first memory device and a second memory device, which store the values and the keys, and a third memory device, which stores parity values calculated from the values and a parity value header for managing the parity values.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for caching data not frequently accessed. One of the methods includes receiving a request for data from a component of a device, determining that the data satisfies an infrequency condition, in response to determining that the data satisfies the infrequency condition: determining a target cache level which defines a cache level within a cache level hierarchy of a particular cache at which to store infrequently accessed data, the target cache level being lower than a highest cache level in the cache level hierarchy, requesting and receiving the data from a memory that is not a cache of the device, and storing the data in a level of the particular cache that is at or below the target cache level in the cache level hierarchy, and providing the data to the component.

Abstract: An apparatus, a computer program and a method for prefetching a predetermined number of data items to a cache. The method comprises obtaining a list of candidate data items and associated scores thereof, that comprises more candidate data items than the predetermined number of data items to be prefetched to the cache. The method comprises repeatedly selecting, based on scores of the candidate data items, a candidate data item from the list and determining whether to add the candidate data item to the cache. Determining whether to add the candidate data item to the cache comprises determining whether the candidate data item is retained by the cache; and in response to determining that the candidate data item is not retained by the cache, adding the candidate data item thereto. The repeatedly selecting and determining are performed until the predetermined number of data items is added to the cache.

Abstract: Various embodiments are generally directed to techniques to store data for critical chunk operations, such as by utilizing a spare lane, for instance. Some embodiments are particularly directed to a memory controller that stores a portion of a critical chunk in a spare lane to enable the entire critical chunk to be stored in a half of the cache line.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, first to third circuits. The first circuit is configured to control duty cycles of first and second signals based on a third signal, and output fourth and fifth signals. The second circuit is configured to acquire information regarding duty cycles. The third circuit is configured to control the third signal. The second circuit includes a switching circuit and a comparator. The switching circuit is configured to transfer the fourth and fifth signals to first and second nodes. The comparator is configured to compare a signal voltages in the first and second nodes, and output the comparison result to the third circuit.

Abstract: Techniques for offloading operations to access data that is compressed and distributed to multiple storage nodes are disclosed. A storage node includes one or more storage devices to store a portion of compressed data. Other portions of the compressed data are stored on other storage nodes. A storage node receives a request to perform an operation on the data, decompresses at least part of the portion of the locally stored compressed data, and performs the operation on the decompressed part, returning the operation result to a compute node. Any part that could not be decompressed can be sent with the request to the next storage node. The process continues until all the storage nodes storing the compressed data receive the request, decompress the locally stored data, and perform the operation on the decompressed data.

Abstract: Provided are an apparatus and system to cache data in a first cache and a second cache that cache data from a shared memory in a local processor node, wherein the shared memory is accessible to at least one remote processor node. A cache controller writes a block to the second cache in response to determining that the block is more likely to be accessed by the local processor node than a remote processor node. The first cache controller writes the block to the shared memory in response to determining that the block is more likely to be accessed by the one of the at least one remote processor node than the local processor node without writing to the second cache.

Abstract: Embodiment of this disclosure provides a mechanism to store cache lines in dedicated cache of an idle core. In one embodiment, a multi-core processor comprising a first core, a second core, a first cache, a second cache, a third cache, and a cache controller unit is provided. The cache controller is operatively coupled to at least the first cache, the second cache, and the third cache. The cache controller is to evict a first line from the first cache, wherein the first core is in an active state. Responsive to the evicting of the first line, the first line is stored in the third cache. Responsive to storing the first line, a second line is evicted from the third cache. Responsive to evicting the second line, the second line is stored in the second cache when the second core is in an idle state.

Abstract: In a Redis-based database data aggregation and synchronization method, a synchronization program scans data of a table of a target database, calculates and stores a Key and a Value of each row into a Redis, while writing the row into an aggregation database. When there is a change of data in the table of the target database, the synchronization program re-calculates a new Key and a new Value of each row in the target database and inquires whether a key same as the new Key exists in the Redis to update the data in the aggregation database, and then perform a difference set calculation for the data after the synchronization of the primary key set of the table of the target database and the corresponding primary key set of the table of the aggregation database, and delete the data from the aggregation database by determining whether or an element exists in the difference set.

Abstract: The present invention relates to a method and a device for searching for and controlling controllees in a smart home system. The method for searching for and controlling controllees existing on two or more networks from controllers in a smart home system, according to one embodiment of the present invention, comprises the steps of: requesting a list of the controllees and receiving the list of the controllees from a server; transmitting a response request signal for requesting a response to the controllees existing in the received list of the controllees; and, when a response signal has not been received from one or more controllees, generating a non-response list for controlling, by the server, the controllees from which the response signal has not been received.

Abstract: To address the issue of latency in relational database systems, a computerized database management system comprising a database server, a processor, and associated random access memory is provided. The processor may configure an in-memory database in the random access memory to have tables, each containing a plurality of cells associated memory addresses, establish a direct table association between an origin cell and a target cell within the tables, receive a request to perform a join database operation of a first table including the origin cell on a second table including the target cell, dereference the direct table association for the origin cell to obtain a value of the target cell stored at the memory address for the target cell, execute the join database operation to produce a joined table including the value, and store the joined table at a new location in the random access memory.

Abstract: A first cache module, comprising fully associative cache circuitry, provides TLB entries for a first group of multiple page sizes. A second cache module, comprising set associative cache circuitry, provides TLB entries for a second group of multiple page sizes. Managing TLB entries includes: performing a search in the first cache module based on selected tag bits of a target virtual address that are selected for each TLB entry in the first cache module based on information stored in the first cache module corresponding to one of the multiple pages sizes in the first group, and performing multiple search iterations in the second cache module based on selected index bits and selected tag bits of the target virtual address, where quantities of bits in the selected index bits and the selected tag bits are different for each of the search iterations.

Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.

Abstract: A computational device determines whether one or more tasks are waiting for accessing a cache for more than a predetermined amount of time while least recently used (LRU) based replacement of tracks are being performed for the cache via demotion of tracks from a LRU list of tracks corresponding to the cache. In response to determining that one or more tasks are waiting for accessing the cache for more than the predetermined amount of time, in addition to continuing to demote tracks from the LRU list, a plurality of deadlock prevention demotion tasks demote tracks from the cache.

Abstract: A method and system for synchronizing caches after reboot are described. In a cached environment, a host server stores a cache counter associated with the cache, which can be stored in the cache itself or in another permanent storage device. When data blocks are written to the cache, metadata for each data block is also written to the cache. This metadata includes a block counter based on a value of the cache counter. After a number of data operations are performed in the cache, the value of the cache counter is updated. Then, each data block is selectively updated based on a comparison of the value of the cache counter with a value of the block counter in the metadata for the corresponding data block.

Abstract: Storage of data in a cache system is controlled by a cache monitor. A cache line is filled in response to a memory instruction from a cache client. The cache monitor includes a predictor table and update logic. An entry in the predictor table comprises an instruction identifier that associates the entry with a memory instruction and, for each cache in the system, a reuse counter. The update logic is configured to update a reuse counter table dependent upon cache behavior in response to memory instructions. Storage of data a first data address in cache in response to a memory instruction having a first instruction identifier, is dependent upon reuse counter values in an entry of the predictor table associated with first instruction identifier. Reuse counters are updated dependent upon cache behavior. A Bloom filter or other data structure may be used to associate data addresses with a memory instruction.

Abstract: A data processing system includes a processor core having a shared store-through upper level cache and a store-in lower level cache. The processor core executes a plurality of simultaneous hardware threads of execution including at least a first thread and a second thread, and the shared store-through upper level cache stores a first cache line accessible to both the first thread and the second thread. The processor core executes in the first thread a store instruction that generates a store request specifying a target address of a storage location corresponding to the first cache line. Based on the target address hitting in the shared store-through upper level cache, the first cache line is temporarily marked, in the shared store-through upper level cache, as private to the first thread, such that any memory access request by the second thread targeting the storage location will miss in the shared store-through upper level cache.

Abstract: An information processing apparatus configured to be coupled via a communication line to a plurality of nodes each having a storage device, the information processing apparatus includes a memory; and a processor coupled to the memory and configured to determine, from among a plurality of nodes, a location where a virtual machine is to be placed, determine that a location where management information on data to be processed, the data to be accessed from the virtual machine, is to be stored is, among the plurality of nodes, a node that is identical to the location of the virtual machine, and store the management information in the determined node.

Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.

Abstract: Various embodiments of the present disclosure generally relate to a method and an electronic device for reading data. Specifically, the method comprises receiving a request for reading the target data, and in response to the request, searching for the target data by searching a data index generated in a cache for reading data. The method further comprises in response to the target data being found, providing the target data. A corresponding system, device and computer program product are also provided.

Abstract: The present technology provides a new content-based centrality metric that may be used for allocating content to caches in a network. The proposed method for measuring centrality and allocating content not only considers the topology of the network, but also the distribution of cache spaces and content among the cache spaces in the network in order to improve how content may be allocated. This approach to content allocation enables improved content retrieval in the form of higher cache hit rates, lower delays and improved network performance.

Abstract: Data entities in a client-server system are accessed. The client-server system comprises a set of clients, a server system, and a repository for storing a plurality of data entities. The server system comprises an inter-transactional cache, the inter-transactional cache being accessible for each client of the set of clients. A first client of the set of clients comprises a first intra-transactional cache. If a copy of a first data entity is in the inter-transactional cache, a version identifier of the original first data entity is read from the repository. If the copy of the first data entity is to be accessed with an exclusive lock, a copy of the copy of the first data entity is added to the first intra-transactional cache. The copy of the copy of the first data entity in the first intra-transactional cache is accessed for further processing of the first data entity by the first client.

Abstract: A prefetch controller is configured to communicate with a prefetch cache in order to increase system performance. The prefetch controller includes an instruction lookup table (ILT) configured to receive a first tuple including a first instruction ID and a first missed data address. The prefetch controller further includes a tuple history queue (THQ) configured to receive an instruction/stride tuple, the instruction/stride tuple generated by subtracting a last data access address from the first missed data address. The prefetch controller further includes a sequence prediction table (SPT) in communication with the tuple history queue (THQ) and the instruction lookup table. The prefetch controller includes an adder in communication with the instruction lookup table (ILT) and the sequence prediction table (SPT) configured to generate a predicted prefetch address and to provide the predicted prefetch address to a prefetch cache.

Abstract: Data entities in a client-server system are accessed. The client-server system comprises a set of clients, a server system, and a repository for storing a plurality of data entities. The server system comprises an inter-transactional cache, the inter-transactional cache being accessible for each client of the set of clients. A first client of the set of clients comprises a first intra-transactional cache. If a copy of a first data entity is in the inter-transactional cache, a version identifier of the original first data entity is read from the repository. If the copy of the first data entity is to be accessed with an exclusive lock, a copy of the copy of the first data entity is added to the first intra-transactional cache. The copy of the copy of the first data entity in the first intra-transactional cache is accessed for further processing of the first data entity by the first client.

Abstract: A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.

Abstract: Techniques for managing data files spread across different remote storage systems are described. A remote storage management system can provide a unified file system that interacts with different remote storage services to allow a user to manage, from one interface, the user's data stored in different source systems. The remote storage management system may allow a user to create sharable cloud drives with combination of files from the unified file system irrespective of which service provider is storing the files. The generated cloud drive can be shared with a recipient to give the recipient access to the user's files. The recipient is not required to have an account with any of the remote storage service providers or with the remote storage management system.

Abstract: An overlay optimizer can prevent cross-volume moves to optimize the performance of a write filter. The overlay optimizer can be configured to detect when a file move is being attempted and can modify the handling of the file move so that a cross-volume move is not performed. In the case where the file move would result in a file being moved from the volume where the overlay cache is implemented, the overlay optimizer can create a copy of the target directory tree in the overlay cache and redirect the move to the newly created directory. In the case where the file move would result in a file being moved to the volume where the overlay cache is implemented, the overlay optimizer can forgo redirection so that the file will be moved within the same volume.

Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

Abstract: A method for accessing data is provide, the method includes: receiving a first address and identification information used to identify an address type; and when the identification information indicates a logical address type, converting the first address into a first physical address, and accessing at least one corresponding flash memory chip in the storage device; or when the identification information indicates a physical address type, directly accessing at least one corresponding flash memory chip in the storage device. When the storage device is accessed, a type of an accessed address is determined according to the identification information. If the address is a logical address, the storage controller maps the logical address to a physical address and accesses the physical address; or if the address is a physical address, the storage controller directly accesses the physical address sent by the host.

Abstract: System and method for managing multiple data storages using a file system of a computer system utilize a primary data storage to cache objects of logical object containers stored in a secondary data storage in caching-tier volumes. When an access request for an object stored in the secondary data storage is received at the file system and the object is not currently cached in the primary data storage, a caching-tier volume in the primary data storage is created that corresponds to a logical object container in the secondary data storage that includes the requested object. The caching-tier volume is used to cache the object as an inflated file so that the inflated file is available at the primary data storage in the caching-tier volume for a subsequent access request for the object stored in the secondary data storage.

Abstract: In some examples, a computing device may determine that a selected application is executing and gather, over a predetermined time interval, data associated with operations being performed to the input/output stack by the selected application. After gathering the data, a classifier may analyze the data and determine a particular workload type from a predefined set of workload types associated with the selected application. The computing device may select a particular profile from a plurality of predefined profiles based at least in part on the particular workload type, and modify, based on the particular profile, a plurality of parameters to create a plurality of modified parameters. The modified parameters may reduce an execution time of performing the operations to the input/output stack.

Abstract: An expandable drawing surface is described. In various embodiments, a drawing surface manager is configured to cause a size of a drawing surface to expand dynamically to provide a user with a truly infinite drawing surface such that the user is not limited for space in any direction. To do so, the drawing surface manager creates and displays new pages for the drawing surface as the user scrolls in any direction. The new pages are displayed proximate existing pages such that the user is presented with a continuous drawing surface on which the user can work seamlessly. In one or more embodiments, a memory manager is configured to provide efficient memory techniques such that, at any point of time, only data associated with visible pages of the drawing surface is loaded onto a memory.

Abstract: A memory system includes: a memory device that includes a plurality of memory dies each of which includes a plurality of planes, each of which includes a plurality of memory blocks that store data; and a controller including a first memory, and configured to: receive a plurality of commands from a host; perform command operations corresponding to the received commands in the memory blocks; detect patterns of the commands, the command operations, and user data corresponding to the command operations; dynamically allocate as pattern zones the first memory based on the patterns; and load map segments of map data corresponding to the commands, the command operations, and the user data into the pattern zones.

Abstract: A facility is provided that, when installed, removes from an architecture a selected architectural function, such that the function is not able to be turned on/off regardless of other controls within the environment. When the facility is installed, the architectural function is not supported when processing in an architectural mode based on the architecture. It is as if the selected architectural function is no longer available in the architecture, and in fact, the code implementing the facility may have been deleted, bypassed, or otherwise eliminated. One such architectural function is virtual address translation, such as dynamic address translation (DAT), and the architecture is, for instance, ESA/390.

Abstract: Objects are managed in a virtual machine. A frequency of access to fields in objects for an application is identified while the application runs in the virtual machine. An object in the objects is split into a hot object and a cold semi-object based on the frequency of access to the fields in the object as identified while the application runs in the virtual machine, wherein cache misses are reduced from splitting objects based of the frequency of access.

Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.

Abstract: Examples provide a memory device, a dual inline memory module, a storage device, an apparatus for storing, a method for storing, a computer program, a machine readable storage, and a machine readable medium. A memory device is configured to store data and comprises one or more interfaces configured to receive and to provide data. The memory device further comprises a memory module configured to store the data, and a memory logic component configured to control the one or more interfaces and the memory module. The memory logic component is further configured to receive information on a specific memory region with one or more model identifications, to receive information on an instruction to perform an acceleration function for one or more certain model identifications, and to perform the acceleration function on data in a specific memory region with the one or more certain model identifications.

Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

Abstract: An iterative graph algorithm accelerating method, system, and computer program product, include recording an order of access nodes in a memory layout, reordering the access nodes in the memory layout in accordance with the recorded order, and updating edge information of the reordered access nodes.

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.

Abstract: In one implementation, a method includes transmitting, to a server, a first interest message. The first interest message includes a request for a representational state transfer (REST) operation and a name of a first state for the REST operation. The method also includes receiving, from the server, a second interest message. The second interest message includes the name of the first state for the REST operation. The method further includes transmitting, to the server, the first state based on the second interest message and receiving, from the server, a response to the REST operation.

Abstract: Examples herein are directed to centralized database based multicast converging. For instance, in various examples centralized database based multicast converging can include starting a restart timer having a value greater than a time to validate stored entries in a centralized database, sending data packets at least to hosts on the network corresponding to the stored entries in the centralized database to maintain service to the hosts while the restart timer is running, sending query packets to validate a host corresponding to an entry of the stored entries in the centralized database, and responsive to the restart timer expiring, sending data packets to a converged group of hosts including at least the validated host.

Abstract: An improved data storage device including an improved storage controller that enables the acceleration of datacenter software by making it easier to deploy application software portions (applets) onto storage devices in a manner that best supports runtime performance acceleration of storage-network-latency-throttled applications. Means are defined for how server hosted applications cause to have provisioned, initiate execution of, and work with a multitude of applets disposed for execution proximate to storage contents on a multitude of storage devices. This invention supports the multi-exabyte growth of data storage, by scaling performance acceleration linearly with the growth in the number of storage devices. This in turn supports the evolving cloud and Enterprise Cognitive Computing datacenter by providing the infrastructure necessary for accelerating applications that face enormous heterogeneous datasets. This includes Big Data Analytics of problems that have eluded successful analysis.

Abstract: The present invention provides a temporary memory processing method including: receiving a write command including a write data and a write address; determining whether a corresponding temporary address is in a missed state to generate a determined result; and determining whether to write the write data into a corresponding buffer address of a buffer memory according to the determined result.

Abstract: An apparatus and method are provided for controlling use of a register cache. The apparatus has decode circuitry for decoding instructions retrieved from memory, execution circuitry to execute the decoded instructions in order to perform operations on data values, and a register file having a plurality of registers for storing the data values to be operated on by the execution circuitry. Further, a register cache is provided that comprises a plurality of entries, and is arranged to cache a subset of the data values. Each entry is arranged to cache a data value and an indication of the register associated with that cached data value. Prefetch circuitry is then used to prefetch data values from the register file into the register cache. Further, operand analysis circuitry derives source operand information for an instruction fetched from memory, at least prior to the decode circuitry completing decoding of that instruction.

Abstract: Example multi-device storage systems, storage devices, and methods provide hosted services on peer storage devices. Storage devices include local memory resources, such as operating memory, remotely addressable memory, or logical mapping memory, and compute resources, such as a processor or coding engine. Each storage device is configured to communicate with a plurality of peer storage devices over an interconnect fabric. The storage devices identify requested hosted services from service host requests received through the interconnect fabric. The storage devices store a plurality of hosted services are to enable access to local memory resources and local compute resources for data management operations for the plurality of peer storage devices.

Abstract: A method of sharing information between an external device and a portable processing device in communication with the external device, including the steps of the portable processing device evaluating policy restrictions associated with the external device, evaluating requested data by the external device in view of the policy restrictions, if the requested data may be shared with the external device, then the portable process device providing access to the data requested. The method may further include setting policy restrictions as a function of the external device, 3rd party security requirements, subscriber preferences and/or predefined mobility network policies.