Abstract: Aspects of the disclosed technology relate to techniques for modeling content-addressable memory in emulation and prototyping. A model for content-addressable memory comprises memory circuitry configured to store match results for various search keys. The match results are stored in the second memory circuitry during write operations. The model for content-addressable memory may further comprise additional memory circuitry configured to operate as a standard computer memory, performing read operations alone and write operations along with the memory circuitry.

Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.

Abstract: Provided are systems and methods for obtaining geographic location data. In one embodiment, an example method includes identifying, by the first software application running on one or more computing devices, one or more location parameters indicative of a geographic point of interest based at least in part on an application programming interface invoked by the first software application. The method includes generating, by the first software application running on the one or more computing devices, a query string including the one or more location parameters and a parameter that is indicative of the application programming interface. The method includes requesting, by the first software application, location data associated with the geographic point of interest based at least in part on the query string. The method includes providing for display, on at least one display device, the location data associated with the geographic point of interest.

Abstract: A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.

Abstract: An apparatus and method are provided for controlling allocation of data into cache storage. The apparatus comprises processing circuitry for executing instructions, and a cache storage for storing data accessed when executing the instructions. Cache control circuitry is arranged, while a sensitive allocation condition is determined to exist, to be responsive to the processing circuitry speculatively executing a memory access instruction that identifies data to be allocated into the cache storage, to allocate the data into the cache storage and to set a conditional allocation flag in association with the data allocated into the cache storage. The cache control circuitry is then responsive to detecting an allocation resolution event, to determine based on the type of the allocation resolution event whether to clear the conditional allocation flag such that the data is thereafter treated as unconditionally allocated, or to cause invalidation of the data in the cache storage.

Abstract: A data processing system includes a plurality of processor cores each having a respective store-through upper level cache and a store-in banked lower level cache. Store requests of the plurality of processor cores destined for the banked lower level cache are buffered in multiple store queues including a first store queue and a second store queue. In response to determining that the multiple store queues contain store requests targeting a common bank of the banked lower level cache, store requests from the first store queue are temporarily favored for selection for issuance to the banked lower level cache over those in the second store queue.

Abstract: A data processing system includes a plurality of processor cores each having a respective store-through upper level cache and a store-in banked lower level cache. Store requests of the plurality of processor cores destined for the banked lower level cache are buffered in multiple store queues including a first store queue and a second store queue. In response to determining that the multiple store queues contain store requests targeting a common bank of the banked lower level cache, store requests from the first store queue are temporarily favored for selection for issuance to the banked lower level cache over those in the second store queue.

Abstract: A method includes altering a request interval threshold when a cache-hit ratio falling below a target, receiving a request for content, providing the content when the content is in the cache, when the content is not in the cache and the time since a previous request for the content is less than the request interval threshold, retrieving and storing the content, and providing the content to the client, when the elapsed time is greater than the request interval threshold, and when another elapsed time since another previous request for the content is less than another request interval threshold, retrieving and storing the content, and providing the content to the client, and when the other elapsed time is greater than the other request interval threshold, rerouting the request to the content server without caching the content.

Abstract: A computing system includes multiple compute nodes that include respective processors and respective cache memories. The processors are configured to determine a default compute node in which a given data item is to be cached, to make a decision whether to cache the given data item in the default compute node or in an alternative compute node, based on cache-quality metrics that are evaluated for respective cache memories of the compute nodes, and to cache the given data item in the default compute node or in the alternative compute node, depending on the decision.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Abstract: Methods and systems are provided for increasing bandwidth efficiency in satellite communications. In some embodiments, a satellite communications method is provided that comprises receiving, at a satellite and from a plurality of user ground terminals, a plurality of source signals, wherein each of the source signals are modulated according to at least one source modulation method, and further receiving, at a satellite and from a plurality of user ground terminals, a plurality of information signals corresponding to the plurality of source signals. The method further includes combining, at the satellite, the plurality of source signals into a combined source signal with an overlapping bandwidth, wherein each of the source signals are further modulated according to at least one predetermined modulation method before they are combined, and transmitting, by a downlink transmission from the satellite to a gateway ground station, the combined source signal.

Abstract: Systems, methods and/or devices are used to enable using sub-region I/O history to cache repeatedly accessed sub-regions in a non-volatile storage device. In one aspect, the method includes (1) receiving a plurality of input/output (I/O) requests including read requests and write requests to be performed in a plurality of regions in a logical address space of a host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including, for each sub-region of a plurality of sub-regions of the region: (a) determining whether the sub-region is accessed more than a predetermined threshold number of times during a predetermined time period, and (b) if so, caching, from a storage medium of the storage device to a cache of the storage device, data from the sub-region.

Abstract: A request to access to a logical location in a file stored in a content addressable storage (CAS) system can be processed by retrieving first tree data from a first node in a first hash tree that represents a first version of the file. Based on the first tree data, a second node is selected from which a CAS signature is compared to a reserved CAS signature to determine the proper file version. In response to a match, a third node is accessed in a second hash tree that represents a second version of the file. Tree data is retrieved from a third node.

Abstract: Embodiments are directed to techniques for implementing a deduplication system that minimizes disk accesses to an on-disk digest log when deduplicating consecutively-stored data. These techniques for performing deduplication utilize an in-memory temporal digest cache. When the on-disk digest log is accessed for a set of data and a match is found, the temporal digest cache is written with digests not only for the set of data but also for other data stored in a temporal relationship with the set of data. This temporal digest cache allows subsequent deduplication of temporally-related data to proceed faster without needing to repeatedly access the digest log on disk.

Abstract: An apparatus to facilitate page translation is disclosed. The apparatus a set associative translation lookaside buffer (TLB) including a plurality of entries to store virtual to physical memory address translations and a page size table (PST) including a plurality of entries to store page size corresponding to each of the TLB entries.

Abstract: Technology to dynamically modulate read granularity of a memory device. A computing system may include a controller and one or more memory devices coupled to the controller, the one or more memory devices including instructions, which when executed by the controller, may cause the computing system to determine whether a read to a memory device satisfies a sub-page read policy. In addition, the instructions, when executed, may cause the computing system to issue a sub-page read command to retrieve data from the memory device at sub-page granularity when the read satisfies the sub-page read policy. Moreover, the instructions, when executed, may cause the computing system to issue a full-page read command to retrieve the data at full-page granularity when the read does not satisfy the sub-page read policy or when a read for a segment of sequentially stored data does not satisfy the sub-page read policy.

Abstract: Providing dynamic determination of memory attributes in processor-based systems is disclosed. In this regard, in some aspects, a processor-based system comprises a processor device and one or more memory devices, each of which is associated with one of a plurality of memory attributes. The processor device transmits a request to one of the memory devices to determine the memory attribute associated with the memory device. In response to the request, the memory device provides a memory attribute indication that informs the processor device of the memory attribute associated with the memory device. The processor device in some aspects then performs subsequent memory access operations on the memory device based on the memory attribute indication. Some aspects may provide that the processor device also stores the memory attribute indication, and performs subsequent memory access operations based on the stored memory attribute indication.

Abstract: A method of operating a cache and corresponding apparatus are provided. The cache is capable of being only partially powered, and a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access. The cache hit bandwidth is compared against this memory bandwidth equivalent and when the cache hit bandwidth is less than the memory bandwidth equivalent, the proportion of the cache which is currently powered is reduced. A analogous decision may also be made and based on calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power, and when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, the proportion of the cache which is currently powered is increased.

Abstract: A device includes a processor configured to: divide loop in a program into first loop and second loop when compiling the program, the loop accessing data of an array and prefetching data of the array to be accessed at a repetition after prescribed repetitions at each repetition, the first loop including one or more repetitions from an initial repetition to a repetition immediately before the repetition after the prescribed repetitions, the second loop including one or more repetitions from the repetition after the prescribed repetitions to a last repetition, and generate an intermediate language code configured to access data of the array using a first region in a cache memory and prefetch data of the array using a second region in the cache memory in the first loop, and to access and prefetch data of the array using the second region in the second loop.

Abstract: Systems and methods for a low-overhead index for a cache. The index is used to access content or segments in the cache by storing at least an identifier and a location. The index is accessed using the identifier. The identifier may be shortened or be a short identifier. Because a collision may occur, the index may also include one or more meta-data values associated with the data segment. Collisions can be resolved by also comparing the metadata of the segment with the metadata stored in the index. If both the short identifier and metadata match those of the segment, the segment is likely in the cache and can be accessed. Segments can also be inserted into the cache.

Abstract: Embodiments of the present invention provide a method, computer program product, and a computer system for storing data records in extents. According to one embodiment a data record comprising an attribute value is received. One or more data records stored in a first extent, are identified, wherein the stored one or more data records in the first extent have at least one attribute value. The attribute value of the received data record is compared to the attribute values of the identified data records stored in the first extent. It is then determined whether to store the received data record in the first extent. Responsive to determining, not to store the received data record in the first extent, the received data record is stored in a second extent. If the first received data record is stored in a second extent, determining, an attribute value information of the second extent.

Abstract: A power state transformer, a system and a method thereof are disclosed. The power state transformer is coupled with a processing unit model. The power state transformer is configured for counting performance activities executed in the processing unit model, and further for determining a power state of the processing unit model according to count values of the performance activities.

Abstract: Provided are a computer program product, system, and method for processing cache miss rates to determine memory space to add to an active cache to reduce a cache miss rate for the active cache. During caching operations to the active cache, information is gathered on an active cache miss rate based on a rate of access to tracks that are not indicated in the active cache list and a cache demote rate. A determination is made as to whether adding additional memory space to the active cache would result in the active cache miss rate being less than the cache demote rate when the active cache miss rate exceeds the cache demote rate. A message is generated indicating to add the additional memory space when adding the additional memory space would result in the active cache miss rate being less than the cache demote rate.

Abstract: Aspects include computing devices and methods implemented by the computing for automatic cache coherency for page table data on a computing device. Some aspects may include modifying, by a first processing device, page table data stored in a first cache associated with the first processing device, receiving, at a page table coherency unit, a page table cache invalidate signal from the first processing device, issuing, by the page table coherency unit, a cache maintenance operation command to the first processing device, and writing, by the first processing device, the modified page table data stored in the first cache to a shared memory accessible by the first processing device and a second processing device associated with a second cache storing the page table data.

Abstract: A computer processor is disclosed. The computer processor comprises one or more processor resources. The computer processor further comprises a plurality of hardware thread units coupled to the one or more processor resources. The computer processor may be configured to permit simultaneous access to the one or more processor resources by only a subset of hardware thread units of the plurality of hardware thread units. The number of hardware threads in the subset may be less than the total number of hardware threads of the plurality of hardware thread units.

Abstract: Disclosed are methods, circuits, devices, systems and associated computer executable code for providing Domain Name Resolution functionality to a data client device accessing a networked data resource through an access point of a data communication network. According to some embodiments, an access point or node of a data communication network may be integral or otherwise functionally associated with a conditional domain name system (CDNS), which CDNS may include a local cache of conditional DNS records.

Abstract: A data processing system includes at least one processor core each having an associated store-through upper level cache and an associated store-in lower level cache. In response to execution of a memory move instruction sequence including a plurality of copy-type instructions and a plurality of paste-type instructions, the at least one processor core transmits a corresponding plurality of copy-type and paste-type requests to its associated lower level cache, where each copy-type request specifies a source real address and each paste-type request specifies a destination real address. In response to receipt of each copy-type request, the associated lower level cache copies a respective data granule from a respective storage location specified by the source real address of that copy-type request into a non-architected buffer.

Abstract: Techniques are provided for maintaining data persistently in one format, but making that data available to a database server in more than one format. For example, one of the formats in which the data is made available for query processing is based on the on-disk format, while another of the formats in which the data is made available for query processing is independent of the on-disk format. Data that is in the format that is independent of the disk format may be maintained exclusively in volatile memory to reduce the overhead associated with keeping the data in sync with the on-disk format copies of the data. Selection of data to be maintained in the volatile memory may be based on various factors. Once selected the data may also be compressed to save space in the volatile memory. The compression level may depend on one or more factors that are evaluated for the selected data.

Abstract: According to embodiments described herein, the hierarchical complexity for coherence protocols associated with clustered cache architectures can be encapsulated in a simple function, i.e., that of determining when a data block is shared entirely within a cluster (i.e., a sub-tree of the hierarchy) and is private from the outside. This allows embodiments to eliminate complex recursive coherence operations that span the hierarchy and instead employ simple coherence mechanisms such as self-invalidation and write-through but which are restricted to operate where a data block is shared. Thus embodiments recognize that, in the context of clustered cache hierarchies, data can be shared entirely within one cluster but can be private (unshared) to this cluster when viewed from the perspective of other clusters. This characteristic of the data can be determined and then used to locally simplify coherence protocols.

Abstract: Technical solutions are described for executing one or more out-of-order instructions by a processing unit. An example method includes executing, by a load-store unit (LSU), instructions from an out-of-order (OoO) window. The OoO execution includes determining an effective address being used by a load instruction from the OoO window. Further, the execution includes determining presence of the effective address in an effective address directory (EAD) by identifying an EAD entry in the EAD, the EAD entry maps the effective address with an index of a corresponding effective-real table (ERT) entry from an effective-real table (ERT). In response to the effective address being present in the EAD, the execution includes accessing the corresponding ERT entry of the effective address of the load instruction, the corresponding ERT entry including a real address for the effective address, and issuing the load instruction using the real address from the corresponding ERT entry.

Abstract: An instruction in a first cache line may be identified and an address associated with the instruction may be determined. The address may be determined to cross a cache line boundary associated with the first cache line and a second cache line. In response to determining that the address crosses the cache line boundary, the instruction may be adjusted based on a portion of the address included in the first cache line and a second instruction may be created based on a portion of the address included in the second cache line. The second instruction may be injected into an instruction pipeline after the adjusted instruction.

Abstract: Embodiments of the present invention provide a method, computer program product, and a computer system for storing data records in extents. According to one embodiment a data record comprising an attribute value is received. One or more data records stored in a first extent, are identified, wherein the stored one or more data records in the first extent have at least one attribute value. The attribute value of the received data record is compared to the attribute values of the identified data records stored in the first extent. It is then determined whether to store the received data record in the first extent. Responsive to determining, not to store the received data record in the first extent, the received data record is stored in a second extent. If the first received data record is stored in a second extent, determining, an attribute value information of the second extent.

Abstract: In non-limiting examples of the present disclosure, systems and methods for interning expression trees are provided. Hash code for a plurality of expression tree nodes is recursively computed and a determination is made as to whether hash code for each of a plurality of expression tree nodes is stored in a cached intern pool. Upon determining that at least one of a plurality of expression tree nodes is not stored in a cached intern pool, one or more functions may be run on at least one of a plurality of expression tree nodes for determining whether at least one of a plurality of expression tree nodes should be stored in a cached intern pool. Normalization of expression trees may also be employed to effectuate effective sharing of expression tree nodes.

Abstract: A memory system may include a memory device comprising a plurality of memory blocks each having a plurality of pages; and a controller suitable for storing data in a first memory block among the memory blocks, storing map data of the data in a second memory block among the memory blocks, and scanning the map data by performing filtering on logical information of the data in response to a command.

Abstract: Systems, methods, and computer programs are disclosed for reducing memory power consumption. An exemplary method comprises configuring a power saving memory balloon associated with a volatile memory. Memory allocations are steered to the power saving memory balloon. In response to initiating a memory power saving mode, data is migrated from the power saving memory balloon. A power saving feature is executed on the power saving memory balloon while in the memory power saving mode.

Abstract: Technical solutions are described for executing one or more out-of-order instructions by a processing unit. An example method includes executing, by a load-store unit (LSU), instructions from an out-of-order (OoO) window. The OoO execution includes determining an effective address being used by a load instruction from the OoO window. Further, the execution includes determining presence of the effective address in an effective address directory (EAD) by identifying an EAD entry in the EAD, the EAD entry maps the effective address with an index of a corresponding effective-real table (ERT) entry from an effective-real table (ERT). In response to the effective address being present in the EAD, the execution includes accessing the corresponding ERT entry of the effective address of the load instruction, the corresponding ERT entry including a real address for the effective address, and issuing the load instruction using the real address from the corresponding ERT entry.

Abstract: A cloud-based storage service hosts content information that may be accessed by client machines in a peer-to-peer network. The content information is a compact representation of the content which is stored outside of the cloud-based storage service. The cloud-based storage service generates the content information and a content information hash. The content information hash is used to validate the content information when the content information is downloaded to the peer-to-peer network. The cloud-based storage service also generates metadata that describes the content information so that a client machine in the peer-to-peer network may access the content information from the cloud-based storage service.

Abstract: A special class of loads and stores access a user-defined memory region where coherency and memory orders are only enforced at the coherent point. Coherent memory requests, which are limited to user-defined memory region, are dispatched to the common memory ordering buffer. Non-coherent memory requests (e.g., all other memory requests) can be routed via non-coherent lower level caches to the shared last level cache. By assigning a private, non-overlapping, address spaces to each of the processor cores, the lower-level caches do not need to implement the logic necessary to maintain cache coherency. This can reduce power consumption and integrated circuit die area. This can also improve memory bandwidth and performance for applications with predominantly non-coherent memory accesses while still providing memory coherence for specific memory range(s)/applications that demand it.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for caching data not frequently accessed. One of the methods includes receiving a request for data from a component of a device, determining that the data satisfies an infrequency condition, in response to determining that the data satisfies the infrequency condition: determining a target cache level which defines a cache level within a cache level hierarchy of a particular cache at which to store infrequently accessed data, the target cache level being lower than a highest cache level in the cache level hierarchy, requesting and receiving the data from a memory that is not a cache of the device, and storing the data in a level of the particular cache that is at or below the target cache level in the cache level hierarchy, and providing the data to the component.

Abstract: Embodiments herein provide for improved store-to-load-forwarding (STLF) logic and linear aliasing effect reduction logic. In one embodiment, a load instruction to be executed is selected. Whether a first linear address associated with said load instruction matches a linear address of a store instruction of a plurality of store instructions in a queue is determined. Data associated with said store instruction for executing said load instruction is forwarded, in response to determining that the first linear address matches the linear address of the store instruction.

Abstract: Cloud-based virtual machines and offices are provided herein. Methods may include establishing a cloud-based virtual office using a runbook that is pre-configured with computing resource settings for VMs as well as VM dependencies and sequences that create the virtual office or virtual private cloud. Multiple runbooks can be created to cover various scenarios such as disaster recovery and sandbox testing, by example.

Abstract: A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern covering the upper sidewall of the contact plug such that the insulation pattern isolates the first barrier metal from exposure. A magnetic tunnel junction pattern may cover a top surface of the contact plug. Each element of the contact plug, the first barrier metal, and the insulation pattern may be in a contact hole of a first interlayer dielectric layer.

Abstract: Systems, apparatuses, and methods for implementing per-page control of physical address space distribution among memory modules are disclosed. A computing system includes a plurality of processing units coupled to a plurality of memory modules. A determination is made as to which physical address space distribution granularity to implement for physical memory pages allocated for a first data structure. The determination can be made on a per-data-structure basis (e.g., file, page, block, etc.) or on a per-application-basis. A physical address space distribution granularity is encoded as a property of each physical memory page allocated for the first data structure, and physical memory pages of the first data structure distributed across the plurality of memory modules based on a selected physical address space distribution granularity.

Abstract: Examples disclosed herein relate to programmable memory-side cache management. Some examples disclosed herein may include a programmable memory-side cache and a programmable memory-side cache controller. The programmable memory-side cache may locally store data of a system memory. The programmable memory-side cache controller may include programmable processing cores, each of the programmable processing cores configurable by cache configuration codes to manage the programmable memory-side cache for different applications.

Abstract: Provided are a computer program product, system, and method for considering a density of tracks to destage in groups of tracks to select groups of tracks to destage. Groups of tracks in the cache are scanned to determine whether they are ready to destage. A determination is made as to whether the tracks in one of the groups are ready to destage in response to scanning the tracks in the group. A density for the group is increased in response to determining that the group is not ready to destage. The group is destaged in response to determining that the density of the group exceeds a density threshold.

Abstract: A resource management and task allocation controller for installation in a multicore processor having a plurality of interconnected processor elements providing resources for processing executable transactions, at least one of said elements being a master processing unit, the controller being adapted to communicate, when installed, with each of the processor elements including the master processing unit, and comprising control logic for allocating executable transactions within the multicore processor to particular processor elements in accordance with pre-defined allocation parameters.

Abstract: According to one embodiment, a data storage device includes a first storage unit, a second storage unit, a first queue, a second queue, and a distributor. The second storage unit is used as a cache of the first storage unit and has a lower write transfer rate and a faster response time than the first storage unit. The first queue corresponds to the first storage unit. The second queue corresponds to the second storage unit. The distributor distributes a write command received presently from a host to one of the first and second queues in which the number of write commands registered presently is smaller.

Abstract: A data accessing method includes: determining whether a preset cache area has cached data that a read target address points to when receiving a read instruction that includes the read target address; and finding a cache address corresponding to the read target address according to a first mapping relationship if the preset cache area has cached the data that the read target address points to, and reading data that the cache address points to from the preset cache area, where the first mapping relationship is used to record a correspondence between the target address and the cache address; orreading, from non-volatile storage space, the data that the read target address points to if the preset cache area has not cached the data that the read target address points to. By means of the method, data read errors caused by write interference can be reduced.

Abstract: A system for reducing data center latency including a webserver having a processor, a memory system controller, external memory, cache memory including a plurality of cache blocks, where each cache block includes provider parameters and at least one user identifier (ID), and program memory including code segments executable by the processor. In an embodiment, the webserver receives a request sent by a requestor having requestor parameters including at least a requestor ID and a user ID, identifies a predictive cache block set; formulates a reply based, at least in part, upon a probability that a number of replies associated with a user ID of the predictive cache block set will exceed a frequency floor number within a predetermined period of time; and sends the reply to the requestor.

Abstract: Systems, apparatuses, and methods for implementing a hybrid cache. A processor may include a hybrid L2/L3 cache which allows the processor to dynamically adjust a size of the L2 cache and a size of the L3 cache. In some embodiments, the processor may be a multi-core processor and there may be a single cache partitioned into a logical L2 cache and a logical L3 cache for use by the cores. In one embodiment, the processor may track the cache hit rates of the logical L2 and L3 caches and adjust the sizes of the logical L2 and L3 cache based on the cache hit rates. In another embodiment, the processor may adjust the sizes of the logical L2 and L3 caches based on which application is currently being executed by the processor.