Abstract: One embodiment provides an apparatus. The apparatus includes collector circuitry to capture processor trace (PT) data from a PT driver. The PT data includes a first target instruction pointer (TIP) packet including a first runtime target address of an indirect branch instruction of an executing target application. The apparatus further includes decoder circuitry to extract the first TIP packet from the PT data and to decode the first TIP packet to yield the first runtime target address. The apparatus further includes control flow validator circuitry to determine whether a control flow transfer to the first runtime target address corresponds to a control flow violation based, at least in part, on a control flow graph (CFG). The CFG including a plurality of nodes, each node including a start address of a first basic block, an end address of the first basic block and a next possible address of a second basic block or a not found tag.

Abstract: Systems and methods for caching data from a plurality of virtual machines may comprise detecting, using a computer processor executing cache management software, initiation of migration of a cached virtual machine from a first virtualization platform to a second virtualization platform, disabling caching for the virtual machine on the first virtualization platform, detecting completion of the migration of the virtual machine to the second virtualization platform, and enabling caching for the virtual machine on the second virtualization platform.

Abstract: An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory that includes multiple memory cells arranged in multiple planes that each includes one or more blocks of the memory cells. The storage circuitry is configured to apply a multi-plane storage operation to multiple blocks simultaneously across the respective planes. In response to detecting that the multi-plane storage operation has failed, the storage circuitry is configured to apply a single-plane storage operation to one or more of the blocks that were accessed in the multi-plane storage operation, including a given block, and to identify the given block as a bad block if the single-plane operation applied to the given block fails. The storage circuitry is further configured to store data in the blocks that were accessed in the multi-plane operation but were not identified as bad blocks.

Abstract: A data processing apparatus has multiple caches and a controller for controlling the caches. The controller and caches communicate over a first network and a second network. The first network is used for unicast communication from the controller to a specific one of the caches. The second network is used for communication of a multicast communication from the controller to two or more of the caches.

Abstract: Example apparatus and methods provide a log structured block device for a hard disk drive (HDD). Data that is to be stored on an HDD is serialized and written as a series of data blocks using a sequential write. Information about where individual data blocks were supposed to be written (e.g., actual address, neighboring data blocks), where data blocks were actually written, and how often data blocks are accessed is maintained. During garbage collection, data blocks that are being accessed with similar frequencies may be relocated together, with the most frequently accessed (e.g., hottest) data blocks migrating to the outer cylinders of the disk and the least frequently accessed (e.g., coldest) data blocks migrating to the inner cylinders. Blocks stored in the same temperature regions that were intended to be located together when written may be repositioned to facilitate sequential reads.

Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

Abstract: Embodiments provide for a processor comprising a cache, a prefetcher to select information according to a prefetcher algorithm and to send the selected information to the cache, and a prefetch tuning buffer including tuning state for the set of candidate prefetcher algorithms, wherein the prefetcher is to adjust operation of the prefetcher algorithm based on the tuning state.

Abstract: A computing system includes a processor and a memory unit that stores program instructions. The system purges an entry from an address translation cache in response to the processor executing the program instructions to perform issuing, via an operating system running on the computing system, a command indicating a request to perform an I/O transaction requiring a translation entry. A host bridge monitors a total data length of the address translation entry to be transferred during the I/O transaction. An address translation entry is selected from an address translation table, loaded into the address translation cache, and data corresponding to the I/O transaction is transferred using the selected address translation entry. The host bridge automatically purges the selected address translation entry from the address translation cache in response to determining the transferred amount of data matches the total data length for the address translation entry.

Abstract: Disclosed aspects relate to memory affinity management in a shared pool of configurable computing resources that utilizes non-uniform memory access (NUMA). An access relationship is monitored between a set of hardware memory components and a set of software assets. A set of memory affinity data is stored. The set of memory affinity data indicates the access relationship between the set of software assets and the set of hardware memory components. Using the set of memory affinity data, a NUMA utilization configuration with respect to the set of software assets is determined. Based on the NUMA utilization configuration, a set of accesses pertaining to the set of software assets and the set of hardware memory components is executed.

Abstract: In an aspect, a cache memory device receives a request to read an instruction or data associated with a memory device. The request includes a first realm identifier and a realm indicator bit, where the first realm identifier enables identification of a realm that includes one or more selected regions in the memory device. The cache memory device determines whether the first realm identifier matches a second realm identifier in a cache tag when the instruction or data is stored in the cache memory device, where the instruction or data stored in the cache memory device has been decrypted based on an ephemeral encryption key associated with the second realm identifier when the first realm identifier indicates the realm and when the realm indicator bit is enabled. The cache memory device transmits the instruction or data when the first realm identifier matches the second realm identifier.

Abstract: A computing resource service provider may operate a build service configured to store data object on behalf of a customer of the computing resource service provide. The build service may receive a stream of data objects including object objects that reference one or more other data objects. A Bloom filter may be used to determine whether a one or more referenced data objects have been previously processed by the build service. This may enable the build service to reorder processing of the data object based at least in part on whether the one or more referenced data objects have previously been processed by the build service.

Abstract: Techniques relate to handling outstanding cache miss prefetches. A processor pipeline recognizes that a prefetch canceling instruction is being executed. In response to recognizing that the prefetch canceling instruction is being executed, all outstanding prefetches are evaluated according to a criterion as set forth by the prefetch canceling instruction in order to select qualified prefetches. In response to evaluating, a cache subsystem is communicated with to cause canceling of the qualified prefetches that fit the criterion. In response to successful canceling of the qualified prefetches, a local cache is prevented from being updated from the qualified prefetches.

Abstract: Machines, systems and methods for recovering data objects in a distributed data storage system, the method comprising storing one or more replicas of a first data object on one or more clusters in one or more data centers connected over a data communications network; recording health information about said one or more replicas, wherein the health information comprises data about availability of a replica to participate in a restoration process; calculating a query-priority for the first data object; querying, based on the calculated query-priority, the health information for the one or more replicas to determine which of the one or more replicas is available for restoration of the object data; calculating a restoration-priority for the first data object based on the health information for the one or more replicas; and restoring the first data object from the one or more of the available replicas, based on the calculated restoration-priority.

Abstract: A memory system implements a plurality of cache eviction policies and optionally a plurality of virtual address modification policies. A cache storage unit of the memory system has a plurality of cache storage sub-units. The cache storage unit is optionally managed by a cache management unit in accordance with the cache eviction polices. The cache storage sub-units are allocated for retention of information associated with respective memory addresses and are associated with the cache eviction policies in accordance with the respective memory addresses. For example, in response to a reference to an address that misses in a cache, the address is used to access a page table entry having an indicator specifying an eviction policy to use when selecting a cache line from the cache to evict in association with allocating a cache line of the cache to retain data obtained via the address.

Abstract: A method includes using a network interface controller to monitor a transmit ring, wherein the transmit ring comprises a circular ring data structure that stores descriptors, wherein a descriptor describes data and comprises a guest bus address that provides a virtual memory location of the data. The method also includes using the network interface controller to determine that a descriptor has been written to the transmit ring. The method further includes using the network interface controller to attempt to retrieve a translation for the guest bus address. The method includes using the network interface controller to read the descriptor from the transmit ring.

Abstract: A method of operating a memory device that includes at least one sub-memory supporting a cache mode and a memory mode, the method including receiving a mode change signal instructing the memory device to change an operation mode of the at least one sub-memory from the cache mode to the memory mode; and changing the operation mode of the at least one sub-memory from the cache mode to the memory mode without flushing the at least one sub-memory, according to the mode change signal.

Abstract: Machines, systems and methods for recovering data objects in a distributed data storage system, the method comprising storing one or more replicas of a first data object on one or more clusters in one or more data centers connected over a data communications network; recording health information about said one or more replicas, wherein the health information comprises data about availability of a replica to participate in a restoration process; calculating a query-priority for the first data object; querying, based on the calculated query-priority, the health information for the one or more replicas to determine which of the one or more replicas is available for restoration of the object data; calculating a restoration-priority for the first data object based on the health information for the one or more replicas; and restoring the first data object from the one or more of the available replicas, based on the calculated restoration-priority.

Abstract: In one embodiment, a computing device receives receive a request for particular content associated with an application. The device may determine, based on a first recycling policy associated with a first recycler, that the first recycler associated with the application includes a display object that is capable of being used for containing the particular content. The device may encapsulate the display object with the particular content in a wrapper object and return the wrapper object encapsulating the display object in response to the request. The device may receive an indication that the display object is no longer needed, and extract the display object from the wrapper object. The display object may be stored in the first recycler. The wrapper object without the display object may be disposed in accordance with a second recycling policy associated with a second recycler associated with an operating system of the computing device.

Abstract: A mechanism is provided for destaging one or more data files in a volatile memory using a set of heat registers associated with each data file. Responsive to receiving a notification indicating that free space within the volatile memory has fallen below a predetermined threshold, a rule is implemented, based on values associated with the set of heat registers assigned to each data file, to identify a data file to move to a non-volatile memory, where the set of heat registers comprises a content heat register, an access heat register, and a metadata heat register. The data file is moved to the nonvolatile memory. Responsive to determining that the free space fails to have risen above the predetermined threshold, the operations are repeated until the free space rises above the predetermined threshold at which time the set of heat registers assigned to the data files that were moved are deassigned.

Abstract: Apparatuses, computer readable mediums, and methods of processor unit testing using cache resident testing are disclosed. The method may include loading a test program in a cache on a chip comprising one or more processor units. The method may include the one or more processor units executing the test program to generate one or more results. The method may include redirecting a first memory reference to the cache, wherein the first memory reference is generated during the execution of the test program. The method may include determining whether the one or more generated results match one or more test results. The method may include redirecting a memory request to a memory location resident in the cache if the memory request includes a memory location not resident in the cache. The method may include redirecting a memory request to the cache if the memory request is not directed to the cache.

Abstract: Cache memory mapping techniques are presented. A cache may contain an index configuration register. The register may configure the locations of an upper index portion and a lower index portion of a memory address. The portions may be combined to create a combined index. The configurable split-index addressing structure may be used, among other applications, to reduce the rate of cache conflicts occurring between multiple processors decoding the video frame in parallel.

Abstract: Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system is disclosed. In some aspects, a compressed memory controller (CMC) provides an LLC comprising multiple LLC lines, each providing a plurality of sub-lines the same size as a system cache line. The contents of the system cache line(s) stored within a single LLC line are compressed and stored in system memory within the memory sub-line region corresponding to the LLC line. A master table stores information indicating how the compressed data for an LLC line is stored in system memory by storing an offset value and a length value for each sub-line within each LLC line. By compressing multiple system cache lines together and storing compressed data in a space normally allocated to multiple uncompressed system lines, the CMC enables compression sizes to be smaller than the memory read/write granularity of the system memory.

Abstract: A mobile terminal and related repair method is disclosed. The method includes: obtaining current storage integrity information of the mobile terminal; matching the current storage integrity information and original storage integrity information, when the matching fails, connecting to the server, obtaining original system partition document from the server, and repairing the system partition according to the original system partition document.

Abstract: A storage control method executed by a processor included in a storage control device, the storage control device being coupled to a storage including a media cache, the storage being capable of executing a read-modify-write process, the storage control method includes receiving, from the storage, usage information indicating a usage status of the media cache; receiving a write request to write an unaligned data in the storage; transmitting an unaligned data corresponding to the write request to the storage, when the usage information indicates that an available capacity of the media cache is equal to or smaller than a threshold; generating an aligned data from the unaligned data corresponding to the write request by executing the read-modify-write process within the storage control device, when the usage information indicates that the available capacity of the media cache is larger than the threshold; and transmitting the generated aligned data to the storage.

Abstract: Provided is contribution for improving response performance. For that, a storage system includes a control device and a memory device that is connected to the control device via an interconnected network, wherein the memory device includes a data memory unit that stores data and a comparison write unit that performs a comparison write process of comparing first data specified by the control device with second data stored into a predetermined area in the data memory means and determining whether to update data in the predetermined area depending on a result of the comparison, and wherein the control device includes a read command issuance unit that issues a read command to the memory device; a write buffer memory unit that holds data that has been read based on the read command; and a comparison write command unit that designates data written to the write buffer memory means as the first data and instructs, in the form of a comparison write command, the memory device to perform the comparison write process.

Abstract: A system and method for efficiently caching metadata in a storage system. Addresses from a plurality of I/O accesses to the storage system are captured and then a frequency domain representation of the addresses is generated. The frequency domain representation is used to measure the randomness of the various applications which are accessing the storage system. Scores are generated based on the measure of randomness, and scores are assigned to the various regions of the logical address space. Scores are then assigned to the metadata pages which are stored in the cache based on the region of the logical address space to which the metadata pages correspond. The scores are used when determining which metadata pages to evict from the cache. The cache will attempt to evict those metadata pages which correspond to regions of the logical address space that are servicing random I/O accesses.

Abstract: An apparatus includes a buffer, a sequencing circuit, and an execution unit. The buffer may be configured to store a plurality of instructions. Each of the plurality of instructions may be in a first thread. In response to determining that the first instruction depends on the value of a condition variable and to determining that a count value is below a predetermined threshold, the sequencing circuit may be configured to add a wait instruction before the first instruction. The execution unit may be configured to delay execution of the first instruction for an amount of time after executing the wait instruction. The sequencing circuit may be further configured to maintain the plurality of instructions in the first buffer after executing the wait instruction, and to decrement the count value in response to determining that the value of the condition variable is updated within the amount of time.

Abstract: Circuitry to facilitate verification of the integrity of a target instance of a computing platform is described. Specifically, a processor can include circuitry to measure execution parameter values during an execution of a portion of a software image, wherein the execution parameter values represent a sequence of execution states that the target instance of the computing platform passes through while executing the portion of the software image. During operation, a software image can be generated that, when executed at the target instance of the computing platform, verifies integrity of the computing platform. Next, the software image can be sent to the target instance of the computing platform. The processor at the target instance of the computing platform can execute the software image, thereby enabling the verification of the integrity of the target instance of the computing platform.

Abstract: A method of re-mapping a boot loader image from a first to a second address space includes: determining a difference in a virtual address of the boot loader image in the first and second address spaces; building page tables for a third address space that maps a code section within the boot loader image at first and second address ranges separated by the difference and the code section causes execution to jump from a first instruction in the first address range to a second instruction in the second address range; executing an instruction of the code section in the first address space using pages tables for the first address space; executing the first instruction and then the second instruction using the page tables for the third address space; and executing an instruction of the boot loader image in the second address space using page tables for the second address space.

Abstract: A method for execution by one or more processing modules of a dispersed storage network (DSN), the method begins by monitoring an encoded data slice access rate to produce an encoded data slice access rate for an associated rebuilding rate of a set of rebuilding rates. The method continues by applying a learning function to the encoded data slice access rate based on a previous encoded data slice access rate associated with the rebuilding rate to produce an updated previous encoded data slice access rate of a set of previous encoded data slice access rates. The method continues by updating a score value associated with the updated previous encoded data slice access rate and the rebuilding rate and selecting a slice access scheme based on the updated score value where a rebuild rate selection will maximize a score value associated with an expected slice access rate.

Abstract: A programmable controller system includes a control device; a functional device including a buffer memory and a general-purpose logic unit; and a peripheral device that creates a user program. The peripheral device includes a circuit setting unit, which sets operation data indicating the operation of a logic of the general-purpose logic unit; and a circuit-control-parameter setting unit, which sets a circuit control parameter representing the relation between a buffer memory address indicating an address in the buffer memory and a logic address indicating an address in the logic. The functional device includes a circuit control unit that transfers the operation data to the logic address on the basis of the specified buffer memory address and the circuit control parameter.

Abstract: Machines, systems and methods for recovering data objects in a distributed data storage system, the method comprising storing one or more replicas of a first data object on one or more clusters in one or more data centers connected over a data communications network; recording health information about said one or more replicas, wherein the health information comprises data about availability of a replica to participate in a restoration process; calculating a query-priority for the first data object; querying, based on the calculated query-priority, the health information for the one or more replicas to determine which of the one or more replicas is available for restoration of the object data; calculating a restoration-priority for the first data object based on the health information for the one or more replicas; and restoring the first data object from the one or more of the available replicas, based on the calculated restoration-priority.

Abstract: A solid state drive includes a controller with a hardware interface to fewer planes of memory cells than included in the nonvolatile storage. For example, a controller hardware interface can include a 1N plane interface coupled to a nonvolatile storage device with 2N planes of memory cells. For data access transactions between the controller and the nonvolatile storage device, first and second consecutive 1N plane command sequences are interpreted as a single 2N plane command sequence.

Abstract: The techniques and systems described herein are directed to providing deep integration of digital signal processing (DSP) operations with a general-purpose query processor. The techniques and systems provide a unified query language for processing tempo-relational and signal data, provide mechanisms for defining DSP operators, and support incremental computation in both offline and online analysis. The techniques and systems include receiving streaming data, aggregating and performing uniformity processing to generate a uniform signal, and storing the uniform signal in a batched columnar representation. Data can be copied from the batched columnar representation to a circular buffer, where DSP operations are applied to the data. Incremental processing can avoid redundant processing.

Abstract: Instruction prefetching in a computer processor includes, upon a miss in an instruction cache for an instruction cache line: retrieving, for the instruction cache line, a prefetch prediction vector, the prefetch prediction vector representing one or more cache lines of a set of contiguous instruction cache lines following the instruction cache line to prefetch from backing memory; and prefetching, from backing memory into the instruction cache, the instruction cache lines indicated by the prefetch prediction vector.

Abstract: Test code and test data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing test code and test data in the non-naturally aligned data boundaries as described herein allows test code and data to be replicated throughout a cache memory while preserving double word and quad word boundaries in segments of the replicated test code and test data. Coherency of the processor memory can be tested when the same cache line from the level two (L2) cache is simultaneously in both the level one (L1) instruction cache and the L1 data cache.

Abstract: Machines, systems and methods for recovering data objects in a distributed data storage system, the method comprising storing one or more replicas of a first data object on one or more clusters in one or more data centers connected over a data communications network; recording health information about said one or more replicas, wherein the health information comprises data about availability of a replica to participate in a restoration process; calculating a query-priority for the first data object; querying, based on the calculated query-priority, the health information for the one or more replicas to determine which of the one or more replicas is available for restoration of the object data; calculating a restoration-priority for the first data object based on the health information for the one or more replicas; and restoring the first data object from the one or more of the available replicas, based on the calculated restoration-priority.

Abstract: A memory-efficient last level cache (LLC) architecture is described. A processor implementing a LLC architecture may include a processor core, a last level cache (LLC) operatively coupled to the processor core, and a cache controller operatively coupled to the LLC. The cache controller is to monitor a bandwidth demand of a channel between the processor core and a dynamic random-access memory (DRAM) device associated with the LLC. The cache controller is further to perform a first defined number of consecutive reads from the DRAM device when the bandwidth demand exceeds a first threshold value and perform a first defined number of consecutive writes of modified lines from the LLC to the DRAM device when the bandwidth demand exceeds the first threshold value.

Abstract: In accordance with various embodiments of the disclosed subject matter, a webpage resource acquisition method, and an apparatus thereof are provided. In some embodiments, the method comprises: obtaining pre-read webpage resources from a web server through a communication network according to a pre-read algorithm; storing raw data of the pre-read webpage resources in a pre-read cache; and in response to receiving a loading instruction to load a target webpage resource, obtaining the raw data of one pre-read webpage resource that corresponds to the target webpage resource from the pre-read cache based on the loading instruction without going through the communication network.

Abstract: A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect. In response to a load-and-reserve request from a first processor core, a first cache memory supporting the first processor core issues on the system interconnect a memory access request for a target cache line of the load-and-reserve request. Responsive to the memory access request and prior to receiving a systemwide coherence response for the memory access request, the first cache memory receives from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the memory access request. In response to the early indication and prior to receiving the systemwide coherence response, the first cache memory initiating processing to update the target cache line in the first cache memory.

Abstract: A processor includes a front end to decode instructions, an execution unit to execute instructions, multiple caches at different cache hierarchy levels, a pipelined prefetcher, and a retirement unit to retire instructions. The prefetcher includes circuitry to receive a demand request for data at a first address within a first line in a memory and, in response, to provide the data at the first address to the execution unit for consumption, to prefetch a second line at a first offset distance from the first line into a mid-level cache, and to prefetch a third line at a second offset distance from the second line into a last-level cache. The prefetcher includes circuitry to prefetch, in response to another demand request, the third line into the mid-level cache, and a fourth line into the last-level cache. The prefetcher enforces minimum or maximum offset distances between prefetched data streams.

Abstract: A method, computer program product, and computer system for receiving, at a first computing device, a first data chunk sent from a second computing device. It may be determined that the first data chunk includes a first type of data. The first data chunk may be stored to a cache operatively coupled to the first computing device based upon, at least in part, determining that the first data chunk includes the first type of data, wherein the cache may include a first storage device type. An acknowledgement of a successful write of the first data chunk to the second computing device may be sent based upon, at least in part, a successful storing of the first data chunk to the cache operatively coupled to the first computing device.

Abstract: A processor core has a store-through upper level cache and a store-in lower level cache. In response to execution of a memory move instruction sequence including a plurality of copy-type instruction and a plurality of paste-type instructions, the processor core transmits a corresponding plurality of copy-type and paste-type requests to the lower level cache, where each copy-type request specifies a source real address and each paste-type request specifies a destination real address. In response to receipt of each copy-type request, the lower level cache copies a respective one of a plurality of data granules from a respective storage location specified by the source real address of that copy-type request into a non-architected buffer. In response to receipt of each paste-type request, the lower level cache writes a respective one of the plurality of data granules from the non-architected buffer to a respective storage location specified by the destination real address of that paste-type request.

Abstract: Systems, apparatuses, and methods for utilizing a programmable memory command sequencer to generate multiple commands from a single memory request. A sequencer receives requests from a host processor and utilizes any of a plurality of programmable routines in response to determining that a given request meets specific criteria. A given programmable routine generates a plurality of memory commands which are then conveyed to a local memory controller and/or one or more remote memory controllers. The host processor programs the sequencer at boot time and updates the sequencer at runtime in response to changing application behavior. In various embodiments, the sequencer generates a variety of error correction routines in response to different requests received from the host processor.

Abstract: Preventing a prefetch memory operation from causing a transaction to abort by receiving by a local processor a prefetch request from a remote processor. Determining whether the prefetch request conflicts with a transaction of the local processor. Responding to at least one of i) a determination that the local processor has no transaction, and ii) a determination that the prefetch request does not conflict with a transaction of the local processor, by providing a requested prefetch data. Responding to a determination that the prefetch request conflicts with a transaction of the local processor by determining an evaluation of the prefetch request. Performing at least one of i) an abort of the prefetch request, ii) a quiesce the prefetch request, iii) a delay in the processing of the prefetch request for a delay period, and iv) an execution of the prefetch request based on the evaluation the prefetch request.

Abstract: A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and an interconnect fabric. In response to a first cache memory snooping on the interconnect fabric a request of an interconnect operation of a second cache memory, the first cache memory allocates a snoop machine to service the request. Responsive to the snoop machine completing its processing of the request and prior to the first cache memory receiving a systemwide coherence response of the interconnect operation, the first cache memory allocates an entry in a data structure to handle completion of processing for the interconnection operation and deallocates the snoop machine. The entry of the data structure protects transfer of coherence ownership of a target cache line from the first cache memory to the second cache memory during a protection window extending at least until the systemwide coherence response is received.

Abstract: Embodiments are directed to perfect physical garbage collection (PPGC) process that uses a NUMA-aware perfect hash vector. The process splits a perfect hash vector (PHVEC) into a number of perfect hash vectors, wherein the number corresponds to a number of nodes having a processing core and associated local memory, directs each perfect hash to a respective local memory of a node so that each perfect hash vector accesses only a local memory, and assigns fingerprints in the perfect hash vector to a respective node using a mask function. The process also performs a simultaneous creation of perfect hash vectors in a multi-threaded manner by scanning the Index once.

Abstract: Systems, methods and/or devices are used to enable using history of I/O sequences to trigger cached read ahead in a non-volatile storage device. In one aspect, the method includes (1) receiving, at a storage device, a plurality of input/output (I/O) requests from a host, the plurality of I/O requests including read requests and write requests to be performed in a plurality of regions in a logical address space of the host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including (a) determining whether the region has a history of sequential read requests during a predetermined time period, and (b) in accordance with a determination that the region has a history of sequential read requests during the predetermined time period, enabling read ahead logic for the region.

Abstract: Preventing a prefetch memory operation from causing a transaction to abort by receiving by a local processor a prefetch request from a remote processor. Determining whether the prefetch request conflicts with a transaction of the local processor. Responding to at least one of i) a determination that the local processor has no transaction, and ii) a determination that the prefetch request does not conflict with a transaction of the local processor, by providing a requested prefetch data. Responding to a determination that the prefetch request conflicts with a transaction of the local processor by determining an evaluation of the prefetch request. Performing at least one of i) an abort of the prefetch request, ii) a quiesce the prefetch request, iii) a delay in the processing of the prefetch request for a delay period, and iv) an execution of the prefetch request based on the evaluation the prefetch request.

Abstract: A data processing system includes a processor core having a store-through upper level cache and a store-in lower level cache. In response to a first instruction, the processor core generates a copy-type request and transmits the copy-type request to the lower level cache, where the copy-type request specifies a source real address. In response to a second instruction, the processor core generates a paste-type request and transmits the paste-type request to the lower level cache, where the paste-type request specifies a destination real address. In response to receipt of the copy-type request, the lower level cache copies a data granule from a storage location specified by the source real address into a non-architected buffer, and in response to receipt of the paste-type request, the lower level cache writes the data granule from the non-architected buffer to a storage location specified by the destination real address.