Abstract: Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly via another memory device, a second port to interface with yet another memory device, and a switch to selectively electrically connect the memory controller to a circuit path leading to the second port or to the memory array, wherein the switch may be responsive to a signal generated by the memory controller.

Abstract: Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has multiple sub-cycle periods within a user period of the user design clock cycle. The method identifies multiple port accesses to a first multi-port memory defined in the user design. The accesses are in a single user design clock cycle. The method maps the multiple port accesses to the first multi-port memory to multiple physical-port memory accesses to a second physical-port memory in the configurable IC during multiple sub-cycles associated with a single user design clock cycle.

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Abstract: The present invention relates to a coarse-grained reconfigurable array, comprising: at least one processor; a processing element array including a plurality of processing elements, and a configuration cache where commands being executed by the processing elements are saved; and a plurality of memory units forming a one-to-one mapping with the processor and the processing element array. The coarse-grained reconfigurable array further comprises a central memory performing data communications between the processor and the processing element array by switching the one-to-one mapping such that when the processor transfers data from/to a main memory to/from a frame buffer, a significant bottleneck phenomenon that may occur due to the limited bandwidth and latency of a system bus can be improved.

Abstract: A multi-core processor system includes a memory controller that includes multiple ports and shared memory that includes physical address spaces divided among the ports. A CPU acquires from a parallel degree information table, the number of CPUs to which software that is to be executed by the multi-core processor system, is to be assigned. After this acquisition, the CPU determines the CPUs to which the software to be executed is to be assigned and sets for each CPU, physical address spaces corresponding to logical address spaces defined by the software to be executed. After this setting, the CPU notifies an address converter of the addresses and notifies the software to be executed of the start of execution.

Abstract: A memory system includes a selection element for selecting a selectable access rate from a plurality of access rates and a memory element for providing or for accepting data at the selectable access rate.

Abstract: In one embodiment, the present invention includes a method to obtain topology information regarding a system including at least one multicore processor, provide the topology information to a plurality of parallel processes, generate a topological map based on the topology information, access the topological map to determine a topological relationship between a sender process and a receiver process, and select a given memory copy routine to pass a message from the sender process to the receiver process based at least in part on the topological relationship. Other embodiments are described and claimed.

Abstract: A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus.

Abstract: Deadlock is avoided in a grid storage system having superior scalability. Provided is a storage subsystem connected to a host computer for receiving a write or read access from the host computer. This storage subsystem includes a plurality of modules respectively having a storage resource, a switch for connecting the plurality of modules, a controller for controlling the transfer of a packet based on the write or read access from the host computer to a target module among the plurality of modules via the switch, and a memory storing a transfer rule of the packet. The controller controls the transfer of the packet based on the transfer rule.

Abstract: A system and method for efficient garbage collection. A general-purpose central processing unit (CPU) partitions an allocated heap according to a generational garbage collection technique. The generations are partitioned into fixed size cards. The CPU marks indications of qualified dirty cards during application execution since the last garbage collection. When the CPU detects a next garbage collection start condition is satisfied, the CPU sends a notification to a special processing unit (SPU) corresponding to a determination of one or more card root addresses, each card root address corresponding to one of said marked indications. The SPU has a single instruction multiple data (SIMD) parallel architecture and may be a graphics processing unit (GPU). The SPU may utilize the parallel architecture of its SIMD core to simultaneously compute multiple card root addresses. Following, the SPU sends these addresses to the CPU to be used in a garbage collection algorithm.

Abstract: A device is disclosed having a memory module that comprises a first memory block, a second memory block, a programmable storage location, and a memory controller. The first memory block of non-volatile memory comprises a plurality of word locations and an address decoder coupled to a first access port of the memory controller. The address decoder to select one of the plurality of word locations for access in response to receiving address information via the first access port. The second memory block comprising a plurality of word locations and an address decoder coupled to a second access port of the memory controller. The address decoder to select one of the plurality of word locations for access in response to receiving address information via the second access port.

Abstract: A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.

Abstract: A write controller controls writing of packet data to a memory, and a read controller controls reading of packet data from the memory. The write controller signals the read controller if a packet is to be discarded. In response to a discard signal from the write controller, the read controller checks whether it is in the midst of processing the packet to be discarded. If the read controller has yet to process the packet to be discarded, then no corrective action is required. However, if the read controller is in the midst of processing the packet to be discarded, then the read controller adjusts its memory read pointer to point to the position in the memory at which it began reading the packet to be discarded.

Abstract: An apparatus and method for managing a rights object by backing up and restoring the rights object between a host device and a multimedia card are provided. The apparatus includes an input unit that receives an order signal from a user, a rights-object-managing unit that determines whether the rights object can be backed up and restored based on rights object information when the order signal is input, and backs up and restores the rights object according to a result of the determination, and an information-managing unit that manages information related to movement and removal of the rights object and information on the backed up and restored rights object.

Abstract: A switch 100 includes a plurality of ports 101 for exchanging data. A shared memory 102 enables the exchange of data between first and second ones of the ports 101 and includes an array 202 of memory cells arranged as a plurality of rows and a single column having width equal to a predetermined word-width and circuitry 202, 204, 206, 208 for writing selected data presented at the first one of the ports 101 to a selected row in the array as a word of the predetermined word-width during a first time period and for reading the selected data from the selected row as a word of the predetermined wordwidth during a second time period for output at a second one of the ports 101.

Abstract: A Common System Storage Repository replaces all the different system support storages distributed across a server system topology transparent to various subsystems by providing a central non-volatile repository for all the different system data. Each of the various subsystems communicate with the Common System Storage Repository via the individual system support storage interfaces.

Abstract: According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware threads identified as high priority hardware threads for processing by a multi-threaded processor in communication with the cache; assigning high priority hardware threads to the selected first subset; monitoring a cache usage of a high priority hardware thread assigned to the selected first subset of plurality of cache ways; and reassigning the assigned high priority hardware thread to any cache way of the plurality of cache ways if the cache usage of the high priority hardware thread exceeds a predetermined inactive cache usage threshold value based on the monitoring.

Abstract: In an information processing system, a plurality of information processing devices CHIP0 and CHIP1 are connected to multiport memory MPMEM0 that has a plurality of ports, and memory areas in multiport memory MPMEM0 can be altered to memory areas occupied by particular ports and memory areas shared by a plurality of ports. At such times, immediately after the occurrence of a request from a port, the status of this request may be supplied from other ports.

Abstract: The present invention relates to a device having a shared memory and a code data transmitting method. According to an embodiment of the present invention, the digital processing device can include n processors, n being a natural number of 2 or greater; and a shared memory, coupled to each of the processors through independent buses and having a boot section allotted, the boot section being for writing a boot program code to be used for booting of at least one processor.

Abstract: A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.

Abstract: Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The memory device may include a configuration register that stores configuration data indicative of the mapping of the memory banks to the ports. In response to the configuration data, for example, a steering logic may couple each of the ports either to one or all of the native memory banks or to one or all of the non-native memory banks.

Abstract: An address generation system and method is provided for internally storing and thereafter producing an address to be sent to a memory device. The address that is stored need not be sent from an external address bus at each clock cycle, but the processing can remain internal to the memory device. The burst-block starting address can be stored in the mirror register and output from a selector circuit, such as a multiplexer, when that address is chosen. Otherwise, the multiplexer can simply perform its normal operation of selecting between an address pointed to by a counter, the external address, or the incremented counter output, based on the state of the external counter control signals. The system includes a mirror register, a counter, and a multiplexer that selects either the mirror register stored address or the internally processed address.

Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.

Abstract: A system for managing a circular buffer memory includes a number of data writers, a number of data readers, a circular buffer memory; and logic configured to form a number of counters, form a number of temporary variables from the counters, and allow the data writers and the data readers to simultaneously access locations in the circular buffer memory determined by the temporary variables.

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

Abstract: Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has multiple sub-cycle periods within a user period of the user design clock cycle. The method identifies multiple port accesses to a first multi-port memory defined in the user design. The accesses are in a single user design clock cycle. The method maps the multiple port accesses to the first multi-port memory to multiple physical-port memory accesses to a second physical-port memory in the configurable IC during multiple sub-cycles associated with a single user design clock cycle.

Abstract: A system and method for controlling access to a computer provides for loose security within a local network while retaining strong security against external access to the network. In one embodiment, a user has access to trusted nodes in a secured group within an unmanaged network, without being required to choose, enter and remember a login password. To establish such a secure blank password or one-click logon account for the user on a computer, a strong random password is generated and stored, and the account is designated as a blank password account. If the device is part of a secured network group, the strong random password is replicated to the other trusted nodes. When a user with a blank password account wishes to log in to a computer, the stored strong random password is retrieved and the user is authenticated.

Abstract: A mechanism is provided for providing an improved reconfigurable cache. The mechanism partitions a large cache into inclusive cache regions with equal-ratio size or other coarse size increase. The cache controller includes an address decoder for the large cache with a large routing structure. The cache controller includes an additional address decoder for the small cache with a smaller routing structure. The additional address decoder for the small cache reduces decode, array access, and data return latencies. When only a small cache is actively in use, the rest of the cache can be turned into low-power mode to save power.

Abstract: A method and apparatus are provided for sharing multipath-accessible memory between a plurality of processors, the method including connecting the plurality of processors in read/write communication to a same shared memory region; connecting the plurality of processors in read communication to a same semaphore area; selectably connecting one of the plurality of processors in write communication to the same semaphore area; exchanging shared memory access command messages between two processors for negotiating access to the same shared memory region; and storing protected variables indicative of the currently negotiated access to the same shared memory region in the same semaphore area, wherein the shared memory region has a channel relative to each processor, each channel having at least one buffer disposed for transferring a plurality of data packets in a burst mode.

Abstract: A device that includes multiple processors that are connected to multiple level-one cache units. The device also includes a multi-port high-level cache unit that includes a first modular interconnect, a second modular interconnect, multiple high-level cache paths; whereas the multiple high-level cache paths comprise multiple concurrently accessible interleaved high-level cache units. Conveniently, the device also includes at least one non-cacheable path. A method for retrieving information from a cache that includes: concurrently receiving, by a first modular interconnect of a multiple-port high-level cache unit, requests to retrieve information. The method is characterized by providing information from at least two paths out of multiple high-level cache paths if at least two high-level cache hit occurs, and providing information via a second modular interconnect if a high-level cache miss occurs.

Abstract: A memory module and a corresponding method for handling atomic operations in a multi-level memory system (MLMS) are provided. The memory module receives load and store operations of the atomic operations from a data processing engine (DPE) or an upper level memory module (ULMM). The memory module logs the load operation and/or forward the load operation to a lower level memory module (LLMM) according to predetermined conditions such as cacheability or whether there is a data hit or not. In addition, the memory module executes the store operation, inhibits the store operation, or forwards the store operation to an LLMM according to predetermined conditions such as cacheability, data hit, or whether there is a matching load operation logged in the memory module. The memory module and the method ensure correct, consistent and efficient execution of atomic operations for all DPEs sharing the MLMS.

Abstract: Systems and methods for accessing common registers in a multi-core processor are disclosed. In an embodiment a method may comprise streaming at least one transaction from one of a plurality of processing cores in a core domain directly to a register domain. The method may also comprise reassembling the at least one streamed transaction in the register domain for data access operations at the common registers.

Abstract: A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value.

Abstract: A programmable logic device may include first and second ports in data communication with a memory block including a pair of address areas. A system using the programmable logic device may include the programmable logic device in data communication with a central processing unit and a controller. A method of using the programmable logic device may include generating a command from the central processing unit based on data read from one of the address areas and written to the second address area wherein the address areas are associated with a common memory address.

Abstract: A multi-port memory, comprising: a memory array made of a plurality of memory cells arranged at intersection points between a plurality of bit lines and a plurality of word lines, the memory array being divided into n (an integer of 2 or greater) memory banks; m (an integer of 2 or greater) input/output ports, each independently performing input and output of a command, an address, data to and from each of the memory banks; and a route switching circuit that sets signal for the command, address, and data between the memory banks and the input/output ports, the route switching circuit controlling a connection state of signal lines between the plurality of input/output ports and the plurality of memory banks.

Abstract: An integrated device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access. An input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros. As connection interconnects, command information interconnects and data interconnects are included. The command information interconnects are formed by private interconnects, while the data interconnects are formed by private interconnects for at least the second direction interconnects.

Abstract: A method of validating a digital certificate comprises retrieving from a first data store a digital certificate, retrieving from a second data store a plurality of certificate revocation lists (CRLs), and selecting one of the plurality of CRLs to validate the digital certificate as of a date which is before the current date.

Abstract: Disclosed are computer systems, a plurality of methods and a computer program for preventing a delay in execution time of one or more instructions. The computer system includes: a lock unit for executing an instruction to acquire exclusive-use of the external resource and an instruction to release the exclusive-use of the external resource in the one or more threads; a counter unit for increasing or decreasing a value of a corresponding one of counters respectively associated with the threads; and a controller for controlling an execution order of the instructions to be executed by exclusively using the external resource and instructions that causes a delay in the execution time of the instructions to be executed by exclusively using the external resource.

Abstract: A device having a shared memory and a shared memory controlling method are disclosed. A digital processing device can include a shared memory, having a storage area including at least one common section, coupled to each of the processors through separate buses and outputting access information to whether a processor is accessing a common section. With the present invention, each processor can efficiently use or/and control a shared memory by using access information.

Abstract: An apparatus for executing an atomic memory transaction comprises a processing core in a multi-processing core system, where the processing core is configured to store an atomic program in a cache line. The apparatus further comprises an atomic program execution unit that is configured to execute the atomic program as a single atomic memory transaction with a guarantee of forward progress.

Abstract: A system and method for providing roaming access on a network are disclosed. The network includes a plurality of wireless and/or wired access points. A user may access the network by using client software on a client computer (e.g., a portable computing device) to initiate an access procedure. In response, a network management device operated by a network provider may return an activation response message to the client. The client may send the user's username and password to the network provider. The network provider may rely on a roaming partner, another network provider with whom the user subscribes for internet access, for authentication of the user. Industry-standard methods such as RADIUS, CHAP, or EAP may be used for authentication. The providers may exchange pricing and service information and account information for the authentication session. A customer may select a pricing and service option from a list of available options.

Abstract: Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port.

Abstract: A playback apparatus which plays back video or music contents, includes: a playback unit playing back the video or music contents recorded on a recording medium; an output unit outputting the video or music contents played back in the playback unit; and a control unit controlling at least an operation of the playback unit, wherein in the video or music contents, a quick reference mark is set at multiple places, in response to user manipulation, the control unit finds a start of a sequence in accordance with the quick reference mark to control the operation of the playback unit to play back the video or music contents, in response to user manipulation for the quick reference, the control unit varies a priority that expresses a degree served for the quick reference, and for the mark having a low priority, the control unit accepts no user manipulation for quick reference.

Abstract: A memory system including a plurality of ports and a memory core having a plurality of memory banks. Access requests received at the ports are broadcast to the memory banks. Multiple memory banks may be concurrently accessed in response to access requests received on different ports. A memory controller provides the access requests to the memory system, and ensures that a single memory bank is not concurrently accessed by different ports. All access requests are processed with the same latency. If the memory banks include memory cells that must be periodically refreshed, then the memory controller also provides refresh requests to the memory banks. Because multiple memory banks may be concurrently accessed in response to access requests provided on different ports, the memory banks can operate at a lower frequency than the ports.

Abstract: A multiprocessor system having a direct access boot operation and a direct access boot method are provided to substantially reduce a boot error of processor that does not provide a memory link architecture in the multiprocessor system.

Abstract: A multiport semiconductor memory device and a multiprocessor system employing the same directly accesses a shared nonvolatile memory. The multiport semiconductor memory device includes a plurality of port units coupled with respective corresponding processors. A shared memory area is accessed by both the processors through the port units. A data path control unit controls a data path between the shared memory area and the port units and data transmission/reception is performed between the processors through the shared memory area. An access authority information storage unit is positioned outside of the memory cell array and stores information for an access authority of nonvolatile memory and provides the information to the processors. Accordingly, a direct access is performed by a processor indirectly connected to nonvolatile memory.

Abstract: A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register.

Abstract: An apparatus includes a programmable device that has an interface and command ports that can each receive commands, each command requesting an information transfer through the interface. A technique relating to the device involves: selecting during field programming a number of priority definitions; configuring each of the priority definitions during field programming to specify an order of priority for a group of the command ports; and using the priority definitions in succession and, for each of the priority definitions, causing a command to be accepted from the command port of highest priority that contains a command.

Abstract: A protocol chip and a communication conversion circuit are provided in a channel adapter package that is in charge of communications with a host. The communication conversion circuit communicates with the protocol chip using a procedure that conforms to a communication protocol. The communication conversion circuit communicates with a microprocessor using a procedure that is common to multiple communication protocols. It appears from the microprocessor as though communications are being carried out with the same type of channel adapter package.

Abstract: A system and method for writing, by a sender, a message into blocks of a memory space, the memory space being shared by the sender of the message and a receiver of the message, and sending, by the sender, an interrupt corresponding to the message.