Abstract: An integrated device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access. An input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros. As connection interconnects, command information interconnects and data interconnects are included. The command information interconnects are formed by private interconnects, while the data interconnects are formed by private interconnects for at least the second direction interconnects.

Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

Abstract: Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data.

Abstract: A semiconductor memory device comprises a memory unit having a first and a second port and including plural banks; a bank address conversion circuit operative to convert a first bank address fed from external into a second bank address different from the first bank address and operative to supply the first bank address to one of the first and second ports and supply the second bank address to the other of the first and second ports; and a write data conversion circuit operative to convert input data fed from external into write data different from the input data and operative to supply the input data to one of the first and second ports and supply the converted write data to the other of the first and second ports.

Abstract: Systems and methods to respond to schedule commands at a memory controller are disclosed. A transmission error between a first memory controller port and a first redrive device may be detected. A first corrective action may be initiated at the first memory controller port in response to the detection of the transmission error. A particular method may include determining that a second memory controller port initiated a second corrective action. Incoming read commands may be distributed based on a comparison of the first corrective action and the second corrective action.

Abstract: Provided is a storage system. The storage system includes: a hard disk drive, and a storage controller for reading/writing data from/to the hard disk drive, the storage controller including: at least one interface connected to a host computer through a network; and a plurality of processors connected to the interface through an internal network. The storage system is characterized in that: the processor provides at least one logical access port to the host computer; and the interface stores routing information including a processor which processes an access request addressed to the logical access port, extracts an address from the received access request upon reception of the access request from the host computer, specifies the processor which processes the received access request based on the routing information and the extracted address, and transfers the received access request to the specified processor.

Abstract: Read commands on a mirrored memory computer system are scheduled by utilizing information about pending memory access requests. A conflict queue is configured to track a read/write queue associated with each of a plurality of memory ports on the mirrored memory system. The conflict queue determines a predicted latency on each memory port based on the contents of each of the read/write queues. A compare logic unit is coupled to the conflict queue, wherein the compare logic unit compares a predicted latency of a primary memory and a mirrored memory and schedules read commands to the memory port with the lowest predicted latency.

Abstract: A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas, and a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area.

Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface are some operations performed by the controller. The controller determines a width for a Data bus while assigning a target device address to each of the memory devices.

Abstract: A shared memory system including: a shared memory includes a plurality of memory banks; a plurality of input ports; a plurality of input buffers; and a controller for controlling writing-into and reading out of the shared memory and for transferring data from each of the input buffers to the shared memory, wherein when one of the memory banks is cycled back next to the starting memory bank, another memory block is to be selected next for writing the remainder of a series of data, said controller controlling each of the input buffers to transfer a plurality of series of data to the shared memory successively with a time gap while switching to said another memory block, said controller offsetting a start memory bank in said another block for start writing the remainder of the series of data by an amount of memory banks corresponding to the time gap.

Abstract: Bandwidth consumption between a data replication source and destination and storage consumption at the destination are reduced, when logical block mirroring is used with source deduplication, by eliminating repeated transmission of data blocks from source to destination. A reference is created for each data block at the source, the reference being unique within a storage aggregate of the source. During a mirror update, the source initially sends only the references of modified data blocks to the destination. The destination compares those references against a data structure to determine whether the destination already has any of those data blocks stored. If the destination determines that it already has a data block stored, it does not request or receive that data block again from the source. Only if the destination determines that it has not yet received the referenced data block does it request and receive that data block from the source.

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract: A method and apparatus for improved algorithm and key agility for a cryptosystem, comprising a CAM-type key manager. The key manager uses two memories, an index RAM and a key RAM, to virtualize each algorithm or key using pointers from the index RAM to the key RAM, allowing simple reference to algorithm/key pairs, and to dynamically allocate storage for keys. An autonomous free memory management design improves latency in future key write operations by transforming the search for free location addresses in the key RAM memory into a background task, and employing a free address stack. The index RAM is resizable so that data for a plurality of cryptographic algorithms may be stored dynamically.

Abstract: A packet transmission control apparatus includes a plurality of controllers, an arbitrator, a BUSY control circuit, and a memory. The controller controls a transmission of a packet to an interface and manages a request for data to a memory and a reception of data from the memory. The arbitrator selects a controller to be used from among the plurality of controllers. The BUSY control circuit recognizes a BUSY state of a control unit at destination of a packet. The memory stores data to be requested.

Abstract: A multi-channel multi-port memory is disclosed. In a particular embodiment, the multi-channel memory includes a plurality of channels responsive to a plurality of memory controllers. The multi-channel memory may also include a first multi-port multi-bank structure accessible to a first set of the plurality of channels and a second multi-port multi-bank structure accessible to a second set of the plurality of channels.

Abstract: Multi-ported memory systems (e.g., register files) employ self-timing for operational synchronization. Thus, rather than using a reference clock duty cycle for operational synchronization, as in conventional multi-ported register files, embodiments of the present disclosure employ self-timing for such operational synchronization. According to certain embodiments, self-timing is employed to synchronize all the internal events within the memory so that all the events are spaced in time for appropriate synchronization. For instance, the completion of one event leads to triggering another event, the completion of which leads to triggering another event, and so on. Thus, in one embodiment, the self-timing is achieved by referencing the operational events with the memory (or register file) to each other, rather than to a reference clock duty cycle.

Abstract: Described embodiments provide a multi-port memory system that has a plurality of memory banks and an equal number of mapping memory banks, each one of the data memory banks corresponding to one of the mapping memory banks. The multi-port memory reads, from one of the mapping memory banks selected by a read logical bank number, a read physical bank number identifying which one of the data memory banks data is to be read. The memory system also calculates, from at least one physical bank number read from the mapping memory banks other than the mapping memory bank selected by the read logical bank number, a write physical bank number indicating which one of the data memory banks is to be written. The calculation uses a hash of the physical bank numbers, such as by using an Exclusive-OR. This arrangement allows for simultaneous read/write access of the memory with fixed latency.

Abstract: A system and method for parallel scanning among multiple scanning entities. According to various embodiments of the present invention, buffers are allocated from a pool of memory pages, with one packet being located on each page. Each of the pages is mapped such that unprivileged scanners, privileged scanners, and hardware-based scanners are all capable of accessing the pages. By having the packets located on separate pages, additional data other than the packets at issue do not have to be shared, and copying is not necessary to complete the scanning process.

Abstract: A semiconductor memory device includes a first nonvolatile memory which has a first external interface and is capable of recording 1-bit data in one memory cell, a second nonvolatile memory which has a test terminal interface and is capable of recording a plurality of data in one memory cell, and a control unit which has a second external interface and is configured to control a physical state of an inside of the second nonvolatile memory.

Abstract: A method of and apparatus for arbitrating a memory access conflict to a memory array. The apparatus may include selection logic coupled with a plurality of ports and a memory array to arbitrate among a plurality of contending memory access requests and to conditionally block write data from accessing the memory array when write data arrives late in time.

Abstract: A system and method proxies data access commands across a cluster interconnect between storage appliances in a cluster. Each storage appliance activates two ports for data access, a local port for data access requests directed to clients of the storage appliance and a proxy port for data access requests directed to the partner storage appliance. Clients utilizing multi-pathing software may send data access requests to either the local port of the storage appliance or the proxy port of the storage appliance.

Abstract: Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.

Abstract: A system having a memory device accessible by a plurality of processors is provided. The system includes a memory device, a first processor, and a second processor. The memory device has a first memory array part and a second memory array part. The first processor predominantly accesses the first memory array part of the memory device and selectively accesses the second memory array part of the memory device. The second processor predominantly accesses the second memory array part of the memory device and selectively accesses the first memory array part of the memory device.

Abstract: A method, apparatus, computer chip, circuit board, computer and system are provided in which data is stored in a low-voltage, maskable memory. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing a data value in a memory cell in a storage device if a first access parameter associated with the memory cell matches a first pre-determined value and if a second access parameter associated with the memory cell matches a second pre-determined value. The method also includes maintaining a data value in the memory cell in the storage device if the first access parameter differs from the first pre-determined value. The apparatus includes a first and second pair of access parameter ports operatively coupled together and associated with a first and second access parameter respectively.

Abstract: Mechanisms are disclosed for detecting protocols independently of the ports used by streams associated with the protocols or applications that may send out such streams. The detecting may entail using a content filter that is hosted on a networking stack, where the content filter may be composed of a stream buffer and handlers for detecting the protocols. The handlers may be further used to modify streams incoming to a port or streams outgoing from an application. The handlers can modify the streams in a variety of ways, including reading, inserting, replacing, deleting, and completing data in the streams according to some policy criteria, such as those set by parental controls. Individual handlers may be selected from a plurality or set of handlers so that they can be matched up to the appropriate streams.

Abstract: Code, data, and/or other information types, may be isolated from one another and stored in distinct regions within the memory array of a nonvolatile memory. The distinct regions in memory may have corresponding read/write interfaces that are optimized for each information type.

Abstract: A multiprocessor system includes first and second processors and a multi-path accessible semiconductor memory device including a shared memory area and a pseudo operation execution unit. The shared memory area is accessible by the first and second processors according to a page open policy. The pseudo operation execution unit responds to a virtual active command from one of the first and second processors to close a last-opened page. The virtual active command is generated with a row address not corresponding to any row of the shared memory area. For example, bit-lines of a last accessed row are pre-charged for closing the last-opened page.

Abstract: Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data.

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Abstract: A computer enclosure includes a case comprising a drive bracket housing a number of compact disc drives and a storage device module mounted in the drive bracket in the absence of installed disk drives. The storage device module includes a supporting frame fixed in the drive bracket, a backboard, and a number of data storage devices arranged in the supporting frame. The backboard provides connection of the data storage devices to a motherboard of the case.

Abstract: A method for managing storage space in a storage port queue includes establishing a watermark for the storage port queue. The method further receives, at the storage port associated with the storage port queue, a command having an initiator-target-LUN (ITL) nexus associated therewith. Upon receiving the command, the method determines whether the used space in the storage port queue has reached the watermark. In the event the used space has not reached the watermark, the method processes the command. In the event the used space has reached the watermark and a specified number of commands for the ITL nexus are already present in the storage port queue, the method rejects the command. Otherwise, the method may process the command. A corresponding apparatus and computer program product are also disclosed herein.

Abstract: A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.

Abstract: A memory controller is provided for dealing with change in the form of use or operation state of a system. The memory controller includes bus interfaces, a memory controller core unit, and a memory interface. The memory controller core unit has a command controller. The bus interface units and command controller exchange commands via a bus.

Abstract: A multi-port memory, comprising: m (m?2) input/output ports independent of one another; n (n?2) memory banks independent of one another; and a route switching circuit capable of optionally setting signal routes of a command, an address, and input/output data between the m input/output ports and the n memory banks, wherein the route switching circuit allocates p (1?p?m) input/output ports optionally selected from the m input/output ports to a memory bank optionally selected from the n memory banks.

Abstract: Some embodiments of the invention pertain to a memory system containing multiple memory devices, in which one or multiple ones of the memory devices may flexibly be selected at one time for a common operation to be performed by all the selected devices concurrently.

Abstract: A method and system for sharing banks of memory in a multi-port memory device between components is provided. The multi-port memory device includes multiple ports to which components of a system are attached, and multiple banks of memory within the multi-port memory device that are shared by each of the ports. A bank availability pin is added to each port for each bank of memory. The bank availability pin is signaled when the bank is available to a particular port and unsignaled when the bank is unavailable. Thus, the multi-port memory device can be shared by several components simultaneously with only a small amount of additional hardware to support the sharing. Also provided are methods for refreshing the banks of memory.

Abstract: Write-through-read (WTR) comparator circuits and related WTR processes and memory systems are disclosed. The WTR comparator circuits can be configured to perform WTR functions for a multiple port file having one or more read and write ports. One or more WTR comparators in the WTR comparator circuit are configured to compare a read index into a file with a write index corresponding to a write-back stage selected write port among a plurality of write ports that can write data to the entry in the file. The WTR comparators then generate a WTR comparator output indicating whether the write index matches the read index to control a WTR function. In this manner, the WTR comparator circuit can employ less WTR comparators than the number of read and write port combinations. Providing less WTR comparators can reduce power consumption, cost, and area required on a semiconductor die for the WTR comparator circuit.

Abstract: A dual-port block random access memory (BRAM) can include first and second sections including direct mapped cache entries. The dual-port BRAM further can include third and fourth sections including translation look-aside buffer entries, wherein entries of the third section are associated with entries of the fourth section and wherein an entry of the third section and an associated entry of the fourth section collectively specify complete translation look-aside buffer data. The dual-port BRAM also can include first and second address ports concurrently accessing at least one of the first, second, third, or fourth sections of the dual-port BRAM to locate a virtual address to be translated.

Abstract: A memory device and a method of controlling the memory device are provided, comprising: generating commands at a memory controller; counting a number of commands in response to a clock signal; storing the commands and the count numbers corresponding to the commands; transmitting to a memory device the commands, the count number of the commands, and data; receiving at the memory device the commands, the count number of the commands, and data sent from the memory controller; counting at the memory device the number of commands received in response to the clock signal; storing at the memory device the count number of commands received; and transmitting the count number of the commands received to the memory controller, wherein said transmitting the count number of the command to the memory controller is performed upon indication of an error condition.

Abstract: A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.

Abstract: A multiprocessor system includes a first processor coupled to a first bus, a second processor coupled to a second bus, a first memory coupled to the first bus and the second bus, and a second memory coupled to the second bus. The first processor is configured to access the first memory through the first bus, and the second processor is configured to access the first memory and the second memory through the second bus.

Abstract: A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.

Abstract: A non-volatile memory storage system including a transmission interface, a memory module, and a controller is provided. The memory module includes first and second non-volatile memory chips. The first and the second non-volatile memory chips can be simultaneously enabled by receiving a chip enable signal from the controller via a chip enable pin. When the controller performs a multichannel access, the controller provides an access instruction to the first and second non-volatile memory chip, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal. When the controller performs a single channel access, the controller provides the access signal to one of the first and second non-volatile memory chips, and provides a non-access instruction to the other one, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal.

Abstract: A method for implementing data storage and a dual port, dual element storage device are provided. A storage device includes a predefined form factor including a first port and a second port, and a first storage element and a second storage element. A controller coupled between the first port and second port, and the first storage element and second storage element controls access and provides two separate data paths to the first storage element and second storage element.

Abstract: An embodiment of the present invention is directed to a method of deterministic collision detection involving at least two ports. The method includes receiving a read/write operation at a first data rate at a first port of a multi-port device, receiving a read/write operation at a second data rate at a second port of the multi-port device, detecting a collision between the first port and the second port if a same address space is accessed by the first port and the second port coincidentally, asserting a busy signal at least one of said first port and said second port a number of clock cycles after detecting said collision, storing an address location of said address space in a memory register, and deterministically report the collision using the address location and the number of clock cycles.

Abstract: A memory module having a plurality of memory devices and a memory buffer that translates between a variable width primary data port and a plurality of fixed width secondary data ports, each of which is coupled to one of the memory devices. The translation is effected by distributing the width of the primary data port to all or to a subset of the secondary data ports. In another aspect, the invention comprises a memory buffer that supports adjustable data width in a variety of ways.

Abstract: A memory controller performs a mirror copy function in a way that allows processor accesses to memory to continue during the mirror copy operations that make up the mirror copy function. Data integrity of mirror copy operations is assured by protocols set up in the memory controller. The result is a memory controller that performs a mirror copy function in a way that allows normal processor accesses to memory to be interleaved with mirror copy operations, thereby minimizing the impact on system performance of executing the mirror copy function.

Abstract: A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus.

Abstract: A system may include a content addressable memory (CAM) that is configured to include multiple services, receive a key, where the key includes source port information and IP information related to a packet received on one of multiple ports, and output a match index value in response to a search of the CAM using the key. The system may include a policy memory module that is configured to receive the match index value and to output meter controls and a meter address based on the match index value, a port meter map module that is configured to receive the source port information and to output a mask value and a per port meter value, and a remapping module that is configured to receive the meter address, receive the mask value and the per port meter value, and modify the meter address based on those values.

Abstract: A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.