Multiport Memory Patents (Class 711/149)
-
Patent number: 7941614Abstract: A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.Type: GrantFiled: May 7, 2009Date of Patent: May 10, 2011Assignee: QST, Holdings, IncInventors: Frederick Curtis Furtek, Paul L. Master
-
Patent number: 7937539Abstract: A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.Type: GrantFiled: May 7, 2009Date of Patent: May 3, 2011Assignee: QST Holdings, LLCInventors: Frederick Curtis Furtek, Paul L. Master
-
Patent number: 7937538Abstract: A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.Type: GrantFiled: May 7, 2009Date of Patent: May 3, 2011Assignee: QST Holdings, LLCInventors: Frederick Curtis Furtek, Paul L. Master
-
Patent number: 7934057Abstract: Embodiments of the invention are directed to systems and method for providing predictable timing for read operations in a multiport memory device. Accordingly, an embodiment is directed to a multiport memory system, comprising a single port memory core synchronized to a first clock, multiple access ports synchronized to at least a second clock, and a multiplexer logic coupled to the core memory and the plurality of access ports. The multiplexer logic arbitrates access to the memory core between multiple access ports. Each access ports includes an uncertainty detect logic that measures data path latency, and an uncertainty adjust logic that operates to selectively add data path delay to increase the measured path latency to a predictable value.Type: GrantFiled: December 24, 2003Date of Patent: April 26, 2011Assignee: Cypress Semiconductor CorporationInventor: S. Babar Raza
-
Publication number: 20110093767Abstract: A system for serially transmitting vital data includes first and second processors to determine first and second data, a serial communication apparatus to input third data and output serial data based upon the third data, and a memory having first and second ports accessible by the first and second processors, a first memory writable by the first processor and readable by the second processor, and a second memory writable by the second processor and readable by the first processor. The first and second processors store the first and second data in the first and second memories, cooperatively agree that the first data corresponds to the second data, and responsively cause the apparatus to employ: one of the first and second data as the third data, or parts of the first and second data as the third data, and output the serial data based upon the third data.Type: ApplicationFiled: October 15, 2009Publication date: April 21, 2011Inventors: WILLIAM A. SHARP, JOHN E. LEMONOVICH, JAMES C. WERNER, ZHU DING, LAWRENCE A. WEBER
-
Publication number: 20110087847Abstract: Systems and methods for improved multiple-port memory are provided. In one embodiment, a processing system comprises: at least one processing core; a peripheral bus; and a memory for storing digital data, the memory divided into a first and a second partition of memory segments. The memory includes a first port coupled to the peripheral bus providing read access and write access only to the first partition, wherein the first partition stores peripheral data associated with one or more peripheral components coupled to the peripheral bus; a second port coupled to the at least one processor providing read-only access to only the second partition, wherein the second partition stores executable code for the at least one processing core; and a third port coupled to the at least one processor providing read access and write access to the entire first partition and the second partition.Type: ApplicationFiled: October 8, 2009Publication date: April 14, 2011Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Scott Gray, Nicholas Wilt
-
Patent number: 7917941Abstract: A system and method for providing security for an Internet server. The system comprises: a logical security system for processing login and password data received from a client device during a server session in order to authenticate a user; and a physical security system for processing Internet protocol (IP) address information of the client device in order to authenticate the client device for the duration of the server session.Type: GrantFiled: September 22, 2003Date of Patent: March 29, 2011Assignee: International Business Machines CorporationInventor: Bruce Wallman
-
Patent number: 7917687Abstract: There is provided a flash memory apparatus for storing data aggregate having a plurality of types of data in and reproduce the data aggregate from a flash memory via a plurality of ports. The flash memory apparatus includes a plurality of access request units configure to request to write data in one block of the flash memory by aligning a writing position of one block data with a page unit on a data type basis of the flash memory when the data classified by type that are inputted via the ports corresponding to the access request units on the one-to-one basis are stored to reach an amount relative to one block of the flash memory, and an access controller configured to write the data in the flash memory during time division allocated per port based on the requests incited by the respective access request units.Type: GrantFiled: April 4, 2007Date of Patent: March 29, 2011Assignee: Sony CorporationInventors: Kaoru Urata, Masakazu Yoshimoto
-
Patent number: 7913022Abstract: Port Interface Modules (PIMs) are provided for ports of a Multi-Port Memory Controller. The PIMs include logic that is programmable to be compatible with different types of devices, processors or buses that can be connected to the ports. The PIMs can further include protocol bridges to enable one port PIM to connect to a device or another port PIM in a master/slave fashion.Type: GrantFiled: February 14, 2007Date of Patent: March 22, 2011Assignee: Xilinx, Inc.Inventor: Glenn A. Baxter
-
Patent number: 7908440Abstract: A personal sensing device that may be used for storing personal data and sensed data arbitrates and prioritizes competing requests for memory access from sensing, wireless, and wired interfaces. The personal sensing device enables power efficiency with burst-writes to the memory at higher data rates then an incoming sensor data stream without risk of data loss. Sensing operations coordinated by reconfigurable control logic are partitioned from storage operations coordinated by a multi-port memory controller. The interface between the functional partitioning uses message passing, status/control registers and buffering to reduce or eliminate system interdependencies.Type: GrantFiled: August 9, 2007Date of Patent: March 15, 2011Assignee: Intel CorporationInventors: Benjamin Kuris, Donald R. Denning, Jr., Steven M. Ayer
-
Patent number: 7903684Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.Type: GrantFiled: July 25, 2007Date of Patent: March 8, 2011Assignee: Silicon Image, Inc.Inventors: Dongyun Lee, Yeshik Shin, David D. Lee, Deog-Kyoon Jeong, Shing Kong
-
Patent number: 7904667Abstract: A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device. Each bit of the ODR can manipulate the state of a connected external binary device or can be read without changing the state. The memory device may include settable controlling bits and a set of controlled register bits. Setting the one or more controlling bits may define which controlled register bits are associated with the IRR and which are associated with the ODR.Type: GrantFiled: August 10, 2006Date of Patent: March 8, 2011Assignee: Integrated Device Technology, Inc.Inventors: Yunsheng Wang, Casey Springer, Tak Kwong Wong, Bill Beane
-
Patent number: 7904681Abstract: Methods and systems are disclosed that enable data migration from a source logical volume to a target logical volume in signal communication with the source logical volume with minimal disruption to the accessibility of that data. The coherency of data on the source logical volume and the target logical volume is confirmed. A first pseudoname is unmapped from a source logical volume identifier, and a second pseudoname is unmapped from a target logical volume identifier. A logical volume identifier includes information specific to the logical volume it identifies. The first pseudoname is then mapped to the target logical volume identifier.Type: GrantFiled: June 30, 2006Date of Patent: March 8, 2011Assignee: EMC CorporationInventors: Michael E. Bappe, Helen S. Raizen
-
Publication number: 20110055492Abstract: Sorting data using a multi-core processing system is disclosed. An unsorted data set is copied from a global memory device to a shared memory device. The global memory device can store data sets for the multi-core processing system. The shared memory device can store unsorted data sets for sorting. The unsorted data set can include a plurality of data elements. The unsorted data set can be sorted into sorted data in parallel on the shared memory device using a cluster of processors of the multi-core processing system. The cluster of processors may include at least as many processors as a number of the data elements in the unsorted data set. The sorted data can be copied from the shared memory device to the global memory device.Type: ApplicationFiled: September 3, 2009Publication date: March 3, 2011Inventors: Ren Wu, Bin Zhang, Meichun Hsu
-
Publication number: 20110055491Abstract: A switching frame buffer is described in which data units within a sequence of time slots, of a frame, may be simultaneously input and output at ports of the switching frame buffer. In one implementation, a write port may receive data units within a single cycle of the switch. A number of memories may be provided, where first selected ones of the memories constitute memory groups and second selected ones of the memories constitute a memory subsets, each of the memory groups including a corresponding one of the memory subsets. The write port may supply each of a number of copies of the data units to a corresponding one of the memory subsets. Multiplexers may be associated with the groups of the memories and a read port may receive one of the copies of a number of the data units from different ones of the multiplexers.Type: ApplicationFiled: August 31, 2009Publication date: March 3, 2011Inventors: Chung Kuang Chin, Shankar Venkataraman, Swaroop Raghunatha
-
Patent number: 7900073Abstract: An apparatus for providing management storage via a USB port of a computer system is disclosed. The apparatus includes a flash memory, a first and second switches, a first and second inverters, a designated port, and a controller. Coupled to the flash memory, the first and second switches are controlled by a main power of a computer system in a complementary manner. The first and second inverters, which are powered by a standby power of the computer system, are coupled to a respective control input of the first and second switches. The designated port, which is coupled to the flash memory via the first switch, allows data to be read from and written to the flash memory without booting up the computer system. On the other hand, the controller, which is coupled to the flash memory via the second switch, allows data to be read from and written to the flash memory by the computer system only after the computer system has been booted up.Type: GrantFiled: March 28, 2008Date of Patent: March 1, 2011Assignee: Lenovo (Singapore) Pte. Ltd.Inventors: Joseph R. Parker, Paul Plaskonos
-
Patent number: 7890690Abstract: A method for emulating a dual-port I2C device includes monitoring a bus for I2C traffic. A system receives an I2C interrupt on the bus. The system determines whether the received I2C interrupt is one of either a hardware interrupt or a software interrupt. In the event the received I2C interrupt is a hardware interrupt, the system responds to the hardware interrupt, and accesses a flash memory for read/write operation based on the hardware interrupt. In the event the received I2C interrupt is a software interrupt, the system responds to the software interrupt, and accesses a flash memory for read/write operation based on the software interrupt.Type: GrantFiled: June 7, 2007Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Kaveh Naderi, Patrick Allen Buckland, Jason Eric Moore, Abel Enrique Zuzuarregui
-
Publication number: 20110035575Abstract: A multiprocessor system comprises first and second processors connected to a multi-port semiconductor memory device. The multi-port semiconductor memory device comprises a shared memory area and a plurality of mailbox areas used for inter-processor communication. The first and second processors use a single nonvolatile memory device for storing boot data and transmit information for booting via the shared memory area.Type: ApplicationFiled: May 17, 2010Publication date: February 10, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Jin-Hyoung KWON
-
Publication number: 20110035537Abstract: A multiprocessor system comprises a multi-port semiconductor memory device, a first processor, and a memory link architecture. The multi-port semiconductor memory device comprises a mailbox area and a shared memory area accessible through a plurality of ports. The first processor is configured to write a multi-command set comprising multiple commands for multiple read/write operations to a command area of the shared memory, and to write a message to the mailbox area to indicate the writing of the multi-command set. The memory link architecture comprises a second processor connected to the multi-port semiconductor memory device, and a nonvolatile semiconductor memory device connected to the second processor. The second processor is configured to read the multi-command set from the mailbox area and to sequentially perform the multiple read/write operations according to the multi-command set.Type: ApplicationFiled: May 7, 2010Publication date: February 10, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Jin-Hyoung KWON
-
Patent number: 7886099Abstract: In some embodiments, a system comprises a system memory module and an access card. The system memory module connects to a memory bus on a motherboard for a personal computer, while the access card connects to an expansion bus. The access card couples to the system memory module to provide power when the personal computer is unpowered. When the personal computer boots, the system memory module operates in a cloaked mode that hides the system memory module from a memory bus. The access card switches the system memory module from the cloaked mode to a normal mode in response to a command received via the expansion bus. For long-term power outages, the access card may copy data from the system memory module to a nonvolatile information storage device. Energy storage and nonvolatile information storage may be provided by a separate longevity unit that couples to the access card.Type: GrantFiled: June 16, 2006Date of Patent: February 8, 2011Assignee: Superspeed LLCInventor: Vincent P. Bono
-
Patent number: 7882344Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.Type: GrantFiled: October 26, 2006Date of Patent: February 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Jae Byun, Young Min Lee, Yun-Tae Lee, Gyoo-Cheol Hwang
-
Patent number: 7873763Abstract: A system for managing a circular buffer memory includes a number of data writers, a number of data readers, a circular buffer memory; and logic configured to form a number of counters, form a number of temporary variables from the counters, and allow the data writers and the data readers to simultaneously access locations in the circular buffer memory determined by the temporary variables.Type: GrantFiled: March 26, 2010Date of Patent: January 18, 2011Assignee: Juniper Networks, Inc.Inventors: Juqiang Liu, Hua Ji, Haisang Wu
-
Patent number: 7873757Abstract: A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.Type: GrantFiled: February 16, 2007Date of Patent: January 18, 2011Assignee: ARM LimitedInventors: Paul Kimelman, Edmond John Simon Ashfield, Steven Richard Mellor, Ian Field
-
Patent number: 7870326Abstract: A multiprocessor system and method thereof are provided.Type: GrantFiled: June 28, 2007Date of Patent: January 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Hee Shin, Han-Gu Sohn, Young-Min Lee, Ho-Cheol Lee, Soo-Young Kim, Dong-Hyuk Lee, Chang-Ho Lee
-
Patent number: 7870334Abstract: A storage system, consisting of one or more data storage logical units (LUs) formed in physical media. The LUs are adapted to receive command and respond to the commands to store and recall data. The storage system further includes a plurality of ports, each port being adapted to maintain a respective LU command queue for each of the LUs, such that upon receiving a command directed to one of the LUs, the port places the received command in the respective LU command queue. The port converts the received command to one or more converted commands at least some of which are directed to the physical media of the one of the LUs. The port then conveys the commands directed to the physical media in an order determined by the respective LU command queue.Type: GrantFiled: November 12, 2003Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: Ofir Zohar, Yaron Revah, Haim Helman, Dror Cohen, Shemer Schwartz
-
Publication number: 20110004734Abstract: Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has multiple sub-cycle periods within a user period of the user design clock cycle. The method identifies multiple port accesses to a first multi-port memory defined in the user design. The accesses are in a single user design clock cycle. The method maps the multiple port accesses to the first multi-port memory to multiple physical-port memory accesses to a second physical-port memory in the configurable IC during multiple sub-cycles associated with a single user design clock cycle.Type: ApplicationFiled: September 13, 2010Publication date: January 6, 2011Inventors: Herman Schmit, Steven Teig, Brad Hutchings
-
Patent number: 7861039Abstract: Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or more local memory arrays into a single, larger functional unit. One exemplary embodiment of the present invention provides a FIFO made up of a number of FIFO sub-blocks connected in series. Each FIFO sub-block includes local read and write address counters such that read and write addresses are not bused between the FIFO sub-blocks.Type: GrantFiled: June 30, 2008Date of Patent: December 28, 2010Assignee: Altera CorporationInventor: Peter Bain
-
Publication number: 20100325370Abstract: A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate.Type: ApplicationFiled: August 24, 2010Publication date: December 23, 2010Applicant: FULCRUM MICROSYSTEMS INC.Inventors: Uri Cummings, Andrew Lines, Patrick Pelletier, Robert Southworth
-
Patent number: 7856541Abstract: A system is composed of multiple storage control modules, which are connected to each other via interconnects. The aforesaid interconnects connecting the storage control modules may cause certain extra latency. Each storage control module may have data preservation module, which can preserve data stored by host computers. The system incorporates a latency table and provides a volume according to the latency table in accordance with a request from a host computer or an administrator. The latency table is dynamically created or statically stored in the inventive system.Type: GrantFiled: April 18, 2007Date of Patent: December 21, 2010Assignee: Hitachi, Ltd.Inventors: Yasunori Kaneda, Hiroshi Arakawa
-
Publication number: 20100318725Abstract: Exemplary embodiments relate to a multi-processor system including: a first processor for writing a power-off check command to a first mail box, reading a power-off wait message or a power-off allowance message written to a second mail box, and waiting or turning off the multi-processor system, in a power-off operation mode; a second processor for indicating whether data is completely stored during a current processing operation in response to the power-off check command in the first mail box and writing the power-off wait message or the power-off allowance message to the second mail box according to the indication result; and a multi-port semiconductor memory device having an internal register that includes the first and second mail boxes and dedicated and shared memory areas for data processing. The first and second mail boxes serve as latch storage units, and the dedicated and shared memory areas are accessed by the first and second processors.Type: ApplicationFiled: January 19, 2010Publication date: December 16, 2010Inventor: Jin-Hyoung Kwon
-
Publication number: 20100318749Abstract: According to one general aspect, a method may include, in one embodiment, grouping a plurality of at least single-ported memory banks together to substantially act as a single at least dual-ported aggregated memory element. In various embodiments, the method may also include controlling read access to the memory banks such that a read operation may occur from any memory bank in which data is stored. In some embodiments, the method may include controlling write access to the memory banks such that a write operation may occur to any memory bank which is not being accessed by a read operation.Type: ApplicationFiled: October 22, 2009Publication date: December 16, 2010Applicant: Broadcom CorporationInventor: Brad Matthews
-
Publication number: 20100295969Abstract: A multimedia information appliance includes a camera unit, an image display unit, and a multi-port memory. The camera unit includes an image sensor, an image signal processor, an application processor, and a multi-port memory. The image sensor is configured to receive an optical signal of a photographed image from a lens, and to convert the optical signal into an electrical signal. The image signal processor is configured to convert the electrical signal into an image signal, and to control the image sensor. The application processor is configured to process the image signal. The multi-port memory includes a plurality of data input/output ports and stores signals received from the image signal processor and the application process through different data input/output ports.Type: ApplicationFiled: April 29, 2010Publication date: November 25, 2010Inventor: Hyunduk Cho
-
Patent number: 7840762Abstract: A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.Type: GrantFiled: August 23, 2007Date of Patent: November 23, 2010Assignee: Samsung Electronics Co., LtdInventors: Chi-Sung Oh, Yong-Jun Kim, Kyung-Woo Nam, Jin-Kuk Kim, Soo-Young Kim
-
Patent number: 7835021Abstract: Systems, methods, and media for managing the print speed of a variable speed printer are disclosed. Embodiments include a print controller system having a raster image processor for rasterizing a print job to create a plurality of rasterized pages and a printer controller buffer for storing one or more of the rasterized pages. The printer controller buffer may also transmit at a print engine feed rate the one or more rasterized pages to a print engine. Embodiments may also include a speed control module in communication with the printer controller buffer for determining the print engine feed rate. Further embodiments may include the speed control module determining the print engine feed rate based on one or more of page processing times, page arrival rates, estimated print completion rates, and the number of pages in a print engine buffer.Type: GrantFiled: May 23, 2005Date of Patent: November 16, 2010Assignee: Infoprint Solutions Company, LLCInventor: John Thomas Varga
-
Publication number: 20100281227Abstract: Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of which are non-native to each port. The memory device may include a configuration register that stores configuration data indicative of the mapping of the memory banks to the ports. In response to the configuration data, for example, a steering logic may couple each of the ports either to one or all of the native memory banks or to one or all of the non-native memory banks.Type: ApplicationFiled: April 29, 2009Publication date: November 4, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Robert Walker, Dan Skinner
-
Patent number: 7814280Abstract: A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is operable to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of the data segments in the shared memory.Type: GrantFiled: August 18, 2005Date of Patent: October 12, 2010Assignee: Fulcrum Microsystems Inc.Inventors: Uri Cummings, Andrew Lines, Patrick Pelletier, Robert Southworth
-
Patent number: 7809875Abstract: A system and method for writing, by a sender, a message into blocks of a memory space, the memory space being shared by the sender of the message and a receiver of the message, and sending, by the sender, an interrupt corresponding to the message.Type: GrantFiled: June 30, 2008Date of Patent: October 5, 2010Assignee: Wind River Systems, Inc.Inventors: Anand Sundaram, Johan Fornaeus
-
Publication number: 20100250865Abstract: Multi-ported memory systems (e.g., register files) employ self-timing for operational synchronization. Thus, rather than using a reference clock duty cycle for operational synchronization, as in conventional multi-ported register files, embodiments of the present disclosure employ self-timing for such operational synchronization. According to certain embodiments, self-timing is employed to synchronize all the internal events within the memory so that all the events are spaced in time for appropriate synchronization. For instance, the completion of one event leads to triggering another event, the completion of which leads to triggering another event, and so on. Thus, in one embodiment, the self-timing is achieved by referencing the operational events with the memory (or register file) to each other, rather than to a reference clock duty cycle.Type: ApplicationFiled: March 25, 2009Publication date: September 30, 2010Applicant: QUALCOMM IncorporatedInventors: Hari Rao, Chang Ho Jung, Nan Chen, Sei Seung Yoon
-
Publication number: 20100235590Abstract: A memory system including a plurality of ports and a memory core having a plurality of memory banks. Access requests received at the ports are broadcast to the memory banks. Multiple memory banks may be concurrently accessed in response to access requests received on different ports. A memory controller provides the access requests to the memory system, and ensures that a single memory bank is not concurrently accessed by different ports. All access requests are processed with the same latency. If the memory banks include memory cells that must be periodically refreshed, then the memory controller also provides refresh requests to the memory banks. Because multiple memory banks may be concurrently accessed in response to access requests provided on different ports, the memory banks can operate at a lower frequency than the ports.Type: ApplicationFiled: March 16, 2009Publication date: September 16, 2010Applicant: MoSys, Inc.Inventor: Kit Sang Tam
-
Patent number: 7797393Abstract: A shared storage network system comprises at least one storage client and a plurality of storage servers, each providing a storage portion of the shared storage network system, each storage portion being divided into a plurality of sectors, each sector being divided into a plurality of blocks, a virtual block identifier being associated to each of the blocks such that the entirety of all of the virtual block identifiers of the blocks form a global block address space in which each of the virtual block identifiers is unique. The plurality of storage servers and the at least one storage client are grouped into a plurality of local area networks interconnected with preferred optical channels to form a global network. The at least one storage client is adapted to have read and/or write access to at least one block of at least one of the storage portions associated to one of the local area networks which differs from the local area network of the storage client.Type: GrantFiled: January 8, 2004Date of Patent: September 14, 2010Assignee: Agency for Science, Technology and ResearchInventors: Qiang Qiu, Jit Biswas
-
Patent number: 7797497Abstract: Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has multiple sub-cycle periods within a user period of the user design clock cycle. The method identifies multiple port accesses to a first multi-port memory defined in the user design. The accesses are in a single user design clock cycle. The method maps the multiple port accesses to the first multi-port memory to multiple physical-port memory accesses to a second physical-port memory in the configurable IC during multiple sub-cycles associated with a single user design clock cycle.Type: GrantFiled: March 8, 2006Date of Patent: September 14, 2010Assignee: Tabula, Inc.Inventors: Herman Schmit, Steven Teig, Brad Hutchings
-
Publication number: 20100228908Abstract: An integrated circuit device may include a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single port of the first IC portion.Type: ApplicationFiled: March 9, 2010Publication date: September 9, 2010Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventor: Dinesh Maheshwari
-
Publication number: 20100228926Abstract: An integrated circuit device may include a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single port of the first IC portion.Type: ApplicationFiled: March 9, 2010Publication date: September 9, 2010Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventor: Dinesh Maheshwari
-
Publication number: 20100211748Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.Type: ApplicationFiled: April 11, 2008Publication date: August 19, 2010Applicant: RAMBUS INC.Inventors: Richard E. Perego, Frederick A. Ware
-
Publication number: 20100205383Abstract: The present invention describes improving the scheduling of read commands on a mirrored memory computer system by utilizing information about pending memory access requests. A conflict queue is configured to track a read/write queue associated with each of a plurality of memory ports on the mirrored memory system. The conflict queue determines a predicted latency on each memory port based on the contents of each of the read/write queues. A compare logic unit is coupled to the conflict queue, wherein the compare logic unit compares a predicted latency of a primary memory and a mirrored memory and schedules read commands to the memory port with the lowest predicted latency.Type: ApplicationFiled: February 12, 2009Publication date: August 12, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Herman L. Blackmon, Joseph A. Kirscht, Elizabeth A. McGlone, Jeb A. Shookman
-
Publication number: 20100199057Abstract: Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.Type: ApplicationFiled: April 9, 2010Publication date: August 5, 2010Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventors: HONG BEOM PYEON, HAKJUNE OH, JIN-KI KIM
-
Patent number: 7770170Abstract: A blocking local sense synchronization barrier is provided. The local sense variable is not processor private or global, but truly local to the synchronization barrier function. Safe deletion is provided by making sure the last operation a thread performs on a barrier is a write. Just before returning, threads increment a field that indicates the count of threads that have left the barrier. Blocking is supported such that threads spin for some interval, and when they decide to block, examine and set (if not already set) the indication of whether a thread is blocking that is to be examined by the last thread to arrive at the barrier to determine whether to set an event to release blocking threads.Type: GrantFiled: July 12, 2005Date of Patent: August 3, 2010Assignee: Microsoft CorporationInventors: John Rector, Jonathan D. Morrison, Neill M. Clift, Arun U. Kishan
-
Publication number: 20100191903Abstract: A switch 100 includes a plurality of ports 101 for exchanging data. A shared memory 102 enables the exchange of data between first and second ones of the ports 101 and includes an array 202 of memory cells arranged as a plurality of rows and a single column having width equal to a predetermined word-width and circuitry 202, 204, 206, 208 for writing selected data presented at the first one of the ports 101 to a selected row in the array as a word of the predetermined word-width during a first time period and for reading the selected data from the selected row as a word of the predetermined wordwidth during a second time period for output at a second one of the ports 101.Type: ApplicationFiled: March 31, 2010Publication date: July 29, 2010Applicant: S. Aqua Semiconductor, LLCInventor: G. R. Mohan Rao
-
Publication number: 20100185811Abstract: A data processing system including a non-volatile memory and a processor controlling an operation of the non-volatile memory is provided. The processor transmits and receives a first type of data to and from an outside through a first path through which a first command and a first address, which are used to write/read the first data to/from the non-volatile memory, are transmitted. The processor also transmits and receives a second type of data to and from the outside through a second path different from the first path through which a second command and a second address, which are used to write/read the second data to/from the non-volatile memory, are transmitted.Type: ApplicationFiled: January 6, 2010Publication date: July 22, 2010Inventor: Jin Hyoung Kwon
-
Patent number: 7761668Abstract: A data processing system includes a multiport memory module including a plurality of first ports and a plurality of second ports. The data processing system includes a plurality of first buses and a plurality of second buses. A plurality of hardware acceleration modules configured to communicate with respective ones of the plurality of first ports via respective ones of the plurality of first buses. The data processing system includes a processor module. A random access memory (RAM) module configured to store data. The processor module and the RAM module communicate with the multiport memory module via respective ones of the plurality of second buses. A shared bus includes a first bus portion configured to communicate with the plurality of hardware acceleration modules at a first rate. A second bus portion configured to communicate with the processor module and the RAM module at a second rate that is different than the first rate.Type: GrantFiled: October 6, 2009Date of Patent: July 20, 2010Assignee: Marvell World Trade Ltd.Inventor: Sehat Sutardja