Abstract: A method and device for converting between different time domains at a local unit utilizing an processor is disclosed. Time counters to count time in at least two different formats are located locally at each unit. Once a time conversion is initiated, a time stamp is received by the processor and the time counter in the new time domain commences calculating an adjustment count. Once the converted time is received from the processor, the received time plus the adjustment count are summed to provide a time base for the new time domain. The time counters continue counting in their respective time domains after conversion.

Abstract: A method for accessing a memory includes receiving a first address wherein the first address corresponds to a demand fetch, receiving a second address wherein the second address corresponds to a speculative prefetch, providing first data from the memory in response to the demand fetch in which the first data is accessed asynchronous to a system clock, and providing second data from the memory in response to the speculative prefetch in which the second data is accessed synchronous to the system clock. The memory may include a plurality of pipeline stages in which providing the first data in response to the demand fetch is performed such that each pipeline stage is self-timed independent of the system clock and providing the second data in response to the speculative prefetch is performed such that each pipeline stage is timed based on the system clock to be synchronous with the system clock.

Abstract: One inventive aspect relates to a digital sub-circuit suitable for embedding in an at least partially digital circuit for minimizing the influence of another digital sub-circuit on the at least partially digital circuit, the other digital sub-circuit being part of the at least partially digital circuit. The influence of the other digital sub-circuit may, for example, be the introduction of ground bounce by switching of the other digital sub-circuit. Another inventive aspect relates to an at least partially digital circuit comprising such a digital sub-circuit for minimizing the influence of another digital sub-circuit to the at least partially digital circuit and to a method for reducing the influence of another digital sub-circuit to an at least partially digital circuit.

Abstract: Application settings are roamed across multiple computing devices. Provider modules on the computing devices are run to retrieve application settings to be roamed and to roam those application settings across the multiple computing devices. Application setting changes initiated on a particular computing device are added to a history of application setting changes on the particular computing device, and also added to synchronization communication module for communication to one or more additional computing devices of the multiple computing devices. Application setting changes initiated by one of the one or more additional computing devices are received by the particular computing device and added to a history of application setting changes on the particular computing device, and are also incorporated into the application settings on the particular computing device.

Abstract: The subject systems and/or methods relate to a high speed memory device that enables a preamble pattern to be updated after manufacture. A high speed memory device can include a FLASH module and a RAM module. The FLASH module can include an initial preamble pattern, wherein the initial preamble pattern is loaded during a power-up of the high speed memory. The RAM module can include a default preamble pattern, wherein the default preamble pattern is loaded after the power-up of the high speed memory. The initial preamble pattern or the default preamble pattern can be defined by a manufacture of the high speed memory or an OEM of the high speed memory. Additionally, the initial preamble pattern or the default preamble pattern can be updated with a customized preamble pattern based upon a target environment.

Abstract: In a data bus with asynchronous data transmission via a clock and a data line, the transmitted data are ascertained by sampling with a multiple of the data rate of the data bus. Sampling is done in this case with a clock which is not synchronous with the asynchronous clock of the data bus. For avoiding interferences which develop due to the unnecessary operation of the interface circuit with a high frequency clock when no data are currently transmitted, a control circuit is provided for detecting the beginning and the end of a data transmission. Only at the beginning of a data transmission, the interface circuit will be supplied with the required clock. After the end of the data transmission, the clock for the interface circuit will be switched off again. The control circuit is preferably designed as a state machine which reacts, without the need for clock signals, to the states on the data and clock line of the data bus.

Abstract: A method and apparatus for varying an output clock signal frequency to match the frequency of an output data signal frequency for a SERDES circuit while maintaining a constant input clock frequency is shown. According to this method and apparatus, a PMA rate signal may control the frequency of the output clock while a datastrobe signal may be used to control the frequency of the data signal. Accordingly, the apparatus and methods may be used to produce an output data signal and a clock signal having frequencies that may be lower than the frequency of the input clock signal.

Abstract: An arrangement for controlling a system generated noise level such that the same is adapted to an actual ambient noise level of the system environment. Internal noise generators will thus not run at a needlessly lowered rate than actually needed. For instance, by permitting a fan to run at a generally higher speed, the system will not needlessly undergo significant internal temperature increases. By the same token, CPU performance, to the extent that it represents a noise generator, will not be needlessly throttled.

Abstract: A data transfer control device includes an OUT-transfer transmitter circuit which transmits OUT data by driving a serial signal line, a clock-transfer transmitter circuit which transmits a clock signal CLK by driving a serial signal line, a PLL circuit which generates the clock signal CLK, and a power-down setting circuit which sets a power-down mode. In a first power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode, and the clock-transfer transmitter circuit is set to the power-down mode to stop a system clock signal of a target-side data transfer control device. In a second power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode without setting the clock-transfer transmitter circuit to the power-down mode.

Abstract: Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.

Abstract: A frequency adapter for synchronizing data transfers between a low-frequency module and a high-frequency module connected to an internal bus. The frequency adapter includes a low-to-high synchronization unit for synchronizing data transfers from the low frequency module to the high-frequency module, wherein the low-to-high synchronization unit is clocked by a low frequency clock; and a high-to-low synchronization unit for synchronizing data transfers from the high frequency module to the low-frequency module, wherein the high-to-low synchronization module is clocked by a low frequency clock.

Abstract: A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.

Abstract: A processing system includes a bus and a processor whose core is constrained to have one or more core clock signal frequencies no lower than a predetermined multiple of the lowest of one or more bus clock signal frequencies. In a power-save mode, the processor is able to generate one or more core clock signals at frequencies such that the lowest core clock signal frequency is lower than the predetermined multiple of the lowest of the one or more bus clock signal frequencies in performance mode. The processor is able to achieve this by generating the one or more bus clock signals so that the lowest of the bus clock signal frequencies in power-save mode is lower than the lowest of the bus clock signal frequencies in performance mode.

Abstract: A system and method are disclosed for masking a clock input from a clock line when the clock line is not being driven by a clock source. The clock mask is triggered by a clock cycle from the clock source. In one version, a memory controller configures a masking circuit to either allow a clock signal to the clock input or to mask the clock input from a bidirectional clock bus. The masking circuit may comprise a storage element and a gate, as an example.

Abstract: A decoding circuit for decoding a command is provided. The received command is transmitted during at least two clock periods of a clock signal, and the received command is divided to a former encoded data and a latter encoded data. The decoding circuit includes a pre-trigger signal generating unit, a comparing unit, and a starting signal generating unit. The pre-trigger signal generating unit receives the former encoded data and generates a pre-trigger signal when the former encoded data of the received command matches the corresponding former encoded data of a predetermined command. The comparing unit generates a match signal when the latter encoded data of the received command is the same with the latter encoded data of the predetermined command. The starting signal generating unit outputs a starting signal according to the pre-trigger signal and the match signal. The starting signal starts a corresponding operation of the predetermined command.

Abstract: An embodiment of a processing device includes a function unit and a control unit. The function unit receives input data and performs a specific operation to the input data to generate result data. The control unit receives the result data and generates an output signal. The control unit latches the result data according to a first clock signal to generate first data and latches the result data according to a second clock signal to generate second data. The control unit compares the first data with the second data to generate a control signal and selects the first data or the second data to serve as data of the output signal according to the control signal. The second clock signal is delayed from the first clock signal by a predefined time period.

Abstract: A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams.

Abstract: A variable clock control information generator receives graphics engine activity data relating to the operating level of a graphics engine, and memory activity data relating to an activity level of memory. In response, the variable clock control information generator produces graphics engine clock control information and memory clock control information with respect to each other, such that a relative difference between the graphics engine activity data and the memory activity data is within balance threshold data. Accordingly, the variable clock control information generator adapts to the varying levels of graphics engine activity and memory activity and adjusts the frequency of the graphics engine clock signal and the frequency of the memory clock signal to achieve a balanced relative activity level.

Abstract: A high speed memory system includes a plurality of memory devices; a plurality of buffers; and a memory controller. The plurality of buffers is respectively coupled to the plurality of memory devices. The memory controller is coupled to the plurality of buffers, for generating a plurality of control signal to the plurality of buffers and sequentially controlling access to the plurality of memory devices in a time-sharing manner according to a clock.

Abstract: Embodiments of the disclosure generally set forth techniques for supplying different voltage levels and clock signals to a processor core. One example method includes determining a first workload of a first processor core in the multi-core processor for performing a first computing task associated with a first image area and a first geometric mapping between the first computing task and the first processor core, selecting a first voltage level or a first clock signal having a first clock frequency for the first processor core based on the determined first workload, wherein the first voltage level is compatible with the selected first clock frequency, initiating a voltage change to the first processor core based on the selected first voltage level, and initiating a clock change to the first processor core based on the selected first clock signal having the first clock frequency.

Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.

Abstract: A method of controlling core clocks in a multicore central processing unit is disclosed and may include executing a zeroth dynamic clock and voltage scaling (DCVS) algorithm on a zeroth core and executing a first DCVS algorithm on a first core. The zeroth DCVS algorithm may operable to independently control a zeroth clock frequency associated with the zeroth core and the first DCVS algorithm may be operable to independently control a first clock frequency associated with the first core.

Abstract: A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. A method for clocking a plurality of clocked data processing devices comprises controlling a generation of a plurality of clock signals and controlling an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices.

Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.

Abstract: A computer system has an adjustable data transmission rate between a CPU and a core logic chip thereof. In the computer system, the CPU has a power state adjustable in response to a power management control signal issued by the core logic chip. For adjusting data transmission rate between the CPU and the core logic chip, a change of an asserted time of the power management control signal from a first time period to a second time period is first determined to obtain an index value. The data transmission rate is increased or decreased according to the index value.

Abstract: An information processing apparatus transferring data between at least a plurality of processors through first and second routes running through first and second data transfer circuits, which retires the first and second routes so as to reduce the power consumption under the control of a system control device. The system provides a unit for measuring the amounts of data transfer on the first and second routes and measures the usage rates of the first and second routes. It monitors the measured usage rates by the system control device and, when the usage rates are below a predetermined value, controls the first or second data transfer circuit to make it retire the first or second route.

Abstract: A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a central processing unit (CPU) configured to output first control signals in response to a first clock signal, a first bus connected to the CPU, a bridge circuit connected to the first bus, a second bus connected to the bridge circuit, a plurality of peripheral circuits connected to the second bus, and a clock monitor connected to the first bus or the second bus and configured to output a register value corresponding to a second clock signal to the bridge circuit. The bridge circuit receives the first control signals, generates second control signals based on the register value, and outputs the second control signals to one of the peripheral circuits via the second bus.

Abstract: A clock generation circuit for a semiconductor memory apparatus includes an internal clock generation unit that receives a clock and generates an internal clock, and a clock selection unit that selectively outputs the clock or the internal clock in response to a selection signal.

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Abstract: Various exemplary embodiments relate to an event-driven microprocessor and a related method. A microprocessor may halt processing instructions when it executes a halting command. Thereafter, an EPU clock may stop its processing cycle and therefore halt microprocessor execution until it receives a start signal by a pattern detector. The pattern detector may use a plurality of bit slices to monitor a plurality of external inputs for the occurrence of events specified by the user. Some embodiments may also allow the user to check functioning by skipping upcoming instructions if a monitored event did not occur. By halting the EPU clock and the execution flow of the microprocessor, the event-driven microprocessor minimizes waste associated with executing a main control loop while waiting for a monitored event to occur. This may save processing capacity, memory, and power associated with continually running the main control loop.

Abstract: A phase amount added to a clock signal or a plurality of data signals for adjusting a phase relationship therebetween in a reception apparatus is changed, and, a result of the phase adjusting operation is stored when the phase amount added to the clock signal or the plurality of data signals is changed.

Abstract: An electronic device for data processing is disclosed having a CPU (3), a Closely Coupled Memory (5), an external memory system (8), and a first clock unit (1) and second clock unit (9) for receiving a main clock signal (2) and converting the main clock signal (2) into a first clock signal (6) for at least the Central Processing Unit (3) and Closely Coupled Memory (5) and a second clock signal (10) for the external memory (8). The first clock signal has a first clock frequency and the second clock signal has a second clock frequency being higher than said first clock frequency and wherein the device is configured to switch per time unit the external memory for an active period Tactive in an active state and for a standby period Tstandby in a standby state to retrieve a predetermined amount of data from the external memory per time unit.

Abstract: A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

Abstract: A method and system for digitally controlled multi-frequency clocking are provided. The method includes receiving a system reference oscillator clock frequency at a microprocessor including multiple cores. The system reference oscillator clock frequency provides a reference frequency to a local oscillator. The local oscillator supplies a core clock frequency to at least one of the cores. The method further includes adjusting the local oscillator to output the core clock frequency at a frequency greater than the system reference oscillator clock frequency as a function of digital frequency characteristic data associated with the core or cores. The method supports extendibility to larger systems and may support enhanced power management through frequency adjustments at the core level.

Abstract: A data processing apparatus has initiator circuitry for initiating a transfer of payload data in a first clock cycle, and recipient circuitry for receiving the payload data in a later clock cycle. A communication channel carries the payload data along with associated transfer control information. Timing of receipt of the payload data by the recipient circuitry is controlled by the transfer control information. Timing easing circuitry located within the communication channel temporarily buffers the transfer control information before outputting it to the recipient circuitry. The timing easing circuitry is responsive to a specified timing easing value to determine a time for which the transfer control information is temporarily buffered. The number of clock cycles that elapses between the first clock cycle and the later clock cycle depends on the specified timing easing value. This enables a multi-cycle path to be provided to transfer the payload data.

Abstract: A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.

Abstract: A method and apparatus for digital I/O expander chip with multi-function timer cells have been disclosed. A series of match reload registers load a series of match registers which are driven by a master counter. The status of the match registers can be retrieved through ports. The master counter is reloaded on rollover by a count limit register. The master counter has increment/decrement control and the rollover can be used in an interrupt control block to generate an interrupt request.

Abstract: The present invention provides a measure for getting read/write control information stored within a space of a predetermined size in a format that ensures compatibility with media of a lower order or an older generation even if the size of the read/write control information increases significantly as the storage densities of information storage media rise in the near future. On an information storage medium, a data sequence is writable as a combination of marks and spaces. The medium has at least one information storage layer, which has an information storage area to store information and a control information area for use to perform a read/write operation on the at least one information storage layer. The control information area stores at least one set of control information, which includes a first kind of write pulse information including information to be used as a reference value and a second kind of write pulse information including information to be used as an offset value.

Abstract: One embodiment is a clocking system for a computing environment. The system comprises a first set of processes executing in a first computing environment; a first local clock mechanism associated with the first set of processes; and a first communications channel for connecting the first local clock mechanism with the first set of processes. The first local clock mechanism stores clock rates of the first set of processes, wherein each clock rate is specified by function and source and destination combination, the first local clock mechanism further coordinating the clock speeds of the first set of processes as necessary.

Abstract: A method for refreshing memory is provided. The method comprises determining when a first memory of a plurality of memories is not being accessed and sending a refresh opportunity command from a master refresh controller to one of a plurality of local refresh controllers when the first memory is not being accessed, wherein the one of a plurality of local refresh controllers controls only the first memory. The method further comprises determining when the first memory needs refreshing and refreshing the first memory.

Abstract: Generally, the present disclosure concerns systems and methods for shadowing status for a circuit with a shadow unit. In one aspect, a system comprises a first circuit in a first dynamic clock domain of a plurality of dynamic clock domains, a processor configured to execute software instructions to generate a request for a status of the first circuit, and a second circuit coupled to the first circuit and to the processor. The second circuit, outside the first dynamic clock domain, is configured to shadow a status of the first circuit and to respond to the request for the status of the first circuit with the shadowed status.

Abstract: A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol interference, high-frequency loss, skew between the clock and data channels, and differential skew within a differential signal are compensated by analog circuits which are automatically tuned for best performance by observing the quality of the recovered analog signal. Oversampling is used to provide a 24-bit digital representation of the analog signal for determining the quality of the signal. A corresponding method of deskewing a differential signal and a system and circuit therefor are also provided.

Abstract: An image processor for lowering data transfer speed. A JPEG compression circuit performs two-dimensional compression process on data output from a YCbCr conversion circuit to generate compressed image data. A timing signal generator changes the frequency of a transfer clock signal in accordance with the compressed image data. An output circuit outputs the compressed image data in accordance with the transfer clock signal.

Abstract: An asynchronous data holding circuit including a source synchronizer which acquires an enable signal synchronized with a destination clock, in response to a rising or falling edge of the enable signal, acquires the other one of the rising or falling edge of the enable signal in synchronization with a source clock, and outputs the enable signal, a first data holding unit which holds a data signal from the source, in response to the enable signal from the source synchronizer and the source clock, a destination synchronizer which outputs the enable signal from the source synchronizer, in synchronization with the destination clock, and a second data holding unit which holds the data signal in the first data holding unit in response to the enable signal from the destination synchronizer and the destination clock, is provided.

Abstract: A digital circuit system includes: a register, for receiving and registering digital data; an operation unit, for operating and generating resulting data according to the digital data registered in the first registering unit; a second register, for receiving and registering the resulting data; a multi-phase clock signal generating unit, for generating a plurality of reference clock signals having different phases with each other; a first selector, for selecting one of the reference clock signals to output a first clock signal to the first registering unit; and a second selector, for selecting another of the reference clock signals to output a second clock signal to the second registering unit.

Abstract: A device may include a processor to execute a thread. The processor may be further configured to execute a set of wrappers that are called from within the thread to invoke a set of one-shot signal objects to generate delayed signals. Each of the set of wrappers may be configured to detect whether different ones of one-shot signal objects that were invoked from within the thread have generated signals at periodic time intervals, determine a delay to be used for invoking one of the set of one-shot signal objects, and invoke the one of the set of one-shot signal object to generate one of the delayed signals based on the delay when the different ones of one-shot signal objects have generated signals at periodic time intervals. The processor may be further configured to receive the delayed signals generated from the set of one-shot signal objects over a time period.

Abstract: A universal serial bus (USB) device for receiving data from a link partner is provided. An electrical physical unit receives a series of data from the link partner via a cable and generates a symbol string corresponding to the series of data, wherein the symbol string includes a plurality of symbols. A correction unit receives the symbol string, determines whether each symbol of the received symbol string is a first type symbol and counts a quantity of the received first type symbol, wherein when the counted quantity is odd and a next received symbol is a second type symbol, the next received symbol is replaced with the first type symbol by the correction unit.

Abstract: The invention relates to an automation device, with which a multiplicity of physically distributed functional units communicate with each other by means of a common transmission protocol. The device has a microcontroller (110), which is assigned at least one clock generator (120) and one memory unit (150), and which is connected at least to one data source (140), which is designed to output a data bit-stream to be transmitted.

Abstract: Systems and methods are disclosed that promote communication in an I2C Bus. These systems and methods include establishing a connection between at least two units within coupled together in a I2C bus, transmitting a message from a master to a slave, transitioning the slave to below a threshold during communications, and delaying additional messages from the master to the slave.

Abstract: A storage device includes a nonvolatile storage section; and a control section that controls the nonvolatile storage section, wherein the control section includes an access control section that outputs a clock for access control for performing access control of a read/write of the nonvolatile storage section, and performs access control of the read/write to the nonvolatile storage section, and a masking process section that performs the masking process of a reset signal on the basis of the clock for access control from the access control section, and supplies the reset signal after the masking process to the access control section.