Abstract: The present invention provides a processor comprising: an execution unit arranged to execute a plurality of program threads, clock generating means for generating first and second clock signals, and storage means for storing at least one thread-specific clock-control bit. The execution unit is configured to execute a first one of the threads in dependence on the first clock signal and to execute a second one of the threads in dependence on the second clock signal. The clock generating means is operable to generate the second clock signal with the second frequency selectively differing from the first frequency in dependence on the at least one clock-control bit. A corresponding method and computer program product are also provided.

Abstract: A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode.

Abstract: A method for communication via a bidirectional data link between a processing device and a memory device. The memory device includes a clock source to generate a clock signal for driving a latching at the memory device of data to and/or from the bidirectional data link. The memory device provides the clock signal to the processing device for driving a latching at the processing device of data to and/or from the bidirectional data link.

Abstract: A system and method for providing modified rights information to an application on an electronic device. A centralized component monitors both a system clock and a secure clock. The centralized component calculates the difference between the time of the system clock and the time of the secure clock and thereafter modifies the access rights information for the application by the difference between the times. The modified access rights information is then presented to the application for use.

Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.

Abstract: In one embodiment, a communication system for a multi-blade server system includes a multi-drop serial bus network interconnecting a management module with each of a plurality of servers in a multi-server chassis. A first transceiver subsystem is configured for communicating over the serial bus network between the management module and each server within a first frequency band. A second transceiver subsystem is configured for simultaneously communicating over the serial bus network between the management module and the servers within a second frequency band higher than the first frequency band. A first signal-filtering subsystem substantially filters out signals in the second frequency band from the first transceiver subsystem. A second signal-filtering subsystem substantially filters out the signals in the first frequency band from the second transceiver subsystem.

Abstract: A precision oscillator for an asynchronous transmission system. An integrated system on a chip with serial asynchronous communication capabilities includes processing circuitry for performing predefined digital processing functions on the chip and having an associated on chip free running clock circuit for generating a temperature compensated clock. An on-chip UART is provided for digitally communicating with an off-chip UART, which off-chip UART has an independent time reference, which communication between the on-chip UART and the off-chip UART is effected without clock recovery. The on-chip UART has a time-base derived from the temperature compensated clock. The temperature compensated clock provides a time reference for both the processing circuitry and the on-chip UART.

Abstract: A structure for performing cross-chip communication with mesochronous clocks. The structure includes: a data delay line; a remote clock delay line; a structure that captures at least one value of a state of a delayed remote clock signal on the remote clock delay line; and a control that influences a delay associated with the data delay line and the remote clock delay line.

Abstract: An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

Abstract: The present invention relates to methods and apparatus for data transfer. A data interface is described with at least a first data terminal for either outputting or receiving a data signal. In bi-directional embodiments there may be one terminal for receiving data and one terminal for outputting data. A bit clock terminal outputs or receives a bit clock signal; and a frame clock terminal for outputs or receives a frame clock signal. Interface control circuitry is configurable to associate data outputted or received in each frame with time slots (1-8) of a predetermined number of bits (x, y, z) wherein the control circuitry is adapted such that the frequency of the bit clock signal can be changed at any time so as to vary the number of time slots in a frame.

Abstract: A multi-core electronic system for accessing a data storage device includes a plurality of processors, a data transmission interface and a rate adjustment module. The processors respectively provide a bandwidth requirement, and communicate with the data storage device via the shared data transmission interface. The rate adjustment module receives the bandwidth requirements, and determines a transmission rate of the data transmission interface according to the bandwidth requirements.

Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

Abstract: A digital VLSI circuit is provided with functions in which the number of switching operations to supply electric power to each arithmetic operation unit is reduced in a restricted period of time while electric power supply is controlled for each arithmetic operation unit, so that low power consumption can be achieved in real pipe-line arithmetic operation.

Abstract: A circuit and method has a processing unit, a master clock generator for providing a master clock and a plurality of phase-locked loops, each providing a respective clock signal. A plurality of dynamically variable delay circuits each has a plurality of predetermined delay amounts. Clocked circuits are coupled to respective clock signals provided by respective phase-locked loops. A performance detector is coupled to receive the clock signals for determining a center of a quiet zone for at least one of the plurality of phase-locked loops. The phase-locked loops are turned off and on and a respective one of the plurality of dynamically variable delay circuits is set to have a new predetermined value of delay which adjusts an edge of the master clock to a location that permits the data processing system to operate near substantially the center of the quiet zone.

Abstract: In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed.

Abstract: Methods and apparatus are provided for allowing efficient clock domain crossing management in programmable chip systems. Components associated with different clock domains can be analyzed. Clock domain crossing components are automatically selected from a library of clock domain crossing components to allow connection between disparate clock domains. Clock domain crossing components can be shared, chained, and intelligently selected for increased efficiency.

Abstract: The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB specification to provide synchronization information from an external source, and in another aspect comprising observing USB traffic and locking a local clock signal of a USB device to a periodic signal contained in USB data traffic, wherein the locking is in respect of phase and/or frequency.

Abstract: The disclosed embodiments relate to buffer circuits and methods. One embodiment is a buffer circuit that receives a data signal, a first clock signal and a second clock signal, the buffer circuit comprising circuitry to latch the data signal with the first clock signal to produce a first latched signal, circuitry to latch the data signal with the second clock signal to produce a second latched signal, and circuitry that selects the first latched signal or the second latched signal depending on a transition of the data signal in a previous clock cycle.

Abstract: A data processing circuitry for processing data is disclosed.

Abstract: A method for controlling the execution of a process in a user device, such as a set-top-box is provided. An instruction is received at an input of the user device from the user and this instruction causes an uninterruptible process to begin or commence in the user device after a time delay, measured preferably from receipt of the initial instruction. The input, or inputs, of the device is/are monitored to determine whether a subsequent instruction is received from the user within a time period. Based on this determination, the time delay applied to future processes is adjusted. By adjusting the time delay in response to input from the user, the time delay can be automatically matched to a user's preferences. By adjusting the time delay in response to input from the user, the time delay can be automatically matched to a user's preferences. A corresponding apparatus and computer program are also provided.

Abstract: A mechanism is provided for monitoring and verifying a clock state of a chip that does not write out clock state information. Responsive to identifying an access to the chip, the access is scanned to identify a chip register and a clock domain that will be accessed. A determination is made as to whether a bit of a clock trust unit associated with the chip register and the clock domain indicates whether to trust a clock state associated with the bit in a logical clock state unit. Responsive to the bit of the clock trust unit indicating that the clock state associated with the bit in the logical clock state unit is trusted, the clock state from the logical clock state unit is identified. Responsive to the clock state matching the clock state required by the access, the access is forwarded to the chip for execution.

Abstract: A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.

Abstract: A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (which, in turn, is derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal advances onset of the PHEQ (phase equalization) phase and is used to terminate the ForceSL and On1x modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during On1x exit.

Abstract: A memory interface circuit includes a clock signal supply buffer configured to send a system clock signal which is supplied through a reference node, to a memory through a transmission line; a data strobe buffer configured to receive a data strobe signal supplied from the memory; a system clock synchronizing circuit configured to supply a data read from the memory to a logic circuit in synchronization with the system clock signal; and a delay detecting circuit provided at a front stage to the system clock synchronizing circuit and configured to detect a transmission delay from the clock signal supply buffer to the data strobe buffer. The delay detecting circuit generates a phase difference data indicating the transmission delay based on a difference between a phase of the system clock signal and a phase of the data strobe signal outputted from the data strobe buffer, and supplies the phase difference data to the system clock synchronizing circuit.

Abstract: A computer motherboard with automatically adjusted hardware parameter values restarts automatically and proceeds with overclocking or power-saving operation in case the computer motherboard hangs due to preceding overclocking or power-saving operation.

Abstract: A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is configured to be clocked with a first clock frequency, and a second memory channel being configured to couple the central processing unit to a second semiconductor memory unit, wherein the second memory channel is configured or configurable to be clocked with a second clock frequency smaller than the first clock frequency.

Abstract: A memory block includes a memory circuit and a clock generation unit. The memory circuit may output read data in response to being clocked by a clock signal having a selectable delay that may be dependent upon a time taken for the read data to be output by a memory core after the read command is received at the memory block. The clock generation unit may cause the read data to be provided as an output of the memory block in response to being clocked by a selected data clock signal. The data clock signal may be selected from one of several clock edges generated by one of several clock edges of a system clock such that regardless of the frequency of the system clock, the read data is provided by the memory block a predetermined amount of time after the read command is received at the memory block.

Abstract: An integrated circuit (IC) includes a clock circuit, a processing module, and processing circuitry. The clock circuit is coupled to produce a digital clock signal. The processing module is coupled to determine whether a harmonic component of the digital clock signal having a nominal digital clock rate is within the frequency passband and to provide an indication to the clock circuit to adjust its rate from the nominal digital clock rate to an adjusted digital clock rate when the harmonic component of the digital clock signal is within the frequency passband. The processing circuitry is coupled to process, at the adjusted digital clock rate, the data to produce processed data having a rate corresponding to the nominal digital clock rate and to interpolate, at an interpolation rate, the processed data to produce interpolated processed data having a rate corresponding to the interpolation rate.

Abstract: A clock generating device, method thereof and a computer system using the same are provided. The clock generating device includes a PLL module and a tuning module. The PLL module receives a reference clock signal, and generates an output clock signal as a basic clock of a computer system according to a phase difference between a reference clock signal and a feedback signal. The PLL module includes a frequency divider adjusting an intrinsic frequency dividing ratio according to a control signal and performs a frequency dividing processing on the output clock signal to generate a feedback signal. The tuning module coupled with the PLL module generates the control signal according to a VID of a CPU and one of the feedback signal and the reference clock. Therefore, the operation frequency of the components serving the output clock signal as the basic frequency in the computer system can be synchronously tuned.

Abstract: An electronic circuit has an interface for an I2C-bus. The interface comprises a first node for a clock line of the I2C-bus; a second node for a data line of the I2C-bus; and an I2C-bus controller for controlling an operation of the interface under combined control of the clock line and the data line. The circuit has a plurality of further nodes for connecting to a plurality of further data lines. The controller has an operational mode for control of receiving from the further nodes, or for control of supplying to the further nodes, a plurality of data bits in parallel under combined control of the clock line and the data line.

Abstract: A clock controlling apparatus of a computer system used to tuning a clock frequency of a specific electronic device disposed on a motherboard and the application thereof are disclosed, wherein the clock controlling apparatus comprises an input control unit used to output a frequency increasing signal or a frequency decreasing signal, a control circuit connected to a clock generator disposed on the motherboard in order to tune the clock frequency of the electronic device according to the frequency increasing signal or the frequency decreasing signal, and a displaying unit connected to the control circuit in order to show the clock frequency.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: A system and method provide adaptive frequency scaling for predicting the load on a processing unit and dynamically changing its clock frequency while keeping the synchronization with other processing units. The amount of data in an input memory waiting to be processed is a good indicator of the current load and thus embodiments utilize the same concept for predicting the load on the processing unit. The frequency of operation is thus changed on the basis of the percentage of memory being occupied by its input data. Algorithms according to embodiments allow the processing unit to use the maximum possible clock frequency only when it is required and to run at some lower frequencies in low processing power requirements. Operating the circuit at low frequency helps in reducing power consumption.

Abstract: A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of pipeline units in the pipeline accelerator, one can increase the accelerator's data-processing performance as compared to a single-pipeline-unit accelerator. Furthermore, by designing the pipeline units so that they communicate via a common bus, one can alter the number of pipeline units, and thus alter the configuration and functionality of the accelerator, by merely coupling or uncoupling pipeline units to or from the bus. This eliminates the need to design or redesign the pipeline-unit interfaces each time one alters one of the pipeline units or alters the number of pipeline units within the accelerator.

Abstract: Aspects of the disclosure provide a network device. The network device includes a first port coupled to a first device to communicate with the first device, and a clock wander compensation module. The first port recovers a first clock based on first signals received from the first device. The clock wander compensation module includes a global counter configured to count system clock cycles based on a system clock of the network device, and a first port counter configured to count first clock cycles based on the recovered first clock. Further, the first port transmits a first pause frame to the first device based on the global counter and the first port counter.

Abstract: A method for overclocking a central processing unit (CPU) of a computer motherboard is disclosed. Step A is to set a second frequency of front side bus (FSB) by an operating interface of BIOS. Step B is to determine FSB frequency Fn at each of N stages according to a difference between a first frequency and the second frequency. Step C is to load the CPU with an operating system by booting the CPU at the first frequency of FSB, and send an interruption signal to the CPU from a chipset at predetermined intervals upon completion of the loading of the operating system so as to allow the BIOS to gain control over the CPU, and execute step D by the CPU on each of N occasions of interruption until the FSB frequency of the CPU is changed to the second frequency. Step D is to execute the BIOS by the CPU on the nth occasion of interruption such that the CPU operates at the FSB frequency Fn, and allow the operating system to resume control over the CPU.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

Abstract: Method of controlling a wind power system including a plurality of system elements, the wind power system including a plurality of data processors distributed in the system elements, the method including the steps of: synchronizing at least a part of the data processors to at least one reference signal distributed to the data processors from a time synchronization arrangement, associating the data processors with local clock generation circuitries, wherein the local clock generation circuitries associated with data processors of a first subset of the data processors have a peak-to-peak tracking jitter higher than or equal to a predetermined threshold value and wherein a second subset of the data processors have a peak-to-peak tracking jitter less than the predetermined threshold value, controlling at least one of the system elements at least partly by means of a data processor from the first or second subset of data processors.

Abstract: In some embodiments, the present invention relates to a method of maintaining a global clock within a multiprocessor system having a plurality of nodes that are connected in a network via links. A virtual spanning tree is mapped onto the network and the nodes and the links are configured such that each node is in a parent-child relationship with one or more other nodes in the virtual spanning tree. A global clock is generated in a root of the virtual spanning tree and global clock signals are communicated down the virtual spanning tree to each of the nodes.

Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

Abstract: Methods and systems for resolving clock management issues in emulation of a target system on a host system are disclosed. A first set of code instructions of a target program is emulated to generate a first set of emulated instructions that emulate a first component on the host system. A second set of code instructions is emulated to generate a second set of emulated instructions that emulate a second component of the target system on the host system. The first set is executed based on a first clock (which may be a fixed clock) and the second set is executed based on a second clock (which may be a variable clock). The host system adjusts the first or second clock, execution of the first or second sets of instructions or a memory access to maintain a desired synchronization between the first and second sets of instructions.

Abstract: Provided is a delay adjustment device that contributes to downsizing the circuit that adjusts a flight time. The delay adjustment device is connected to a memory, and adjusts a timing to retrieve data with a data signal and a data strobe signal output from the memory. The delay adjustment device includes a data retrieve unit that receives the data signal and the data strobe signal, and outputs a data value of the data signal in accordance with the data strobe signal; and a control unit that issues a read command to the memory, calculates a flight time, and controls a valid period of the data strobe signal based on the flight time.

Abstract: In some embodiments, a method includes characterizing a plurality of channels, each of the plurality of channels being a channel between a location and a respective one of the plurality of communication interfaces; for each of the plurality of communication interfaces, supplying signals to the communication interface and detecting interference that occurs at the location as a result of emissions radiated from the plurality of communication interface while the signals are supplied thereto; for each of the plurality of communication interfaces, determining an estimate of interference that would occur at the location as a result of emissions radiated from the communication interface while the signals are supplied thereto, based at least in part on the characterization of the channel between the location and the communication interface; and for each of the plurality of communication interfaces, comparing the estimate of interference that would occur at the location to the detected interference that occurs at the

Abstract: A memory interface allows access to SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n (n>1) column memory addresses from the received column address. The interface accesses the synchronous dynamic memory to read or write n bursts of data at the n column memory addresses. Preferably, the SDRAM is clocked at n times the rate of the interconnected memory accessing device, and the memory units. The data units in the n bursts preferably have one nth the expected bit size. In this way, SDRAM may be accessed with high memory bandwidth, without requiring an increase in the size of data units in the SDRAM, and the associated data bus. Conveniently, the interface may be operable in two separate modes or configurations. In one mode, SDRAM may be accessed through the interface in a conventional manner. In the second mode, SDRAM is accessed in multiple bursts for each received burst access.

Abstract: A microcontroller that includes logic to provide a uniform overall power consumption current of parts of the microcontroller generated by sequential element switching is disclosed. For example, the number of sequential elements switching at the triggering edge of the clock is calculated to determine a number of switching elements. The number of switching elements is compared to the number of sequential elements of the circuitry. Additional sequential elements are added in the circuitry and are forced to switch so that the overall number of switching elements equals the number of sequential elements, excluding the additional sequential elements.

Abstract: There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption under non-contact usage, and ensuring high-speed processing under non-contact usage. A dual interface card is a battery-less IC card capable of operating in accordance with a contact usage or a non-contact usage. The dual interface card operates at a high clock under contact usage and at a low clock under non-contact usage. A targeted operation comprises a plurality of different basic operations. The dual interface card comprises a basic arithmetic circuit group. Under the contact usage, the basic arithmetic circuit group performs one basic operation of the targeted operation at one cycle. Under the non-contact usage, the basic arithmetic circuit group sequentially performs at least two basic operations of the targeted operation at one cycle.

Abstract: A timer service uses a single timer function to perform timing services for both relative and absolute timers. The first timers from a sorted array of absolute timers and relative timers are used in a function that will return when the earliest absolute timer expires or will timeout when the earliest relative timer expires. The timer function may be interrupted when a new timer is added to one of the arrays. The function will operate in a predictable and consistent manner, even when a system clock is adjusted.

Abstract: A synchronizing circuit includes an internal partial power supply interruption circuit section which can be subjected to a power supply interruption and includes a data transmission register configured to output data for controlling a power supply interruption and a clock enable control register configured to output an enable signal; an internal partial power supply interruption control circuit section configured to control a power supply interruption and includes a gated clock buffer configured to control a clock signal based on the enable signal, and a data reception register configured to take in data based on the controlled clock signal; and an isolation cell configured to output an output from the internal partial power supply interruption circuit section as a fixed value when the internal partial power supply interruption circuit section has been subjected to a power supply interruption.

Abstract: According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit includes a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock, and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information concerning an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.