Abstract: According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit includes a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock, and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information concerning an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.

Abstract: To provide a semiconductor device including a data input circuit and a data output circuit connected to a plurality of data input/output terminals, where at least one of the data input circuit and the data output circuit fetches data in response to multi-phase clock signals having different phases to be timing signals for fetching data, and adjusts a valid range for fetching data to be substantially uniform for each of the multi-phase clock signals. According to the present invention, the window width of data can be made uniform by individually adjusting the multi-phase clock signals that are input or output timing signals, and thus characteristics of the semiconductor device can be improved.

Abstract: Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.

Abstract: In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow.

Abstract: A mechanism for updating memory controller timing parameters during a frequency change includes a memory controller that controls memory transactions to a memory unit. The integrated circuit may also include a power manager unit that is coupled to the memory controller and may be configured to provide an indication that a memory clock frequency is changing to a new frequency. The integrated circuit also includes a storage that includes a number of entries. Each entry may store a predetermined set of timing values that corresponds to a respective memory clock frequency. In response to receiving the indication, the memory controller may access a given entry of the storage that corresponds to the new frequency, and may generate new timing values that correspond to the new frequency based upon the predetermined set of timing values stored within the given entry.

Abstract: A data processing apparatus comprising: a gate unit connected to an input or an output of a processing unit and configured to cut off the data input and output; a control unit configured to control a supply of clock to the processing unit; and an instruction unit configured to give an instruction for the clock control to the control unit, wherein the control unit controls the gate unit and controls the clock supplied to the processing unit based on an instruction from the instruction unit, whereby securing a higher power saving effect.

Abstract: In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer, generating a mapping of which second clocks of the reader that the reader is allowed to read from the queue, based at least in part on the first and second clocks, and reading the data from the entry at an allowed second clock. Other embodiments are described and claimed.

Abstract: A method and apparatus for handling, maintaining, and controlling network synchronization information emanating from a plurality of line card circuits is described. The technique described may be applied to a redundant pair of line card circuits, where one line card circuit is active, while the other is inactive. Line card activity latches are managed by means of hardware logic that may be configured at the time of line card commissioning. The activity latches are coupled to a logic element. An incoming clock signal is applied to the logic element. If an activity latch indicates that a line card circuit is active, the logic element provides the incoming clock signal as an outgoing clock signal to a control card circuit. If the activity latch indicates that the line card circuit is inactive, the logic element blocks the incoming clock signal from being passed and provides a static output level as the outgoing clock signal to the control card circuit.

Abstract: A system and method are provided for decoding an audio signal. In one embodiment, a first pulse is identified with a predetermined relative duration with respect to a second pulse. A sampling frequency is then calculated based on such identification. In another embodiment, an audio signal is decoded utilizing a threshold. In still yet another embodiment, a decoder is provided for decoding an audio signal utilizing a clock that is independent of the audio signal.

Abstract: A plurality of operation units connected in a pipeline structure performs an operation processing on data. A process control unit operates in synchronization with a system clock signal and generates a process control signal for controlling the operation units upon receiving a data notification signal that notifies the process control unit of an arrival of data from outside. A clock-control signal generating unit operates in synchronization with the system clock signal and generates a clock control signal for controlling a clock supply to each of the operation units upon receiving the process control signal.

Abstract: A block control device for a semiconductor memory and a method for controlling the same are disclosed, which relate to a technology for controlling a block operation state of a Low Power Double-Data-Rate 2 (LPDDR2) non-volatile memory device. A block control device for use in a semiconductor memory includes a block address comparator configured to compare a first block address with a last block address, and output a same pulse or unequal pulse according to the comparison result, a block address driver configured to output a lock state control signal for driving a block address in response to the same pulse, a block address counter configured to count block addresses from the first block address to the last block address in response to the unequal pulse, and generate a block data activation pulse, and a block address register configured to store a lock state of a corresponding block in response to the lock state control signal and the block data activation pulse.

Abstract: A sorter system includes a clock continuously generating a series of clock signals, a systolic array circuit, and control circuitry in communication with serial access memory that stores data items of a sequence to be sorted and with the systolic array circuit to supply thereto data items as input and to receive therefrom data items as output. The systolic array circuit includes at least one processing module and K?1 registers, where K is an integer value greater than two. Each processing module has at least one of the registers, each register for storing one data item. The control circuitry serially presents K data items for input to the systolic array circuit in synchronization with the clock signals. On the next clock cycle after the control circuitry presents to the systolic array circuit the last of the K data items, the data item of least value in the given subsequence is output.

Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.

Abstract: A method for an impaired user to control a peripheral device including receiving key-value pair input from the user, determining whether the received input is valid and executing a job generated from the valid received key-value pair input.

Abstract: A method of accessing electronic memory is provided in electronic circuits where it is desired to lower power consumption and hence there is no active oscillator at the time when access to data within the electronic memory is required. The invention provides a method therefore for accessing the electronic memory from a controller, which generates its own clock signals from a data, communications bus electrically coupled to the controller. Advantageously the method allows for memory access to be continued in integrated circuits where a subset of circuits are powered down to reduce power consumption, and one of the subset of circuits is an oscillator.

Abstract: A wireless device includes a functional unit, a wireless transceiver, an antenna and a clock. The wireless transceiver and antenna are coupled to the functional unit. The clock is coupled to the functional unit and the wireless transceiver. The clock is generates a clock signal. The wireless device is coupled wirelessly to a wireless slave device. The functional unit is configured to determine an amount of time since a last keep alive transmission with the slave device has occurred based on the clock. The functional unit determines a number of keep alive transmissions to transmit to the slave device, and appropriate transmission times for the keep alive transmissions relative to a next scheduled keep alive transmission time, based on the determined amount of time since the last keep alive transmission. The functional unit begins successive transmission of the keep alive transmissions to the slave device per the transmission times.

Abstract: A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.

Abstract: A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom.

Abstract: A selectively synchronous wave pipeline segment and an integrated circuit (IC) including the segment. The segment includes a normally opaque input stage and output stage and multiple internal stages that are normally transparent. A programmable local clock control circuit provides internal stage clock selection control to internal stages. The internal clock selection control determines whether each internal pipeline stage is gated opaque by a local clock. The programmable local clock control circuit is programmed to allows data items to propagate as data waves in a wave pipeline until each wave reaches a point where beyond, a race condition is likely to exist. Multiple pipeline data items pass as data waves between input and said output stage selectively unclocked.

Abstract: One or more counter units of a data acquisition device used to perform sampling operations. Each of the counter units is configurable to operate in a selected one of a plurality of modes. During operation, at least one of the counter units may receive a measurement signal (or input signal) acquired by the data acquisition device and also a sample clock signal. The counter unit may sample the measurement signal based on the selected operational mode and timing of the sample clock, and at a rate that is independent of the frequency of the measurement signal. Furthermore, the counter unit may sample the measurement signal based on a selected one of a plurality of timing modes associated with the sample clock signal. The counter units may take samples of the measurement signal to perform at least one of the following types of measurements: period, frequency, pulse-width, semi-period, time separation, or event counting.

Abstract: The invention describes a method for transferring data between a first clock domain having a first clock rate (CLK1) and at least one additional clock domain having a second clock rate (CLK2), comprising the following for the transfer of data from the first to the second clock domain (CLK1, CLK2): reading in of a data item in accordance with the first clock rate (CLK1) into a first memory (11), and locking of the first memory after saving the data item, signalizing a transfer start after saving the data item in the first memory (11) by means of a transfer start signal (TS), reading out the data item from the first memory, and reading in the data item into a second memory, each according to the second clock signal (CLK2), processing the transfer start signal (TS) according to the second clock signal (CLK2) for generating a transfer end signal (TD), processing the transfer end signal (TD) according to the first clock signal (CLK1) for generating a release signal (TD?) and releasing the first memory as a functi

Abstract: Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also generates a transfer enable signal based on the relative frequency of each clock signal to indicate when data can be transferred between the clock domains. Further, as the relative frequency of the clock signals change, the timing of the transfer enable signal also changes to ensure reliable data transfer.

Abstract: A clock timing calibration circuit includes a clock timing adjusting unit and a calibration control unit. The clock timing adjusting unit is for receiving an incoming reference clock signal and selectively adjusting the received reference clock signal to generate a first clock signal according to a calibration control signal. The incoming reference clock has a predetermined phase and a predetermined frequency, The calibration control unit is for checking if the phase difference between the first clock signal and a second clock signal satisfies a predetermined criterion, and for adjusting the calibration control signal when the phase difference between the first clock signal and the second clock signal does not satisfy the predetermined criterion. The predetermined criterion is to check if the phase difference falls within a specific range associated with a clock period of one of the first clock signal and the second clock signal.

Abstract: Multi-channel pulser driver circuitry for a sub-beam forming transmitter of an ultrasound system in which sub-beam signals are formed by delaying sub-beam pulse pattern data in accordance with sub-beam pulse delay data and multiple clock signals.

Abstract: A method for protecting a secured real time clock module, the method includes: locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration; unlocking the multiple input ports of the secured real time clock module if a predefined high frequency code is received over a control input port of the secured real time clock module; and providing a secured real time clock signal when the multiple input ports of the secured real time clock module are locked and when the multiple input ports of the secured real time clock module are unlocked; wherein changes in a supply voltage results in a supply voltage induced changes of an input signal provided to an input port of the secured real time clock module; wherein a maximal frequency of the supply voltage induced changes of the input signal is lower than the high frequency of the predefined high frequency code.

Abstract: A gearbox is placed between two clock domains to allow data to be transferred from one domain to the other. Although the two domains may operate at the same clock frequency, typically one domain has a faster clock speed than the other. The gearbox is disposed between the two clock domains to control timing of data transfer from one to the other, by selecting a pattern which identifies when data is made transparent for the transfer. The gearbox allows a number of clock ratios to be selected, so that a particular clock ratio between the two domains may be readily selected in the gearbox for the data transfer.

Abstract: An information processing apparatus having a processing circuit to execute a program by operating at a set operating frequency, including: a measuring section that measures an elapsed time from the user's last operation; a notification section that notifies operation allowing frequencies in the processing circuit and instructs, in response to an elapsed time longer than a predetermined threshold time measured by the measuring section, fixing to a specific low-operating frequency among the operation allowing frequencies and in response to the user's operation in an input section, instructs to release the fixing; and a setting section that selects an operating frequency from among the operation allowing frequencies according to a processing situation and sets the selected operating frequency to the processing circuit and upon release of the fixing, restarts setting of an operating frequency selected from among the operation allowing frequencies, according to a processing situation in the processing circuit.

Abstract: The invention provides an integrated circuit with reduced electromagnetic interference induced by memory access. The integrated circuit includes a random code generator, a request receiver and a memory unit. The random code generator generates a plurality of random codes according to a predetermined delay parameter. The request receiver obtains an input clock signal according to a plurality of data requests and spreads the spectrum of the input clock signal based on the random codes to derive a non-periodic output clock signal. The memory unit accesses image data to be displayed in response to the data requests and the output clock signal.

Abstract: This invention uses a flying adder frequency synthesis circuit to provide the required frequency adjustments to accommodate the varying encoding density of a MPEG2 video data stream. This invention adjusts the local clock based on the information extracted from the program clock reference signal in the incoming data. This invention replaces an external or internal voltage-controlled crystal oscillator using a phase locked loop circuit on the video processing integrated circuit.

Abstract: In an embodiment, a system comprises a first memory module interface unit (MMIU) configured to couple to a first one or more memory modules, and a second MMIU configured to couple to a second one or more memory modules. The first MMIU is configured to operate the first one or more memory modules at a first frequency and the second MMIU is configured to concurrently operate the second one or more memory modules at a second operating frequency different from the first operating frequency.

Abstract: A networking device includes a network port configured to receive a message from a remote networking device. The network port includes a detector configured to detect reception of the message. A queue controller is configured to integrate a timestamp with the message to generate a modified message. An ingress timer is configured to generate the timestamp based on an arrival time of the message at the network port.

Abstract: A Multi-Level Processor 200 for reducing the cost of synchronization overhead including an upper level processor 201 for taking control and issuing the right to use shared data and to enter critical sections directly to each of a plurality of lower level processors 202, 203 . . . 20n at processor speed. In one embodiment the instruction registers of lower level parallel processors are mapped to the data memory of upper level processor 201. Another embodiment 1300 incorporates three levels of processors. The method includes mapping the instructions of lower level processors into the memory of an upper level processor and controlling the operation of lower level processors. A variant of the method and apparatus facilitates the execution of Single Instruction Multiple Data (SIMD) and single to multiple instruction and multiple data (SI>MIMD). The processor includes the ability to stretch the clock frequency to reduce power consumption.

Abstract: A field device includes a real time clock, and at least one communication interface for at least unidirectionally, receiving and transmitting data. The real time clock is detachably connected to the at least one receiving communication interface of the field device, and includes a power supply.

Abstract: A method of and system for frequency clocking in a processor core are disclosed. In this system, at least one processor core is provided, and that at least one processor core has a clocking subsystem for generating an analog output clock signal at a variable frequency. Digital frequency control data and an analog signal are both transmitted to that at least one processor core; and that processor core uses the received analog signal and digital frequency control data to set the frequency of the output clock signal of the clocking subsystem. In a preferred implementation, multiple cores are asynchronously clocked and the core frequencies are independently set.

Abstract: An apparatus and method for fault-tolerant and spread spectrum clocking. In one embodiment a master clock synthesizer circuit generates an output clock signal of varying frequency within a predetermined range of frequencies. A slave clock synthesizer circuit is provided to track the output clock signal generated by the master clock synthesizer circuit. If the master clock synthesizer circuit fails or generates an invalid output clock signal, the slave clock synthesizer circuit takes over and functions as the master clock synthesizer circuit. In one embodiment a method of fault-tolerant spread spectrum clocking includes generating a first digital data stream; receiving the first digital data stream, a first input reference signal and a first clock signal in a master clock synthesizer circuit; generating an first output clock signal of varying frequency by the master clock synthesizer circuit in response to the first digital data stream and the first clock signal.

Abstract: An embodiment of a system for implementing parallel usage of a plurality of non-volatile input/output (I/O) devices can include an interface configured to receive, from a source, a source request and a first memory coupled to the interface. The first memory can be configured to store a data unit specified by the source request. The system can include an I/O device controller coupled to the interface. The I/O device controller can be configured to correlate the source request with a plurality of I/O device requests and initiate sending of the plurality of I/O device requests to the plurality of non-volatile I/O devices in parallel. The system also can include a decoder coupled to the first memory and the I/O device controller. The decoder can be configured to receive data from the plurality of non-volatile I/O devices in parallel.

Abstract: Systems and methods for synchronizing a source and sink device are disclosed. A sink device can efficiently determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method for transmitting a source data stream from a source device to a sink device includes, forming a logical channel from a source device to a sink device, where the logical channel is configured to carry the source data stream, and one or more rate parameters. The rate parameters relate a data rate of the source data stream to a data rate of the logical channel.

Abstract: Synchronization of two or more items can be optimized through the use of parallel execution of synchronization tasks and adaptable processing that monitors and adjusts for system loading. Two or more synchronization tasks required to be performed for an item can, if not inherently serial in nature, be performed in parallel, optimizing synchronization of the item. Even if multiple synchronization tasks required for one item must be serially executed, e.g., download the item prior to translating the item, these synchronization tasks can be executed in parallel for different items, optimizing a download request involving two or more items. Moreover, multiple threads for one or more synchronization tasks can be concurrently executed when supportable by the current operating system resources. Rules can be established to ensure synchronization activity is not degraded by the overextension of system resources.

Abstract: A content processing apparatus includes a plurality of takers. Each of a plurality of takers runs with reference to any one of N (N: an integer of two or more) of clocks, and the plurality of takers respectively take a plurality of contents. A mixer mixes the plurality of contents respectively taken by the plurality of takers so as to create equal to or less than N of output contents. A changer changes the clock referred to by each of the plurality of takers corresponding to a mode switching. An adjuster adjusts a mixing manner of the mixer in association with a change process of the changer so that a mixing process is executed for every contents corresponding to a common clock.

Abstract: A data reception apparatus is disclosed. The data reception apparatus includes a strobe extractor for receiving a transmission signal and extracting a strobe signal from the transmission signal, the transmission signal including the strobe signal inserted between data signals and a clock signal following the strobe signal, the strobe signal having a different magnitude from a magnitude of a data signal, and the clock signal having an equal magnitude to the magnitude of the data signal, a clock recoverer for recovering the clock signal from the transmission signal, using the extracted strobe signal, and a sampler for sampling the data signals included in the transmission signal in response to the recovered clock signal. The probability of generating a timing skew error in the time interval between a clock signal and a data signal is minimized. Even though the level of a common component might change, the clock signal can be recovered accurately and the size of the clock recovery circuit can be reduced.

Abstract: The claimed subject matter can provide an architecture that interfaces a single slave device such as a UICC smartcard with multiple host controllers. For example, a secondary host can be interfaced between a primary host (e.g. a controller in a cellular phone, a PDA, an MP3 player . . . ) to manage all transactions with the slave device. The secondary host can operate transparently to the primary host and thus does not require any modifications to the primary host. This can be accomplished, e.g. by employing the CMD channel (which is relatively sparsely used by the primary host) to communicate both commands and data with the slave. Moreover, the transactions initiated by the secondary host can be segmented into many smaller fragments and interleaved between transactions initiated by the primary host. In addition, the secondary host can temporarily take on the role of the slave device and affect direct communication with the primary host.

Abstract: A method for providing applications with a current time value includes receiving a trap for an application to access a time memory page, creating, in a memory map corresponding to the application, a mapping between an address space of the application and the time memory page in response to the trap, accessing, based on the trap, a hardware clock to obtain a time value, and updating the time memory page with the time value. The application reads the time value from the time memory page using the memory map.

Abstract: A method of calibrating read operations in a memory system is disclosed. The method involves placing a memory controller in a calibration mode, and performing a series of dummy read operations. Each of the read operations performs a read of pre-specified data stored in at least one memory component while using different ones of delayed enable signals. Data read from respective dummy read operations is compared to identify successful read operations while the timing information from successful read operations is compared to identify a suitable delayed enable signal.

Abstract: There is provided a signal synchronization method of performing signal synchronization between a device which operates in synchronization with a first clock signal and a processor which operates in synchronization with a second clock signal with a different cycle from that of the first signal.

Abstract: A method for transferring data between a serial peripheral interface (SPI) master device and an SPI slave device generates a first clock signal for the SPI master device and a second clock signal for the SPI slave device. Clock frequency of the first clock signal and the second clock signal is twice than a serial clock signal between the SPI master device and the SPI slave device. Data are transferred with double data rate or single data rate based on the first clock signal and the second clock signal.

Abstract: A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.

Abstract: A memory device is provided. The memory device includes a plurality of memory chips coupled in series, and a register serially coupled to the memory chips. The register includes an integrated delay-locked loop. The memory device may be included in a processing system. Moreover, a method for improving timing budgets in a registered dual in-line memory module (RDIMM) may be implemented using the memory device having a register with an integrated delay-locked loop.

Abstract: Clock synchronization for a wireless communication system is described. The communication system utilizes a server with a radio coupled to receive a radio frequency (RF) signal and a clock interface to receive a reference clock signal. The server includes a network interface configured to receive, from a base station, a time that the RF signal was received at the base station. The server further includes a processing device configured to determine when the RF signal was transmitted and a location of the base station, and configured to calculate clock offset value representative of a time to delay a local clock signal at the base station to synchronize the local clock signal at the base station with the reference clock signal.

Abstract: A mechanism for controlling asynchronous clock domains to perform synchronous operations is provided. With the mechanism, when a synchronous operation is to be performed on a chip, the latches of the functional elements of the chip are controlled by a synchronous clock so that the latches are controlled synchronously even across asynchronous boundaries of the chip. The synchronous operation may then be performed and the chip's functional elements returned to being controlled by a local clock in an asynchronous manner after completion of the synchronous operation. This synchronous operation may be, for example, a power on reset (POR) operation, a manufacturing test sequence, debug operation, or the like.

Abstract: The present invention discloses a device and method for implementing a transparent clock. The device comprises: a clock module, a data identification module and a data correction module, wherein the clock module is connected with the data identification module and the data correction module respectively, and used for providing clock information to the data identification module and the data correction module; the data identification module is used for receiving data and acquiring current time information from the clock module; and the data correction module is connected with the data identification module, and is used for accumulating a positive or negative value of the current time information with the time information included in the data according to an outputting direction of the data and outputting the accumulated time information together with the data.