Abstract: The present invention discloses a device and method for implementing a transparent clock. The device comprises: a clock module, a data identification module and a data correction module, wherein the clock module is connected with the data identification module and the data correction module respectively, and used for providing clock information to the data identification module and the data correction module; the data identification module is used for receiving data and acquiring current time information from the clock module; and the data correction module is connected with the data identification module, and is used for accumulating a positive or negative value of the current time information with the time information included in the data according to an outputting direction of the data and outputting the accumulated time information together with the data.

Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to share an oscillator as so to perform two-stage clock frequency resolution calibrations for generating different frequency-tuning ranges. This can bring an optimal frequency resolution and greatly reduce system complexity and save element cost.

Abstract: Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information provided by timer facilities of the microprocessor is reused by sampling this information at constant intervals. Such direct derivation of the microprocessor clock frequency is a real-time method that also takes into consideration secondary effects. Examples for such secondary effects include clock frequency variations across chips due to manufacturing variations, any degradation due to performance loss by thermal, or other detrimental effects as well as any voltage changes. In the preferred embodiment of the invention, the real-time microprocessor clock frequency determination is implemented as part of the microprocessor itself. No additional service processors or other external hardware facilities are needed in order to control the microprocessor clock frequency determination function.

Abstract: The network node includes a local crystal oscillator for providing a time reference derived from the clock signal produced by the local crystal oscillator, a reset stage for resetting the network node in response to a bus reset pulse received through the network and a control means for issuing a bus reset pulse of a predetermined length substantially greater than a clock period of the clock signal of the local crystal oscillator. Further the network node includes a bus reset detector for determining a length of the received bus reset pulse based on the local time reference. The bus reset detector in the network node is also adapted to adjust the local time reference based on the determined length of the received bus reset pulse.

Abstract: To ensure that a memory device operates in self-refresh mode, the memory controller includes (1) a normal-mode output buffer for driving a clock enable signal CKE onto the memory device's CKE input and (2) a power island for driving a clock enable signal CKE_prime onto that same input. To power down the memory controller, the normal-mode output buffer drives signal CKE low, then the power island drives signal CKE_prime low, then the memory controller (except for the power island) is powered down. The power island continues to drive the memory device's CKE input low to ensure that the memory device stays in self-refresh mode while the memory controller is powered substantially off. To resume normal operations, the power module powers up the memory controller, then the normal-mode output buffer drives signal CKE low, then the power island is disabled, then the memory controller resumes normal operations of the memory device.

Abstract: An interchangeable lens that can be detachably fitted to a camera body includes: a clock signal reception unit that receives a clock signal outputted from the camera body; a control command reception unit that receives a control command and data signal from the camera body, the control command and data signal being in synchrony with the clock signal, specifying a control command for the interchangeable lens and including type data specifying a type of the control command; a response generation unit that generates a response data signal including the type data on the basis of the control command and data signal; and a response transmission unit that transmits the response data signal to the camera body in synchrony with the clock signal received by the clock signal reception unit when a control command and data signal is received from the camera body in a next communication cycle.

Abstract: The present invention extends to methods, systems, and computer program products for using pulses to control work ingress. Generally, embodiments of the invention use a variable-speed clock for accepting work for lower-priority services. A clock rate is controlled by a load monitor. The load monitor periodically collects sensor measurements of resources available after allocations by higher-priority services. Based on the sensor measurements, the load monitor adjusts the clock speed up or down (i.e., depending on the amount of resources available after allocations by higher-priority services). At the boundary of the lower-priority service (e.g., where work enters the system), work requests are enqueued to be associated with a future pulse of the clock. Work is accepted or rejected based on a determination of whether the work request can be allocated a clock pulse within a defined period of time.

Abstract: Semiconductor devices are disclosed providing synchronization circuits for synchronized signal distribution for a plurality of devices in a semiconductor device. The synchronization apparatus includes an independent synchronization circuit and a dependent synchronization circuit. The independent synchronization circuit may be configured to receive a source signal and to generate a first destination signal substantially synchronized with the source signal. The dependent synchronization circuit may be coupled to the independent synchronization circuit and configured to receive the source signal and to generate a second destination signal substantially synchronized with the source signal.

Abstract: In a system for distributing data, distribution device is configured to distribute timestamp, offset and source location information for a digital data stream to an execution device, and the execution device is configured to seek digital data corresponding to the received information. The execution device is further configured to execute the digital data relative to a clock rate maintained by the distribution device. Related methods include receiving timestamp, offset and source location information for the digital data stream and seeking digital data corresponding to the received offset and source location information.

Abstract: A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.

Abstract: Systems and methods are disclosed herein to provide channel-to-channel skew control in accordance with one or more embodiments of the present invention. For example in accordance with an embodiment, a method of adjusting skew between first and second channels includes receiving a first channel output signal and a second channel output signal from the first and second channels, respectively; detecting a phase difference between the first channel output signal and the second channel output signal; and controlling, based on the detected phase difference, a signal delay within at least the first channel or the second channel to reduce skew between the first channel output signal and the second channel output signal.

Abstract: A method for expanding input/output in an embedded system is described in which no additional strobes or enable lines are necessary from the host controller. By controlling the transitions of the signal levels in a specific way when controlling two existing data or select lines, an expansion input and/or output device can generate a strobe and/or enable signal internally. This internal strobe and/or enable signal is then used to store output data or enable input data. The host controller typically utilizes software or firmware to control the data transitions, but no additional wires are needed, and no changes are needed to existing peripheral devices. Thus, an existing system can be expanded when there are no additional control lines available and no unused states in existing signals.

Abstract: The circuit, typically a delay-locked loop, comprises a phase detector, a first counter, a second counter, and a comparator. The phase detector compares a phase of a first clock signal with a phase of a second clock signal. The first counter generates first count signals and adjusts the first count signals when the phase detector indicates that the phases of the first and the second clock signals are out of alignment. The second counter generates second count signals. The first comparator generates a first comparison signal in response to a comparison between the first count signals and the second count signals. The second clock signal is generated in response to the first comparison signal.

Abstract: A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C1 and a second clock domain operating at a second clock frequency C2. In accordance with this invention, data are transmitted from the first domain, through the interfacing circuitry, and to the second domain. Also, the interfacing circuitry includes a synchronization section that operates at a third frequency C3, which, in one embodiment, is greater than and a whole number multiple of C2. Preferably, C3 is an even whole number multiple of C2. In the preferred embodiment, a clock signal A is used to operate the second clock domain at frequency C2, and a clock signal B is used to operate the synchronization section of the interfacing circuitry at frequency C3, and clock signals A and B are source synchronized.

Abstract: An electronic device is provided for generating or utilizing one or more cycle-swallowed clock signals derived based on one or more first clock signals. The device includes a module configured to receive a first clock signal having a first frequency. The module is configured to generate a second clock signal having a second frequency and configured to swallow one or more clock cycles of the first clock signal in generating the second clock signal. The first clock signal has even cycles, and the second clock signal has uneven cycles. The first frequency is greater than the second frequency. The module may include a cycle-swallowing counter. A method and a computer-readable medium are also provided.

Abstract: A non-volatile memory device is disclosed. The non-volatile memory device includes a bank configured to include a plurality of unit cells so as to output sensed data to a global input/output (I/O) line, and a data input/output (I/O) unit configured to store the same data as that of a unit cell contained in the bank in a register, store external input data in the register during a write operation, and output data stored in the register to an external part during a read operation.

Abstract: In a semiconductor LSI that sequentially performs predetermined processing on data input successively, a host CPU, a plurality of sequencers, and a data engine are connected in a hierarchical manner with the host CPU at top and the data engine at bottom. Each sequencer includes a memory that stores a parameter for execution of the sequencer, a memory controller, a loop counter, a sequence controller, and an interface unit that handles transmission and reception of signals with an external unit of the sequencer. The interface units of the plurality of sequencers have the same specifications.

Abstract: There is provided a method for operating a basic input/output system (BIOS) of a pay-as-you go computer system. In one example embodiment, the method includes periodically resetting a watchdog timer, wherein failure to reset the watchdog timer indicates a security violation. In another example embodiment, the method also includes comparing a first time count representing motherboard use time with a second time count representing hard drive use time to determine if a security violation has occurred. There is also provided a pay-as-you-go computer system having a BIOS configured to determine if a hard drive is password protected. In an example embodiment, the BIOS is configured to calculate a password to unlock the hard drive if the hard drive is password protected.

Abstract: Systems and methods for transferring data using a ring bus architecture in a system that implements multi-phase clocking. In one embodiment, the system is a multiprocessor having multiple processor cores coupled to the ring bus. The bus may be a bidirectional bus having a first data path on which data is transferred in a clockwise direction and a second data path on which data is transferred in a counterclockwise direction. Controllers within the processor cores provide phase-shifted signals to the latches to clock data into them. Data transfers on the bus may be controlled by an arbiter which is coupled to the processor cores' controllers. The arbiter may schedule data transfers on the bus based on data transfer speeds associated with left-to-right and right-to-left data transfer directions. The arbiter may cause the phases of the clock signals to be selectively varied, or may cause the clock signals to be gated.

Abstract: In one embodiment, a clock distribution chip includes a clock input adapted to receive an input clock signal, clock dividers each adapted to receive a clock signal based on the first input clock signal and to generate a divided clock signal, and programmable clock outputs adapted to provide output clock signals. The clock outputs are configurable to support a number of signaling standards. A programmable switch fabric is coupled between the clock dividers and the clock outputs and is configurable to provide the divided clock signals to the clock outputs.

Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

Abstract: A memory controller performs a read test for each of a plurality of memory devices to generate a read delay time of each memory device. There is a prime memory device and a subset of memory devices. For each memory device of the subset, the read delay time for the prime memory device is compared with the read delay time of each memory device of the subset of memory devices to generate a differential delay for each memory device of the subset. For each subset memory device, a write test start time of the prime memory device is combined with a differential delay of each memory device to generate a write test start time for the each memory device. A write test for each memory device uses the write test start time for each subset memory device to generate a write launch time for each subset memory device.

Abstract: A method for optimizing operation which is applicable to a multiprocessor integrated circuit chip. Each processor runs with a variable parameter, for example its clock frequency, and the optimization includes determination, in real time, of a characteristic data value associated with the processor (temperature, consumption, latency), transfer of the characteristic data to the other processors, calculation by each processor of various values of an optimization function depending on the characteristic data value of the block, on the characteristic data values of the other blocks, and on the variable parameter, the function being calculated for the current value of this parameter and for other possible values, selection, from among the various parameter values, of that which yields the best value for the optimization function, and application of this variable parameter to the processor for the remainder of the execution of the task.

Abstract: In a premises gateway device that performs encryption or decryption under the IPsec, the throughput of a processor is varied depending on a type of data to be treated in order to realize reduction in power consumption. In the premises gateway device to which a telephone, PCs, and a home appliance that are pieces of home network equipment are connected and which transmits or receives data using an ISP and an IPsec tunnel via an ONU, an OLT, and a carrier network, relevant home network equipment and a data rate are decided based on the data to be treated. The frequency of a clock to be fed to the processor is varied depending on the information.

Abstract: In one embodiment, a clock distribution chip includes a first clock input adapted to receive a first single-ended input clock signal, a second clock input adapted to receive a second single-ended input clock signal, and input buffer circuitry coupled to the first and second clock inputs. The input buffer circuitry is adapted to select an input clock signal among the first single-ended input clock signal, the second single-ended input clock signal, and a differential input clock signal derived from the first and second single-ended input clock signals. A phase-locked loop (PLL) is adapted to receive an input clock signal selected by the input buffer circuitry and to generate a PLL clock signal based on the selected input clock signal. A clock output provides an output clock signal based on the PLL clock signal.

Abstract: A digital data register is disclosed that provides setup and hold timing on the pre-register side, clock centering on the post-register side, and constant propagation delay time over variations in process, supply voltage and temperature (PVT) using a novel means to generate and distribute the clock signal. These features allow the register to be used in applications operating at clock frequencies in excess of 800 MHz.

Abstract: A method of providing or transporting a timing signal between a number of circuits, electrical or optical, where each circuit is fed by a node. The nodes forward timing signals between each other, and at least one node is adapted to not transmit a timing signal before having received a timing signal from at least two nodes. In this manner, the direction of the timing skew between nodes and circuits is known and data transport between the circuits made easier.

Abstract: A method for setting communication parameters in a plurality of communication devices includes setting communication parameters without an authentication process being performed for a second communication device in a case where a first communication device has received a request for setting communication parameters from the second communication device within a predetermined period of time from the start of setting communication parameters. The method further includes setting communication parameters after the authentication process has been performed for the second communication device in a case where the first communication device has received a request for setting communication parameters from the second communication device after the expiration of the predetermined period of time from the start of setting communication parameters.

Abstract: A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.

Abstract: A method for capturing data includes receiving a plurality of external clock signals including a first external clock signal and a second external clock signal. Each external clock signal has a first frequency, a first edge and a second edge. Data is received on one or more signal links at a second frequency that is faster than the first frequency. The data includes consecutive data with a first data signal followed by a second consecutive data signal. The consecutive data is captured at the second frequency in response to the first edges and not the second edges of the external clock signals. The first data signal is captured based on the first edge of the first external clock signal and the second consecutive data signal is captured based on the first edge of the second external clock signal.

Abstract: It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal.

Abstract: Techniques to enable voltage regulators to adjust for coming load changes are presented herein. In some embodiments, a functional block such as a microprocessor core having an associated clock signal is powered by at least one switching-type voltage regulator. When the functional block is about to require an increased level of power, the associated clock is provided to drive the at least one regulator switches overriding their normal drive signal, which has a lower frequency. Thus, the switches are driven at a higher frequency sufficiently prior to (e.g., just ahead of) the load change to reduce the amount of droop that would otherwise occur.

Abstract: A data reception apparatus includes: an oscillation circuit that multiplies or divides an oscillation signal from a CR oscillator based on a cycle setting value, and outputs a clock signal corresponding to the multiplied or divided oscillation signal; a temperature detector; a memory; a clock cycle setting element that reads the cycle setting value corresponding to the temperature from the memory, and inputs the cycle setting value into the oscillation circuit; a receiver that receives a data signal defined by the clock signal; a measurement element that measures a unit bit length of the data signal by counting the clock signal; and a correction element that corrects the cycle setting value based on a count value of the clock signal and a reference count value of a reference cycle corresponding to the unit bit length, and rewrites the cycle setting value with the corrected cycle setting value.

Abstract: In a computing system having a multi-core central processing unit (CPU) having at least two cores, it is determined that a task to be scheduled meets clock acceleration criteria such as requiring a number of threads less than or equal to a pre-defined threshold and/or having tasks that will run above a pre-determined amount of time. Thereafter, a clock speed of a first core of the CPU is increased and a clock speed of a second core of the CPU is decreased. Once the clock speeds have been adjusted, the task is scheduled to be executed by the first core. Related apparatus, systems, techniques and articles are also described.

Abstract: A performance control technique for a processing system that includes one or more adaptively-clocked processor cores provides improved performance/power characteristics. An outer feedback loop adjusts the power supply voltage(s) provided to the power supply voltage domain(s) powering the core(s), which may be on a per-core basis or include multiple cores per voltage domain. The outer feedback loop operates to ensure that each core is meeting specified performance, while the cores also include an inner feedback loop that adjusts their processor clock or other performance control mechanism to maximize performance under present operating conditions and within a margin of safety. The performance of each core is measured and compared to a target performance. If the target performance is not met for each core in a voltage domain, the voltage is raised for the voltage domain until all cores meet the target performance.

Abstract: The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links.

Abstract: The inter-clock domain data transfer FIFO circuit provides a circuit that transfers data between two clock domains of unrelated frequencies. The gate count is kept relatively low, thereby allowing data transfer between the two clock domains at one data item per cycle of the lower of the two frequencies. Depending on the frequency difference between the data producer and consumer, the initial latency could be as low as a fraction of a cycle and no more than two cycles of the consumer's clock. The operation of the data transfer FIFO circuit has been verified using gate-level simulations for several ratios of clock frequencies.

Abstract: System refresh in a cache memory includes generating a refresh time period (RTIM) pulse at a centralized refresh controller of the cache memory, activating a refresh request at the centralized refresh controller in response to generating the RTIM pulse, the refresh request associated with a single cache memory bank of the cache memory, receiving a refresh grant in response to activating the refresh request, and transmitting the refresh grant to a bank controller, the bank controller associated, and localized, at the single cache memory bank of the cache memory.

Abstract: A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal. Data pertaining to operating characteristics of the VRM or power supply may be one or both of two forms. In one form, this data is determined a priori from simulations or experiments made on a particular VRM or power supply unit and used to generate and store parameters that are known to optimally (quickly and without degradation of VRM or power supply performance) change the frequency of the clock processing circuit.

Abstract: A virtual machine monitor, a virtual machine system and a clock distribution method thereof. The clock distribution method includes: distributing real clock resource to a Guest Operation System (GOS), and saving correspondence between said GOS and said real clock resource; intercepting an access operation of said GOS to a virtual clock resource; sending said access operation to the corresponding real clock resource according to said correspondence, and then performing a write operation, or injecting an interrupt of said real clock resource into a local Advanced Programmable Interrupt Controllers (APIC) of a virtual CPU of the corresponding GOS of said GOSs.

Abstract: A microcode configurable frequency clock that may be used to control the speed of high speed comparison in an operational optical transceiver. The frequency clock includes a memory and a logic circuit. The memory receives microcode generated data relating to the desired speed of comparison. The logic circuit is configured to receive an input clock signal and to produce an output clock signal by frequency dividing the input signal based on the microcode generated data. The output clock is used to control the speed of comparison in the optical transceiver.

Abstract: A variable latency interface and method for managing variable latency. An apparatus includes a storage device controller and a read/write channel coupled to the storage device controller by a variable latency interface. The variable latency interface includes a media control component configured for read and write operations. The variable latency interface also includes a data transfer component configured for read and write operations. A read or write operation in the media control component is offset from a respective read or write operation in the data transfer component by a latency period.

Abstract: A memory sharing system includes a master control device, a slave control device and a memory device. The master control device selectively generates a clock signal to the memory device. The slave control device receives and tracks the clock signal via a delay phase locked loop (DLL) to generate and align an output signal with the clock signal. The master control device arbitrates an access right.

Abstract: An embodiment of the invention relates to a clock signal generator and a related method to produce a clock signal that is a rational but non-integer submultiple of a reference clock signal by employing a dithered pulse signal and a fractional phase signal. The rational submultiple includes an integer part and a fractional part, the fractional part including a numerator and a denominator. A dithered pulse generator is configured to produce the dithered pulse signal from a count of the reference clock signal that is reset dependent on the integer part, and a fractional phase signal from a count that is incremented by the numerator and that is reset dependent on the denominator. A phase controller is configured to delay the dithered pulse with a delay proportional to the fractional phase to produce the output clock signal. The delay may be calibrated by internal logic.

Abstract: Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed.

Abstract: A design structure embodied in a non-transitory machine readable medium used in a design process includes an apparatus for implementing speculative clock gating of digital logic circuits, including operation valid logic configured to generate, in a first pipeline stage n, a valid control signal input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and speculative valid logic configured to generate, in the first pipeline stage, a speculative valid control signal used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly to the first register.

Abstract: A memory interface system can include a memory controller configured to operate at a first operating frequency. A physical interface block can be coupled to the memory controller. The physical interface block can be configured to communicate with the memory controller at the first operating frequency and communicate with a memory device at a second operating frequency that is independent of the first operating frequency.

Abstract: A memory controller includes first and second output modules for driving first and second data, respectively, to be written to a memory device. The memory controller also includes a clock module for providing an internal clock signal and a timing control module for producing a first and second timing control signals. The first and second timing control signals are supplied to the first and second output modules, respectively.

Abstract: Computer software that manages the amount of power provided to a processing unit for a specific process task, optimizing the processing speed of that specific task without overheating the processing unit. In the optimization method, the software initially counts the number of operations completed during an initial subtask duration for the current process task, then recounts the number of operations completed during a repeat subtask duration when the voltage to the processing unit was increased incrementally based on its die size. The software then determines whether to (a) repeat such steps until the operations count stops increasing (and save the completed-operations count of that subtask duration), or (b) whenever the temperature of the processing unit exceeds a failsafe temperature, save the completed-operations count of the immediately preceding subtask duration. The task may be processed continuously at that optimized performance level and power level.

Abstract: Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.