Abstract: A decoding apparatus has an on-chip buffer, an external buffer interface, and a turbo decoder. The on-chip buffer is arranged for buffering each code block to be decoded. The external buffer interface is arranged for accessing an off-chip buffer. The turbo decoder is arranged for decoding a specific code block read from the on-chip buffer. The specific code block is not transmitted from the on-chip buffer to the off-chip buffer via the external buffer interface unless decoding fail of the specific code block is identified.

Abstract: A flash memory controller includes a read/write unit, a state machine, a processing unit, and an auxiliary unit. The read/write unit is connected to a flash memory and performs a writing command or a reading command. The state machine is configured to determine a state of the flash memory controller. The processing unit is connected to the read/write unit and the state machine and configured to control the read/write unit. The auxiliary unit is connected to a first data line and a second data line and the processing unit and configured to receive and store a string output from the processing unit. The auxiliary unit outputs the string through the first and second data lines when the flash memory controller completes a writing data transmission.

Abstract: A check node processing unit updates an extrinsic value ratio based on a prior value ratio for each row of a parity check matrix with respect to input data. An identifying unit identifies, based on an element of the parity check matrix that can be identified by a row and column associated with the updated extrinsic value ratio, a next-target element in the same column and in a different row. The identifying unit identifies an element to be updated in the next step by the check node processing unit, from among multiple elements included in the same column. A variable node processing unit updates, based on the extrinsic value ratio, a prior value ratio associated with the identified next-target element after the check node processing unit completes the updating of each row. The check node processing unit and the variable node processing unit alternately and iteratively execute their operations.

Abstract: According to exemplary embodiments, a system, is provided for bit error rate (BER)-based wear leveling in a solid state drive (SSD). A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.

Abstract: Methods and systems for validating positions reported in AIS message signals by fitting suitably chosen functions to signal characteristic data, such as timing and Doppler shift data, derived from a plurality of AIS message signals. Ships whose reported positions deviate from the fitted function may be flagged as suspect.

Abstract: A method of transmitting data over a network, from a sending application to a receiving application, including: coding the data, by the sending application, by implementing a predefined rule; detecting alteration of at least one item of data transmitted, by the receiving application, by implementing the predefined rule; and in case an alteration of a data item is detected, restoring the altered data item. In the course of the coding, in the course of the alteration detection, and in the course of the restoration, a cyclic redundancy check or an encryption can be implemented.

Abstract: A method for improving address integrity in a memory system generates error correction data corresponding to a memory address. The error correction data is transmitted to a memory device over an address bus coincident with transmitting a no-operation instruction over a command bus.

Abstract: Data and a corresponding initial error correction code is written to a first portion of a memory device. Based on an error in the first data and the initial error correction code, the initial error correction code is modified.

Abstract: In one embodiment, a first set of digital data (e.g., an image) is tested for the presence of a certain feature (e.g., a certain face), yielding one of two outcomes (e.g., not-present, or present). If the testing yields the first outcome, no additional testing is performed. If, however, the testing yields the second outcome, further testing is performed to further check this outcome. Such further testing is performed on a second set of digital data that is based on, but different from, the first set of data. Only if the original testing and the further testing both yield the same second outcome is it treated as a valid result. A variety of other features and arrangements are also detailed.

Abstract: The apparatus, systems, and methods described herein may operate to encode a first part of a message into an index, and to encode a second part of the message into a sequence of matrices such that at least one of row spaces or rank of the matrices is determined by the index. Additional apparatus, systems, and methods are described.

Abstract: Various systems and methods for media defect detection.

Abstract: Methods and apparatus for detection and handling of virtual appliance failures. In one aspect, a method is implemented on a host platform on which a hypervisor (aka Virtual Machine Manager) and a plurality of virtual machines (VMs) are running, the plurality of VMs collectively hosting a plurality of Software Defined Networking (SDN) and/or Network Function Virtualization (NFV) appliances that are communicatively coupled via a virtual network. A software-based entity running on the host platform is configured to monitor the plurality of virtual network appliances to detect failures of the virtual network appliances. In response to detection of a virtual network appliance failure, messages containing configuration information are implemented to reconfigure packet flows to bypass the virtual network appliance that has failed.

Abstract: Embodiments of decoding data stored in solid-state memory arrays are disclosed. In one embodiment, multiple read operations are performed while taking inter-cell interference (ICI) into account. Soft-decision information, such as log-likelihood ratios (LLRs), is determined by using known data and its corresponding multi-read output. Soft-decision information is provided to a detector. Reliability is improved and performance is increased.

Abstract: One or more out-of-band input signals (GPIO) are handled and efficiently embedded into a USB capture stream. In order to conserve resources, the state of the input signals can be sent only when a change occurs. The signals are accurately time-stamped, and then presented within the context of the captured USB data. In order to provide maximum visibility, if the digital inputs occur during a normally filtered multi-packet sequence, the filter is canceled and the surrounding packets will also be sent to an analysis computer. Furthermore, because digital inputs may happen during a USB packet, the digital inputs are queued in a FIFO buffer until there is an opportunity to send the digital inputs. Even though the state of the inputs may be sent at a later time, the state of the inputs may be time-stamped when the state of the inputs is perceived by the analyzer.

Abstract: A method includes generating an encoded data block, dividing the encoded data block into a plurality of sub-blocks, and transmitting the plurality of sub-blocks over a plurality of physical medium attachments. The encoded data block may be generated using 64B/66B encoding, and the data being encoded could first be decoded using 8B/10B decoding. Another method includes receiving a plurality of sub-blocks over a plurality of physical medium attachments, generating an encoded data block using the plurality of sub-blocks, and recovering data encoded in the encoded data block. The data may be recovered from the encoded data block using 64B/66B decoding, and the recovered data may be subsequently encoded using 8B/10B encoding. Each physical medium attachment may be capable of serializing data for transmission over a physical transmission medium (such as printed circuit board tracks or lanes) and deserializing data received over the physical transmission medium.

Abstract: A method for decoding comprises the following steps: receiving a first codeword comprising a plurality of elements of a first finite commutative group and associated to a plurality of symbols in accordance with a first code defining codeword elements by respective summations in said first commutative group; determining, by applying a projection onto elements of the first codeword, a second codeword comprising a plurality of elements of a second finite commutative group having a cardinal strictly smaller than the cardinal of the first finite commutative group, wherein the projection is a morphism from the first finite commutative group to the second finite commutative group; decoding the second codeword in accordance with a second code defining codeword elements by respective summations in said second commutative group.

Abstract: A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set.

Abstract: The disclosure is related to systems and methods for servo Gray code error detection and correction. A device may include a circuit configured to 1) selectively implement a quality-based error correction system to determine an error in the servo Gray code and correct the error; 2) selectively implement a trajectory-based error correction system to determine an error in the servo Gray code and correct the error; or 3) implement any combination of a quality-based error correction system and a trajectory-based error correction system to determine an error in the servo Gray code and correct the error.

Abstract: A method includes a DSN access token module retrieving one or more sets of at least a threshold number of dispersed storage (DS) error coding function slices from the DSN memory via the computing device. The method continues with the computing device and/or the DSN access token module decoding the one or more sets of the at least a threshold number of DS error coding function slices using a default DS error coding function to recapture a DS error coding function. The method continues with the computing device and/or the DSN access token module generating a plurality of sets of data access requests in accordance with the DS error coding function. The method continues with the computing device sending the plurality of sets of data access requests to the DSN memory.

Abstract: An apparatus for comparing pairs of binary words includes an intermediate value determiner and an error detector. The intermediate value determiner determines an intermediate binary word so that the intermediate binary word is equal to a reference binary word for a first pair of equal or inverted binary words, so that the intermediate binary word is equal to the inverted reference binary word for a second pair of equal or inverted binary words and so that the intermediate binary word is unequal to the reference binary word and the inverted reference binary word for a pair of unequal and uninverted binary words, if the intermediate value determiner works faultlessly. Further, the error detector provides an error signal based on the intermediate binary word so that the error signal indicates whether or not the binary words of a pair of binary words are equal or inverted.

Abstract: The invention relates to an automated system in which a targeted search may be made for connecting terminals without having to actuate a load connected thereto. For this purpose, the automated system has a communication network, a programmable control unit, and at least one modular bus subscriber which are connected to the communication network. The modular bus subscriber has multiple groups of connecting elements, a display element being associated with each group of connecting elements. An evaluation and control unit is also provided which actuates at least one selected display element in response to signaling information originating from the programmable control unit. The programmable control unit is designed to provide this type of signaling information.

Abstract: A receiver can include a sampler module for sampling a data-bearing input signal to extract data encoded in the data-bearing analog input signal. The sampling results in data-symbol sequences. The data-symbol sequences can be used to identify error events. The identified error events can be used as a basis for adjusting tap coefficients. The tap coefficients can be used in setting reference levels for the sampler module.

Abstract: A communication system having a main control portion (MCP) to transmit information destined to a device n cascade levels down, and create an error detection code (CRC code) for data that contains a count of remaining cascade levels until an n-th cascade level and the information. The code is transmitted to an upstream sub-control portion (USCP) with the data. The USCP creates a CRC code for the data, and compares the created and received codes. For a match, the USCP determines whether the information is destined to itself based on the remaining cascade level count. When the information is not so destined, the USCP creates new data with the remaining cascade level count reduced by 1, and a CRC code for the new data, and transmits the created code to a further device, with the new data.

Abstract: A load balancing method and device are provided by the present invention. The method includes that: for each base station, determining the number of shared mobile hosts shared by the base station with each neighbor base station of the base station and the number of fixed mobile hosts covered only by the base station; ranking all of base stations in an ascending order of the number of fixed mobile hosts; and balancing the number of fixed mobile hosts of each base station by applying a greedy algorithm on the ranked base stations. With the present invention, the load can be efficiently balanced by exploiting the global knowledge.

Abstract: A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component.

Abstract: Subject matter disclosed herein relates to memory management, and more particularly to partitioning a memory based on memory attributes.

Abstract: A method begins by a dispersed storage (DS) processing module updating an encoded data slice of a set of encoded data slices to produce an updated encoded data slice and sending the updated encoded data slice to a first DS unit of a set of DS units. The method continues with the first DS unit storing the updated encoded data slice and generating partial error recovery information to produce a collection of partial error recovery information. The method continues with the first DS unit outputting the collection of partial error recovery information for storage in at least some of the set of DS units. The method continues with one of the at least some of the set of DS units updating error recovery information of an encoded data slice based on a corresponding one of the collection of partial error recovery information.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.

Abstract: Embodiments of the inventions are related to systems and methods for data processing, and more particularly to systems and methods for mitigating trapping sets in a data processing system.

Abstract: Bin identification information for a cell is generated. An estimation function is received where the estimation function trends toward a maximum soft read value at a first end and trends toward a minimum soft read value at a second end. A soft read value is determined for the cell based at least in part on the bin identification information and the estimation function.

Abstract: A method and apparatus for in-line processing a data packet while routing the packet through a router in a system transmitting data packets between a source and a destination over a network including the router. The method includes receiving the data packet and pre-processing layer header data for the data packet as the data packet is received and prior to transferring any portion of the data packet to packet memory. The data packet is thereafter stored in the packet memory. A routing through the router is determined including a next hop index describing the next connection in the network. The data packet is retrieved from the packet memory and a new layer header for the data packet is constructed from the next hop index while the data packet is being retrieved from memory. The new layer header is coupled to the data packet prior to transfer from the router.

Abstract: A method for data storage includes receiving in a memory device data for storage in a group of analog memory cells. The data is stored in the group by performing a Program and Verify (P&V) process, which applies to the memory cells in the group a sequence of programming pulses and compares respective analog values of the memory cells in the group to respective verification thresholds. Immediately following successful completion of the P&V process, a mismatch between the stored data and the received data is detected in the memory device. An error in storage of the data is reported responsively to the mismatch.

Abstract: Exemplary receiving apparatus receives serial data that includes contiguous blocks each having M-bit known pattern. The apparatus includes a serial-parallel conversion circuit that arranges bits in the serial data to generates N-bit wide (N<M) parallel data, a register group including a first register that stores a word of the parallel data and second registers to which the word of the parallel data is sequentially shifted and stored, a comparing circuit that compares the known pattern with storage patterns each including M contiguous bits stored in the register group, and a detecting circuit. The detecting circuit detects reception of the serial data if the comparing circuit detects a first match between the known pattern and a first one of the storage patterns, and a second match between the known pattern and a second one of the storage patterns that starts with a specific bit during a specific clock cycle.

Abstract: The present invention is related to systems and methods for harmonizing testing and using a storage media. As an example, a data system is set forth that includes: a data decoder circuit, a data processing circuit, and a write circuit. The data decoder circuit is configured to decode a test data set to yield a result. The data processing circuit is configured to encode a user data set guided by the result to yield a codeword. The write circuit is configured to store an information set corresponding to the codeword to a storage medium.

Abstract: An analog front end is adjusted by determining a signal quality based at least in part on digital sample(s). If the signal quality satisfies one or more criteria, a data independent gain gradient and a data independent offset gradient are selected to adjust the analog front end, where the two gradients are generated without taking into consideration an instantaneous value of an expected signal. If the signal quality does not satisfy the criteria, a decision directed gain gradient and a decision directed offset gradient are selected to adjust the analog front end, where the two gradients are generated based at least in part on decision(s).

Abstract: In one embodiment, the present invention includes a host controller with transmit logic to prepare data into a data packet for communication along an interconnect and to transmit the data packet. This data packet may include a preamble portion having a first predetermined value, a content portion including the data and having a plurality of symbols each including a start bit separate from the data, an error detection portion including an inverted version of the content portion, and a postamble portion having a second predetermined value. Other embodiments are described and claimed.

Abstract: A data storage system configured to efficiently search and update system data is disclosed. In one embodiment, the data storage system can attempt to correct errors in retrieved data configured to index system data. Metadata stored along with user data in a memory location can be configured to indicate a logical address associated in a logical-to-physical location mapping with a physical address at which user data and metadata are stored. The data storage system can generate modified versions of logical address indicated by the metadata and determine whether such modified versions match the physical address in the logical-to-physical mapping. Modified versions of the logical address can be generated by flipping one or more bits in the logical address indicated by the metadata. Efficiency can be increased and improved performance can be attained.

Abstract: One or more locations in a plurality of data bit sequences that do not satisfy parity and are associated with data bit sequences that are unable to be successfully error correction decoded are determined. Soft information associated with the determined locations is modified and error correction decoding using the modified soft information is performed.

Abstract: Error correction coding for streaming communication is provided. A streaming problem is modeled as a non-multicast network problem with a nested receiver structure. Each packet in the streaming problem corresponds to a link, and each deadline in the streaming problem corresponds to a receiver in the non-multicast network problem. For the non-multicast network problem, content to be transmitted in multiple packets to multiple receivers is obtained. Each of the receivers is required to decode specific independent messages from the content, at given time steps, and has access to a subset of the content received by another receiver. The content is allocated into multiple packets to be transmitted on multiple links. No coding occurs across information demanded by different receivers. A capacity region defines a set of information rate vectors that can be communicated to the receivers successfully. A rate vector is successfully communicated if it complies with various inequalities.

Abstract: A method of detecting errors in road characteristics in a transportation network database includes collecting sequential location measurements from probes traversing between two end points, fitting trace segments having a curved or linear shape between the sequential location measurements collected from the probes to form a probe trace, comparing a position of the probe traces with a position of a calculated path between the two end points, where the calculated path is formed from linked transportation network segments each of the linked transportation segments having a curved or linear shape, where the calculated path follows the road characteristics defined by the attributes associated with the linked transportation segments, and identifying a potential error in the attributes if a probe trace deviating in position from the calculated path is greater than a deviation threshold.

Abstract: A method for data storage in a memory including multiple memory cells arranged in blocks, includes storing first and second pages in respective first and second groups of the memory cells within a given block of the memory. A pattern of respective positions of one or more defective memory cells is identified in the first group. The second page is recovered by applying the pattern identified in the first group to the second group of the memory cells.

Abstract: A block CRC based fast data hash provides efficient data integrity verification functions. A hash word is generated from block CRCs that are stored along with data blocks in a hard drive for each data and/or parity track of a storage system, such as a RAID array. Each storage system member writes the hash word into a global memory. Thereafter, a director verifies data integrity using all member's hash words with one or more XOR operations. Use of the hash words for data integrity verification saves system bandwidth and CPU processing resources.

Abstract: A low-density parity check (LDPC) code decoding method may be provided. The LDPC code decoding method may linearize or perform step-approximation on a natural logarithm hyperbolic cosine function included in a check node updating equation of a sum-product algorithm used for decoding an LDPC code, and may convert the linearized function to correspond to a check node updating equation of a min-sum algorithm.

Abstract: A storage apparatus for controlling a storage unit includes a cache memory for temporarily storing data to be stored in the storage unit, and a processor for executing a process including receiving unit data which is divided from data to be migrated, calculating first checksum data from the received unit data, storing the unit data and the first checksum data to the cache memory, reading out the stored unit data and the first checksum data from the cache memory, calculating second checksum data from the read out unit data, storing the unit data to the storage unit, and determining whether data migration has been performed properly by comparing the first checksum data to the second checksum data.

Abstract: An apparatus for detecting media flaws includes a branch metric selection circuit operable to select a first branch metric and a second branch metric, a subtraction circuit operable to subtract the second branch metric from the first branch metric to yield a difference, and a comparator operable to compare the difference with a threshold value and to indicate a presence of a potential flaw in a storage medium when the difference is less than the threshold value.

Abstract: An apparatus detects an error from data transmitted on a transmission path, and measures a first value indicating the number of times the number of errors detected within a first time interval becomes equal to or greater than a first threshold. The apparatus reports that a failure has been detected on the transmission path of the data, when the first value measured within a second time interval longer than the first time interval becomes equal to or greater than a second threshold.

Abstract: Systems and methods are provided for GF(q) iterative decoding. A decoder computes a plurality of R messages corresponding to a variable node of the decoder and forms decoder extrinsic information for the variable node by combining the plurality of R messages. The decoder stores the decoder extrinsic information in a memory during a first time period and retrieves the decoder extrinsic information from the memory during a second time period, the second time period occurring after the first time period. The decoder extrinsic information is provided to a soft detector.

Abstract: A transmitting apparatus included in a communication system that performs message communication using an error detection code with a receiving apparatus, the transmitting apparatus includes a transmission interval determining means that, based on a parameter related to a transmission error non-detection probability of a message per time, a data length of the message, and a code length of the error detection code used for the message, determines a transmission interval for transmitting the message, so that the transmission error non-detection probability of the message satisfies a condition related to a transmission error non-detection probability included in the parameter, wherein the message is transmitted to the receiving apparatus, based on the transmission interval determined by the transmission interval determining means.

Abstract: According to one embodiment, a host controller includes a command generator and detector. The command generator generates a command having a retransmission flag in an argument, and transmits the generated command to a memory device. The detector detects timeout if a response from the memory device cannot be recognized within a defined time. When transmitting an initial command, the host controller clears the retransmission flag and transmits the command. If the detector detects timeout, the host controller sets the retransmission flag, and retransmits the same command as the initial command to the device. If a normal response corresponding to the initial command or retransmitted command is received, the host controller recognizes that the command is correctly executed.

Abstract: Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity values of data values stored in a plurality of codewords of an NVM device. Other embodiments may be described and claimed.