Abstract: A semiconductor apparatus includes a delay circuit to apply delay to an input signal, a phase detector to detect a phase of an output signal which is outputted from the delay circuit, a filter to set a range of the phase of the output signal for stable operation based on phase information outputted from the phase detector, a counter to count a number of detections of the output signal when the phase deviates from the range for stable operation, a discount controller to generate a discount signal indicating a discount number for the number counted by the counter, in accordance with an operating condition or an external factor outside the delay circuit and an error detector to determine whether or not an error of the phase of the output signal has occurred based on the number counted by the counter and a discount number indicated by the discount signal.

Abstract: According to one aspect of the present disclosure, a method and technique for hierarchical network failure handling in a clustered node environment is disclosed. The method includes: detecting a network failure by a node in a cluster, the cluster having plural nodes arranged in a hierarchy, wherein the network failure is associated with a subordinate node in the hierarchy to the detecting node; communicating the network failure from the detecting node to a superior node in the hierarchy; determining whether the network failure affects nodes higher than the detecting node in the hierarchy; and responsive to determining that the network failure does not affect nodes higher than the detecting node in the hierarchy, the detecting node initiating a protocol to expel the subordinate node from the cluster.

Abstract: A computing system securely stores data to a dispersed data storage system. The computing system includes a processing module and a plurality of storage units. The processing module includes an encryptor and error encoder to encrypt and encode the data for dispersal utilizing a write command to the storage units. The storage units store the encrypted and encoded data when receiving the write command and the encrypted and encoded data.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The embodiments may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature checked.

Abstract: Apparatuses, systems, and methods are disclosed for reconfiguring an array of storage elements. A storage element error module is configured to determine that one or more storage elements in an array of storage elements are in error. An array of storage elements stores a first ECC block and first parity data generated from the first ECC block. A data reconfiguration module is configured to generate a second ECC block comprising at least a portion of data of a first ECC block. A new configuration storage module is configured to store a second ECC block and associated second parity data on fewer storage elements than a number of storage elements in an array.

Abstract: A method and device for determining a size of a transport block based on modulation and coding related information, and resource information.

Abstract: Techniques for wireless access point mapping are described. In at least some embodiments, various characteristics of a wireless access point are detected. Examples of such characteristics include signal strength for wireless signal transmitted by the wireless access point, identifying information for the wireless access point, data error rates for data transmitted by the wireless access point, and so forth. Characteristics of a wireless access point can be detected at multiple different geographic locations to enable a reception range mapping to be generated for the wireless access point, e.g., for an area in which signal reception for the wireless access point is qualitatively acceptable.

Abstract: Methods and apparatuses are described for formally verifying a bit-serial division circuit design or a bit-serial square-root circuit design. Some embodiments formally verify a bit-serial division circuit design using a set of properties that can be efficiently proven using a bit-level solver. In some embodiments, the set of properties that are used for verifying a bit-serial division circuit design does not include any terms that multiply a w-bit partial quotient with the divisor. Some embodiments formally verify a bit-serial square-root circuit design using a set of properties that can be efficiently proven using a bit-level solver. In some embodiments, the set of properties that are used for verifying a bit-serial square-root circuit design does not include any terms that compute a square of a w-bit partial square-root.

Abstract: Gaps in performance data are corrected for through data transformations and conversion. A raw sequence is transformed by correction logic into an interval sequence by partitioning a performance monitoring period into equal intervals and assigning values based on the raw sequence. Locality sequence entries can indicate whether the interval sequence relies on estimation. The interval sequence is converted into an absence length sequence whose entries indicate null value periods in performance data. Conversion includes generating a presence sequence from the interval sequence, and deriving the absence length sequence from the presence sequence, by using a set-based algorithm or other mechanism. Excessive absence length values support treating intervals as downtime for the machine. Correction logic may include a stored procedure residing in a database, for example, which produces the absence length sequence without using a procedural language.

Abstract: A method begins by a computing device determining that dispersed storage network (DSN) memory is to be accessed regarding data. The method continues when the computing device is paired with a DSN access token module with the DSN access token module retrieving a plurality of sets of at least a threshold number of dispersed storage (DS) error coding function slices from the DSN memory via the computing device. The method continues with at least one of the computing device and the DSN access token module decoding the plurality of sets of the at least a threshold number of DS error coding function slices using a default DS error coding function to recapture a DS error coding function and executing, by one or more of the computing device and the DSN access token module, the DS error coding function to access the DSN memory regarding the data.

Abstract: A method begins with a processing module receiving an access request for the data object. The method continues by ascertaining that the data object is divided into a plurality of data segments and that plurality of data segments are dispersed storage error encoded to produce a plurality of sets of encoded data slices. The method continues by ascertaining batching of the plurality of sets of encoded data slices, wherein the plurality of sets of encoded data slices are arranged into a set of batched encoded data slices. The method continues by outputting a set of access requests for the set of batched encoded data slices to storage units of the DSN.

Abstract: Provided herein is a method and system for providing and analyzing unified data signaling that includes setting, or analyzing a state of a single indicator signal, generating or analyzing a data pattern of a plurality of data bits, and signal, or determine, based on the state of the single indicator signal and the pattern of the plurality of data bits, that data bus inversion has been applied to the plurality of data bits or that the plurality of data bits is poisoned.

Abstract: Systems, methods, and apparatuses for error checking are disclosed. In one embodiment, an error checking system is used on a device that has a plurality of parallel data lanes as inputs. It may be desired to provide an error checking system with sufficient resolution to detect single-bit errors, determine how many bits are in error, and/or determine which bit(s) of a parallel data lane are in error. In one embodiment, the present disclosure provides for switchable error checking through the use of a multiplexor configured to select a particular data lane for error checking. This switchable error checking may provide benefits such as low cost, low power consumption, and/or low size.

Abstract: Described herein are embodiments of methods and systems for detecting communications of a first meter board by a second meter board and correlating the time and duration of the communications with metrology data gathered during that time. In accordance with one aspect, a method is provided for diagnosing metrology errors caused by communication activities of a meter board. In one embodiment, the method includes: receiving a signal, wherein the signal indicates a presence of communication activities between a first processor of a meter and another device over a network; recording a time of receipt and duration of the communication activities between the first processor of the meter and another device over the network; and correlating the time and duration of the communication activities between the first processor of the meter and another device over the network with metrology data of the meter measured at the same time and duration.

Abstract: Methods are disclosed for improving communications on feedback transmission channels, in which there is a possibility of bit errors. The basic solutions to counter those errors are: proper design of the CSI vector quantizer indexing (i.e., the bit representation of centroid indices) in order to minimize impact of index errors, use of error detection techniques to expurgate the erroneous indices and use of other methods to recover correct indices.

Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

Abstract: Various embodiments of the present inventions are related to adaptive calibration of NPFIR filters in a data detector. For example, an apparatus for calibrating a noise predictive filter is disclosed, including a data detector operable to generate detected values for data sectors and having an embedded noise predictive finite impulse response filter. The apparatus also includes a comparator operable to determine whether a quality metric for a current one of the data sectors meets a noise threshold. The apparatus also includes a filter calibration circuit operable to adapt a number of filter coefficients for the noise predictive finite impulse response filter based on the detected values for the data sectors, and to omit the detected values for the current one of the data sectors from adaptation for one of the filter coefficients if the quality metric for the current one of the data sectors does not meet the noise threshold.

Abstract: A method of transmitting data in a communication network is provided, wherein the method includes sending an error message indicating that a data packet transmitted using a cooperative transmission scheme on a first channel is not decoded correctly, and retransmitting the data packet using a second channel which is different from the first channel.

Abstract: A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.

Abstract: A system and method for providing a global pause function in a broadcast multimedia system during a pause mode including an input module having an incoming timestamp counter for providing a time-based marker value to mark when each incoming packet arrives from a tuner and an outgoing timestamp counter for providing a time-based marker value for each outgoing packet to a receiver(s), the outgoing counter being configured for controlling when to release each outgoing packet to the receiver(s). At least one global memory device is provided for storing each received packet. The input module is configured to stop the outgoing counter from incrementing in response to activation of a global pause signal for the duration of the pause mode. Data flow to all of the receiver(s) is simultaneously and automatically stopped when a pause mode is enabled.

Abstract: In one implementation, a memory device includes non-volatile memory, a memory controller communicatively coupled to the non-volatile memory over a first bus, and a host interface through which the memory controller communicates with a host device over a second bus. The memory device can also include a signal conditioner of the host interface adapted to condition signals to adjust a signal level of signals received over the second bus based on signal level data received from the host device, wherein the signal level data relates to a voltage level of signals generated by the host device to encode data transmitted across the second bus.

Abstract: Methods and memory systems are provided that can detect bit errors due to read disturbances. A main page of a flash memory in a memory system is read. A bit error in data that is read from the main page is detected and corrected. In parallel with reading the main page, a bit error is detected in data that is read from a dummy page of the flash memory.

Abstract: Various systems and methods for media defect detection.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: In one embodiment a variable barrel shifter includes a shifter operable to apply a cyclic shift to each of a number of portions of a data word, a pivot circuit operable to swap sections of the data word around at least one pivot point in the data word, a first multiplexer operable to select between an input of the variable barrel shifter or an output of the pivot circuit as an input to the shifter, a second multiplexer operable to select between the input of the variable barrel shifter or an output of the shifter as an input to the pivot circuit, and a third multiplexer operable to select between the output of the shifter or the output of the pivot circuit as an output to the variable barrel shifter.

Abstract: A source-channel combined coding method including: determining whether a channel signal-to-noise ratio (SNR) is varied or not; when it is determined that the channel SNR is varied, selecting a MODCOD suitable for the channel SNR by referring to a first table defining an SNR threshold value at which data transmission is performed without an error, for each MODCOD designating a low density parity check (LDPC) code rate and a modulation scheme; calculating a source coding rate by using an effective information bit rate of the selected MODCOD; extracting network abstraction layer (NAL) units for each layer from an inputted video frame so as to satisfy the calculated source coding rate, and packetizing the extracted NAL units; binding packets to configure a baseband (BB) frame; and LDPC coding and modulating the BB frame through the code rate and the modulation scheme which are designated by the selected MODCOD.

Abstract: A method, system and apparatus of lossy compression technique for video encoder bandwidth reduction using compression error data are disclosed. In one embodiment, a method includes storing an error data from a compression of an original reference data in an off-chip memory, accessing the error data during a motion compensation operation, and performing the motion compensation operation by applying the error data through an algorithm (e.g., determined by the method of storing the error data). The method may include generating a predicted frame in the motion compensation operation using a motion vector and an on-chip video data. In addition, the method may include determining the error data as a difference between a compressed reference data (e.g., is created by compressing the original reference data) and an original reference data (e.g., reconstructed from a prior predicted frame and a decompressed encoder data).

Abstract: Example embodiments of the present invention provide authenticated file system that provides integrity and freshness of both data and metadata more efficiently than existing systems. The architecture of example embodiments of the present invention is natural to cloud settings involving a cloud service provider and enterprise-class tenants, thereby addressing key practical considerations, including garbage collection, multiple storage tiers, multi-layer caching, and checkpointing. Example embodiments of the present invention support a combination of strong integrity protection and practicality for large (e.g., petabyte-scale), high-throughput file systems. Further, example embodiments of the present invention support proofs of retrievability (PoRs) that let the cloud prove to the tenant efficiently at any time and for arbitrary workloads that the full file system (i.e.

Abstract: A system and method for decoding data. Multi-dimensional encoded data may be received that potentially has errors. The multi-dimensional encoded data may encode each input bit in a set of input bits multiple times in multiple different dimensions to generate encoded bits. The encoded bits may be decoded in at least one of the multiple dimensions. If one or more errors are detected in a plurality of encoded bits in the at least one of the multiple dimensions, an intersection sub-set of the encoded data may be decoded that includes data encoding the same input bits encoded by the plurality of encoded bits in at least a second dimension of the multiple dimensions. The values of the input bits by decoding the intersection sub-set may be changed.

Abstract: An embodiment of the invention relates to a contactless switching system and an embodiment relates to a method for encoding same with at least one sensor and at least one signal generator, where the signal generator sends at least one data sequence and the sensor receives the data sequence. In at least one embodiment, an aim is to specify a technical teaching for encoding a contactless switching system inexpensively and in a versatile fashion. To this end, at least one embodiment of the invention proposes anchoring user-implementable encoding in the checksum of the data sequence or the checksum computation code, so that the checksum which the data sequence contains is used to check the quality of the data transmission and at the same time to implement the encoding.

Abstract: A method, apparatus and computer program product are provided herein for enabling the joint detection and decoding of uplink state flag symbols. In this regard, a method is provided that determining one or more residual error terms by jointly detecting and decoding in one or more bursts of a radio block. In some example embodiments, the one or more residual error terms are determined over a plurality of uplink state flag symbols in the one or more bursts that correspond to a plurality of available uplink state flag sequences. The method of this embodiment may also include determining a weighted error measure for each of the plurality of available uplink state flag sequences based on the one or more residual error terms. The method of this embodiment may also include determining an uplink state flag value based on the plurality of weighted error measures.

Abstract: A data processing apparatus is provided having error code generation circuitry configured to generate an error code associated with a received data value, such that a bit change in the received data value can be known about by reference to the error code. Stored data values are stored in a data store and associated error codes are stored in an error code store. Error checking circuitry performs a verification operation on a stored data value and an associated error code to determine if an error has occurred in at least one of the stored data value and the associated error code during storage. The received data value comprises at least one additional bit with respect to the stored data value and the error checking circuitry is configured to reconstruct the at least one additional bit by reference to the stored data value and the associated error code.

Abstract: An unequal error protection scheme for borehole telemetry. The scheme, when applied to imaging applications, assigns more protection for the more significant bits and less protection for less significant bits. When applied to communication using channels of different quality, more protection is provided for channels of poor quality.

Abstract: A base station allocates, when receiving a first code included in a predetermined code group from a first mobile station, a wireless resource in a first communication region corresponding to the first code, to the first mobile station, and allocates, when receiving a second code not included in the predetermined code group from a second mobile station, a wireless resource in a second communication region corresponding to the second code, to the second mobile station.

Abstract: The invention relates to a method of probabilistic symmetric encryption of a plaintext message element with the aid of a secret key that can be represented in the form of a matrix. It comprises an operation of encrypting the plaintext message element, with the aid of the matrix parametrized by a random vector, so as to obtain an encrypted message element coupled to the random vector. Furthermore, there is envisaged a step of encoding the plaintext message element as a code word with the aid of an error correcting code having a given correction capacity and a step of adding a noise vector. The error correcting code and the noise vector are adapted so that the Hamming weight of the noise vector is less than or equal to the correction capacity of the correcting code.

Abstract: Systems and methods for detecting resource leaks in a program using static analysis are disclosed. Dynamically adjustable sets of must-access paths can be employed for aliasing purposes to track resources intra- and inter-procedurally through a program. Actionable reports are also disclosed, in which resource leaks are prioritized, filtered and clustered to improve utility.

Abstract: In a system, a data receiving device comprises a timing signal generation unit that generates a timing signal used for receiving the divided transmission data in each of the transmission paths, a data receiving unit that receives the divided transmission data transmitted by the data transmitting device for each of the transmission paths by using the timing signal generated by the timing signal generation unit, and an error detection unit that extracts the error detection information from the divided transmission data received for each of the transmission paths by the data receiving unit and detects an error of transmission data included in the divided transmission data by using the extracted error detection information.

Abstract: A checksum calculation, prediction and validation system includes a host system, a network interface, a reception pipeline disposed between the host system and network interface and configured to calculate an expected full checksum related to packets received in the host system and a transmission pipeline disposed between the host system and network interface and configured calculate factors related to packets for transmission on the network interface.

Abstract: Each of (n?1) 2-bit checking units, where n is an integer larger than or equal to 4, receives n-bit redundant encoded data generated from 1-bit input data, and outputs 2-bit check data based on a result of comparison between bits of the encoded data, combinations of the bits differing in each comparison. An all-bit checking unit outputs all-bit check data based on exclusive ORs of all-bit of the encoded data. An error detecting unit detects errors in the encoded data on the basis of the (n?1) sets of 2-bit check data and the all-bit check data, and outputs the input data on the basis of the result of error detection.

Abstract: An apparatus and method for improving a HARQ combining gain in a broadband wireless communication system are provided. The apparatus includes a seed information generator and a subcarrier allocator. The seed information generator randomly generates a seed value for changing a channel of a subcarrier and an interference pattern in a frame unit when a HARQ combining gain is not generated because an interference pattern is the same during a retransmission period. The subcarrier allocator allocates a subcarrier using the generated seed value.

Abstract: Embodiments of the inventions are related to systems and methods for data processing, and more particularly to systems and methods for mitigating trapping sets in a data processing system.

Abstract: A method and device include a power pin, a ground pin, and a communications pin. A communications module receives power from the power pin and utilizes an edge counting communication protocol over the communication pin.

Abstract: A device and method for attaching a CRC code to a transport block and turbo encoding the CRC attached transport block, where the transport block has a predetermined size.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for selectable positive feedback data processing.

Abstract: A memory management method for receiving a multi channel hybrid automatic repeat request (HARQ) packet may enable smooth communication and reduce costs by maintaining a small memory size of a receiver in a communication system using a HARQ including a plurality of channels.

Abstract: The present invention is related to systems and methods for adaptive parameter modification in a data processing system.

Abstract: A centralized DVR includes a dispersed storage error encoding module, storage nodes, and a distribution module. The dispersed storage error encoding module encodes a broadcast of data in accordance with an error coding dispersal storage function to produce a plurality of sets of encoded data slices, which is stored in the storage nodes. For a first playback request, the distribution module determines a first unique combination and retrieves, as a first unique copy of the broadcast data from the storage nodes, encoded data slices of the plurality of sets of encoded data slices in accordance with the first unique combination. For a second playback request, the distribution module determines a second unique combination and retrieves, as a second unique copy of the broadcast data from the storage nodes, encoded data slices of the plurality of sets of encoded data slices in accordance with the second unique combination.

Abstract: Various embodiments of the present invention provide systems and methods for data processing using variable scaling.

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.