Abstract: The invention provides a system management apparatus for a multi-shelf modular computing system. The system management apparatus receives and parses an alert information in response to an abnormal parameter/state relative to a component of the multi-shelf modular computing system sent from a shelf management device of the multi-shelf modular computing system, and stores the parsed alert information into a storage module. Then, the system management apparatus periodically retrieves the parsed alert information, if any, from the storage module and generates a visual alert information indicating the abnormal parameter/state. Thereby, a user can view the visual alert information to perceive the abnormal parameter/state rapidly and intuitively, so as to take corresponding measures.

Abstract: When performing data descrambling for data including errors, a countermeasure against an error in a seed value that is required for the descrambling is realized in a system having no CPU. There are provided an FIFO unit (202) in which data are stored, an error correction unit (205) for receiving the data contents from the FIFO unit and performing error detection, an ID holding register (204) for holding a seed that is needed for data descrambling or information that is needed for seed generation when the data contents are judged as correct data as a result of the error detection by the error correction unit, and a descrambling unit (203) for receiving the data from the FIFO and performing descrambling by using the value stored in the ID holding register. Therefore, it is possible to perform data descrambling even in a situation where a CPU cannot manage the seed value because the transfer data are used.

Abstract: A method and apparatus are disclosed for performing maintenance operations in a system using address, data, and controls which are transported through the system, allowing for parallel and serial operations to co-exist without the parallel operations being slowed down by the serial ones. It also provides for use of common shifters, engines, and protocols as well as efficient conversion of ECC to parity and parity to ECC as needed in the system. The invention also provides for error detection and isolation, both locally and in the reported status. The invention provides for large maintenance address and data spaces (typically 64 bits address and 64 bits data per address supported).

Abstract: An integrated circuit 2 is provided with a plurality of pipeline stages 10. These pipeline stages 10 have speculative processing control circuitry 12 which permits speculative processing in downstream pipeline stages and triggers a first error recovery operation (partial pipeline flushing) if such speculative processing is determined to be based upon an error. The pipeline stage 10 further includes speculative error detecting circuitry 14 which generates a prediction nc regarding whether or not the processing circuitry 18 will produce an error. This prediction is used to trigger a second error recovery operation (partial pipeline stall). This second error recovery operation has a lower performance penalty than the first error recovery operation.

Abstract: An apparatus for correcting and detecting multiple spotty-byte errors within a byte occurred in a limited number of bytes and which has a function capable of controlling multiple spotty-byte errors within a byte occurred in the limited number of bytes, is provided. The apparatus for correcting and detecting multiple spotty-byte errors within a byte occurred in a limited number of bytes, comprises an encoding means for generating a transmitted word based on input information data; and a decoding means for inputting the transmitted word where errors occurred in an information transmission channel as a received word and correcting and detecting the errors. The encoding means generates the transmitted word by adding check information generated based on a parity check matrix expressing a spotty-byte error control code and the input information data to the input information data.

Abstract: Disclosed herein is a decoding apparatus for decoding an LDPC (Low Density Parity Check) code received in a first format or a second format wherein a process to decode received values each obtained as a result of receiving the LDPC code in the first or second format includes at least F check-node processes carried out concurrently as processes of F check nodes respectively or F variable-node processes carried out concurrently as processes of F variable nodes respectively.

Abstract: A monitoring apparatus and a monitoring method thereof are disclosed. The monitoring apparatus is used to monitor a computer. The monitoring apparatus comprises a control unit, and a first non-volatile memory unit. If the computer has an abnormal operation before loading an operating system, the control unit is used to store an error code according to the abnormal operation in the first non-volatile memory unit and execute a recovery process according to the error code.

Abstract: There is provided with a decoding apparatus for decoding a low-density parity check code defined by a parity check matrix, includes: a first operation unit configured to carry out a row operation for each row of the parity check matrix; a calculation unit configured to calculate a reliability coefficient with respect to establishment of a parity check equation defined by said each row, respectively; a second operation unit configured to carry out a column operation for said each row; and a controller configured to iteratively execute one set which includes respective processing by the first operation unit, the calculation unit and the second operation unit and omit the processing by the first operation unit and the calculation unit for a row for which the reliability coefficient has satisfied a threshold.

Abstract: The present invention relates to a method of constructing a low density Parity Check code, a method of decoding the same and a transmission system using the same. The method comprises steps of: constructing a low density Parity Check matrix of the low density Parity Check code by using a fixed pattern; blocking data sent from an information source (101), encoding the data by directly or indirectly using the constructed low density Parity Check matrix to obtain codewords of the low density Parity Check code; and outputting the codewords of the low density Parity Check code. The low density Parity Check code can be encoded by using the Parity Check matrix or a generation matrix. According to the proposed constructing method, a Parity Check matrix of a low density Parity Check code having excellent performance, a method of constructing the low density Parity Check code and a complexity-reduced decoding method can be obtained.

Abstract: There are provided a method, an apparatus and a computer program product for reducing power consumption in an iterative decoder. The apparatus includes a memory device and an iteration termination device. The memory device is for storing a bit number difference indicating a number of bits that are different between a decoded codeword for a current iteration and a decoded codeword for a previous iteration, for each iteration of the iterative decoder prior to a maximum number of iterations. The iteration termination device is for comparing the bit number difference to a pre-specified bit number difference threshold value, incrementing a confidence value when the bit number difference exceeds the pre-specified bit number difference threshold value, and terminating further iterations of the iterative decoder when the confidence value exceeds a pre-specified confidence threshold value.

Abstract: Methods and apparatus to select Tornado forward error correction parameters for delivery systems are disclosed. A disclosed example system includes a transmitter station comprising a processor to select a Tornado error correction parameter based on an error correction configuration for a file and to indicate to a receiver the selected Tornado error correction parameter, and a Tornado error correction circuit to encode the file based on the selected Tornado error correction parameter.

Abstract: The present invention discloses systems and methods for restoring data in flash memory after an operational failure. The method includes: setting bits of a data buffer in accordance with the data; programming a plurality of memory cells in accordance with the data buffer; and upon failure of the programming step, restoring the data buffer to be set in accordance with the data, wherein the restoring is based only on a present state of the data buffer and on a present state of the plurality of memory cells. A memory device includes: at least one cell; and a controller operative to store data in at least one cell by steps including those described in the method above. The system includes: a memory device that includes at least one cell; and a processor operative to store data in at least one cell by steps including those described in the method above.

Abstract: There are provided a fault processing system and method for quickly and accurately diagnosing a fault and autonomously processing the fault, based on interdependencies between various devices, networks, systems, and services in home network environments, the method including: establishing fault detection rules for detecting faults belonging to respective fault types defined for each situation by classifying faults occurring in the home network environments, fault diagnosis rules for diagnosing a fault type of a fault, and fault processing rules defining a method of solving a fault for each fault type; collecting state information of devices, networks, services, and the system in the home network environments and detecting a fault based on the fault detection rules; diagnosing the fault type of the detected fault by applying the fault diagnosis rules; and processing the detected fault based on the fault processing rules according to the diagnosed fault type.

Abstract: Under the present invention, the performances of a plurality of similarly configured nodes are monitored and compared. If one of the nodes exhibits a performance that varies from the performances of the other nodes by more than a current tolerance, an operational risk is detected. If detected, an alert can be generated and one or more corrective actions implemented to address the operational risk.

Abstract: Methods, systems and machine readable media for file system error detection and protection are described. In one aspect, an embodiment of a method includes collecting first data identifying at least one error in performing at least one of reading or writing data to a storage device and determining, through an association between the first data and file identifiers, a set of files which are effected by the at least one error. The collecting may be performed automatically as a background process. In another aspect, an embodiment of a method includes detecting at least one error in file system metadata for a storage device, the detecting being performed automatically as a background process, and storing state information automatically in response to the detecting; the state information indicates that upon next mounting of the storage device, the data processing system will automatically cause the running of a file system check of the file system metadata.

Abstract: A method and apparatus for testing mathematical programs where code coverage is exceedingly difficult to hit with random data test vectors (probability <2?64) is provided. To enable testing of the mathematical program, instructions in the mathematical program are trapped. Errors are injected through the use of any status/control flag where an error can be created and be rectified later by a reversible operation so that the result of the mathematical operation is not modified by the injected error.

Abstract: A host and a storage system each keep a shared identifier indicating a state of a system. The storage system acquires, at update of data, a data pair including data for a change through processing of the host and data before the update. The storage system relates the data pair to a shared identifier. When the host indicates an identifier, the storage system restores data using the data pair.

Abstract: The encoder chip of the present invention uses LDPC codes to encode input message data at a transmitting end, thereby generating a series of codewords. The encoder chip implements two low-density parity-check (LDPC) codes. The first LDPC code is a (4088,3360) code (4K) which is shortened from a (4095,3367) cyclic code. The second LDPC code is a quasi-cyclic (8158,7136) code (8K). The message data and the generated codewords are transmitted to a receiving end where the received codewords are decoded and checked for errors. To generate the codewords, the encoder applies a generator matrix G to the input message data. The G matrix is generated by first defining an H matrix. An H matrix is initially defined as 16×2 array of right-circulant sub-matrices. The G matrix is formed by manipulating the H matrix according to a 4-step algorithm. A randomizer and a synchronization marker are also included within the encoder.

Abstract: An LDPC encoder with a complexity that increases linearly as a function of block size is provided. They arc implementable with simple logic consisting of a repeater with an irregular repeat pattern, an interleaver, and an accumulator that performs irregular accumulations.

Abstract: In one embodiment, a processor comprises a first register file configured to store speculative register state, a second register file configured to store committed register state, a check circuit and a control unit. The first register file is protected by a first error protection scheme and the second register file is protected by a second error protection scheme. A check circuit is coupled to receive a value and corresponding one or more check bits read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed. The check circuit is configured to detect an error in the value responsive to the value and the check bits. Coupled to the check circuit, the control unit is configured to cause reexecution of the first instruction responsive to the error detected by the check circuit.

Abstract: An apparatus and method for decoding a channel code is disclosed. The method for decoding a channel code includes the steps of receiving a low density parity check (LDPC) encoded signal from a transmitting party, generating a parity check matrix by adjusting the order of rows or columns of the parity check matrix, the parity check matrix including a plurality of groups consisting of a plurality of columns, at least one of the groups including at least one row of which every element is zero (0), and iteratively decoding the received signal for each group by using the generated parity check matrix.

Abstract: A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.

Abstract: A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.

Abstract: A transmitting apparatus arranges data in matrix, calculates error correction codes in the data's column direction, arranges the calculated error correction codes in matrix having the same number of columns as the data, attaches number information corresponding to a row number to each row having data or error correction code, encapsulates, into each packet, each row having number information and data or error correction code, plus error detection code detecting one or more bit errors at least in the number information and the data or error correction code in the packet, and transmits the packet. Receiving apparatus discards received packets having detected errors using the error detection code in each packet, checks packet losses according to number information, and restores lost data using the error correction codes. An error correction method compensates for packet losses and bit errors in a packet, realizing efficient transmission with less delay by simple configuration.

Abstract: A method for handling memory defects during the POST phase and memory calibration in single processor and multiprocessor information handling systems is disclosed whereby information regarding the location of a known memory defect is utilized to optimize the performance of an information handling system. Memory defects within system memory are identified and replaced during operation with error free memory space.

Abstract: A method, system, and computer program product for reducing likelihood of data loss during performance of failovers in a high-availability system comprising a primary system and a standby system are provided. The method, system, and computer program product provide for defining a halt duration, periodically determining a halt end time, halting data modifications at the primary system responsive to failure of data replication to the standby system, resuming data modifications at the primary system responsive to a last determined halt end time being reached or data replication to the standby system resuming, and responsive to the primary system failing prior to a previously determined halt end time, determining that a failover to the standby system will not result in data loss on the standby system with respect to the primary system.

Abstract: A maintenance management system according to the present invention has an electronic device and a database server. In one embodiment of the invention, the electronic device further includes: (1) a log generating unit for collecting states of components and generating a log when a failure is detected during execution of a process; (2) a DB inquiry unit for transmitting the log to the database server and making an inquiry about whether firmware capable of solving the failure exists; and (3) an updating process unit for obtaining firmware capable of solving the failure from the database server and updating firmware in the electronic device with the obtained firmware. In addition, the database server further includes: a storing unit for storing a database having version information of firmware and failure correction information; and an inquiry responding unit for identifying when firmware for solving the failure exists.

Abstract: An error detection structure is proposed for a multilevel memory device including a plurality of memory cells each one being programmable at more than two levels ordered in a sequence, each level representing a logic value consisting of a plurality of digits, wherein the structure includes means for detecting errors in the values of a selected block of memory cells; the structure further includes means for partitioning the digits of each memory cell of the block into a first subset and a second subset, the digits of the first subset being unchanged in the values of a first and a second ending range in the sequence, the means for detecting errors only operating on the digits of the second subset of the block.

Abstract: A method for communicating data is provided that includes receiving a plurality of bits associated with a communications flow and recovering data lost from a packet by retransmitting selected subrate data for a lost sample over a specified time period. The method may further include transmitting one additional subrate for each sample. All data is generally retransmitted in a configured time interval and the additional subrate for each sample is transmitted every twenty milliseconds. In still other embodiments, the method includes skipping over any subrates that have already been transmitted within a recovery interval. In one implementation of the present invention, if any subrates had changed and had already been transmitted within the time period, there is no retransmit operation performed. If a lost packet is detected for a sample already in recovery, the time period is reset and a recovery process is initiated again.

Abstract: A method of correcting and detecting errors in a sector of data stored in a DVD format is provided. The method includes: calculating an initial error detection value for data within the sector, performing an error correction operation on the data within the sector and determining an updated, intermediate error detection value responsive to the error correction operation, using a target error detection value and one of the initial error detection value and the intermediate error detection value to determine that the sector doesn't include errors, processing an outer code to provide a set of error patterns and error locations, and determining if any of the error locations are for data within the sector and not correcting data corresponding to the error locations within the sector.

Abstract: It is proposed a method of decoding a set of symbols to be decoded, several data blocks representative of the set of symbols to be decoded being received by a decoding node of a communications network. The data blocks are encoded by means of an error correction code enabling a decoding by erasure. The decoding node performs the following steps: a first selecting step of selecting at least one of the data blocks, a first determining step of determining first erasures, a checking step of checking whether the number of the first erasures is below a given threshold. In the event of positive determining, the decoding node performs a first decoding step of decoding by erasure of the set of symbols to be decoded. If not it performs a second selecting step of selecting at least one of the data blocks, a second determining step of determining second erasures, and a second decoding step of decoding by erasure of the set of symbols to be decoded from the second erasures.

Abstract: Systems and methods are disclosed for denoising for a finite input, general output channel. In one aspect, a system is provided for processing a noisy signal formed by a noise-introducing channel in response to an error correction coded input signal, the noisy signal having symbols of a general alphabet. The system comprises a denoiser and an error correction decoder. The denoiser generates reliability information corresponding to metasymbols in the noisy signal based on an estimate of the distribution of metasymbols in the input signal and upon symbol transition probabilities of symbols in the input signal being altered in a quantized signal. A portion of each metasymbol provides a context for a symbol of the metasymbol. The quantized signal includes symbols of a finite alphabet and is formed by quantizing the noisy signal. The error correction decoder performs error correction decoding on noisy signal using the reliability information generated by the denoiser.

Abstract: Embodiments of apparatuses and methods for correcting intermittent errors in data storage structures are disclosed. In one embodiment, an apparatus includes a data storage location, error detection logic, inverting logic, control logic, operating logic, and evaluation logic. The error detection logic is to detect an error in a data value read from the data storage location. The inverting logic is to invert the erroneous data value to produce an inverted erroneous data value. The control logic is to cause the inverted erroneous data value to be stored in the data storage location and subsequently read from the data storage location to produce an operand value. The operating logic is to perform a logical operation using the erroneous data value and the operand value. The evaluation logic is to evaluate the result to determine if the error is a soft error.

Abstract: An error correction device for reducing the amount of access to an external memory while preventing the capacity of an internal memory from increasing. An optical disc stores scramble data for each data block. A descramble circuit reads scramble data in the data blocks from the optical disc as read blocks and applies a predetermined scramble value to the scramble data of each read block to generate descramble data. A 1-shift calculator generates a first calculated value by shifting the scramble value by one byte using a generation polynomial. A second shift calculator generates a second calculated value by shifting the scramble value by a number of bytes corresponding to {(total bytes of the data block in the column direction)+1?(total bytes of each read block in the column direction)} using the generation polynomial. An EOR circuit generates descramble data by applying the first or second calculated value as the scramble value to the input scramble data.

Abstract: A method for dynamically modifying a database schema in a streaming database management system receives a new database schema, compares the new schema to an existing schema, identifies the differences between the new schema and the existing schema, and applies the identified differences to the database in a single transaction, thereby producing a database organized according to the new database schema.

Abstract: A storage controller includes an interface to host computer apparatus and an interface to a plurality of controlled storage apparatus. The storage controller comprises a host write component operable to send a request to write a data object to a source data image at one of said plurality of controlled storage apparatus; a copy component operable in response to a metadata state to control copying of said data object to a target data image in a delimited sequence of data images in a cascade at said plurality of controlled storage apparatus and a fill-in component operable in response to detection of an offline condition of a disk containing said target data image to control substitution of a fill-in disk in place of said disk containing said target data image.

Abstract: This descriptive document is about a new backup device that takes advantage of the components of a PC's conventional power supply and it combines them with additional typical electronic components from an uninterruptible power supply (UPS). The result of such combination is a lower cost backup function that is applied directly to the PC and, therefore, eliminates the requirement of external devices—such as a UPS—to perform this backup function. In this document, the electronic components that combine with the PC's power supply in order to provide the backup functionality described above are referred to as integrated backup unit (URI).

Abstract: A method, apparatus, and computer instructions for self-diagnosing remote I/O enclosures with enhanced FRU callouts. when a failure is detected on a RIO drawer, a data processing system uses the bulk power controller to provide an alternate path, rather than using the existing RIO links, to access registers on the I/O drawers. The system logs onto the bulk power controller, which provides a communications path between the data processing system and the RIO drawer. The communications path allows the data processing system to read all of the registers on the I/O drawer. The register information in the I/O drawer is then analyzed to diagnose the I/O failure. Based on the register information, the data processing system identifies a field replacement unit to repair the I/O failure.

Abstract: Processing transactions using graph-based computations includes determining that at least one of a plurality of graph elements of a computation graph of a set of one or more computation graphs includes a computation to be performed for a given transaction, associating the given transaction with an instance of the computation graph that includes reusable computation elements associated with respective graph elements, and executing the graph to perform the computation.

Abstract: An error-correcting method used for decoding of data transmissions is disclosed. The error-correcting method is used for data with an error-correcting part and comprises: providing a multinomial for processing an error-correcting part to get an operational result; providing a database for saving the corresponding operational results of each single bit; and finding the error bit according to the operational results.

Abstract: Methods and systems for handling errors in applications are provided. A comparison may be executed to confirm that actual results are in accordance with expected results. If the comparison results in an application error, a special execution software object is executed. The special execution software object obtains and maintains a copy of the application context associated with the application error found. A user may then view the application context to determine the source of the error. A logbook may be maintained to store all of the application errors and associated application contexts.

Abstract: A decoding circuit includes a mixed modulation memory access circuit responsive to burst rejection information. The mixed modulation memory access circuit selectively accesses burst memory locations containing a valid burst of coded bits. The mixed modulation memory access circuit selectively avoids accessing burst memory locations containing a rejected burst of coded bits based on the burst rejection information. In one example, the mixed modulation memory access circuit accesses the valid burst when the burst rejection information indicates that the memory location contains valid bursts. In one example, the mixed modulation memory access circuit generates zero confidence information when the burst rejection information indicates that the memory location contains rejected bursts.

Abstract: A minimally degraded configuration is determined when failing connections occur. Associative deconfigurations are determined from deconfiguring hardware items in a server system, associative groups are derived, and failed connections are determined. Failed connections are determined between two hardware items that are in the same associative group, and the two hardware items at both endpoints of the failed connection are deconfigured. Each associative group state is set to unknown, and the failed connections are counted where a single endpoint of the failed connection is within the associative group. The associative group state is set to deconfigured, if a member of the associative group was deconfigured. Counts of the associative groups that remain in the unknown state are analyzed, and the associative group with the smallest failed connection count is selected and set to a configured state.

Abstract: A system includes an encoder that manipulates postcoded data and produces parity bits, and a parity bit encoder that produces encoded parity bits by inserting into the parity bits one or more flags with polarities, or states, that are selected to produce, after precoding, precoded parity bits that meet predetermined modulation constraints.

Abstract: The storage control device of the present invention switch-connects each of enclosures and individually stops the transmission of power to the enclosures that are not being accessed in order to reduce the power consumption amount. A plurality of additional enclosures are switch-connected via an inter-device switch to a base enclosure. Drives that have not been accessed for a predetermined period of time or more undergo spindown. If all the drives in the enclosure then assume the spindown state, the supply of power to each of the drives from the intra-enclosure power supply is stopped. In cases where all the drives in a certain enclosure have undergone spindown, the base enclosure turns OFF the switch in the power distribution circuit connected to this enclosure. As a result, the transmission of power to this enclosure is stopped. The fault diagnosis section detects a fault that has occurred with communications that employ the inter-device switch and specifies the point of the fault occurrence.

Abstract: Embodiments are provided to automatically managing system downtime in a computer network. In one embodiment, an event is created in an application server to schedule a system downtime period for a web server. When the scheduled downtime occurs, the web server is automatically removed from the network and a downtime notification message is automatically communicated indicating that the web server is offline. In another embodiment, events may be created to schedule downtime for web-based applications, including websites. Prior to the scheduled downtime, requests to a web-based application may be automatically stopped and redirected to a specified location. In another embodiment, the operation of web servers is automatically monitored to detect the presence of a fault condition and, if a fault condition is present, then a determination may be made that the affected web servers are down and requests to the down web servers are automatically redirected to an alternate server.

Abstract: Provided are an apparatus and a method for diagnosing fault and processing data of a satellite ground system. The apparatus and a method can prevent data loss of a satellite, and efficiently operate the satellite ground system using data buffer and penalty method when a temporary fault occurs. Data buffer stores data in fault situation and penalty method imposes high penalty in critical fault and low penalty in minor fault. System is managed according to penalty degree. The apparatus, includes: a satellite data processing and controlling means; a signal transforming means; a fault detecting and controlling means; a state displaying means for displaying a state of the satellite and the system; a penalty managing means for being notified whether the device has fault or not; a data storing means for storing and transmitting the data; and a system recovery supporting means.

Abstract: Systems, methods and media for recovering from a data scan error are disclosed. In one embodiment, a service processor determines the nature of the data scan error and, depending on the nature of the error, performs one of a plurality of data scan error recovery procedures.

Abstract: A method for efficiently calculating syndromes in Reed-Solomon decoding is adapted to be implemented in a processor having a parallel processing instruction set. The method includes: (a) initializing a syndrome vector; (b) obtaining a symbol from a Reed-Solomon block code; (c) finding a lookup index based on the symbol; (d) using the parallel processing instruction set, obtaining a finite field product vector Corresponding to the lookup index from a finite field vector multiplication table that includes at least one finite field product vector; (e) using the parallel processing instruction set, performing vector finite field addition on the finite field product vector corresponding to the lookup index and the syndrome vector, thereby obtaining an updated syndrome vector; and (f) outputting the updated syndrome vector.

Abstract: Provided are a method, system, and program for reassigning storage volumes from a failed processing system to a surviving processing system. A first processing system detects a failure of a second processing system. The first processing system determines device groups of storage devices managed by the failed second processing system and determines for each determined device group, hosts that connect to storage devices in the device group. The first processing system sends, for each device group, a unit check to each determined host indicating failure of each device group through one storage device in the device group to which the determined host connects. The determined hosts execute instructions to terminate any I/O operations in progress on the storage devices in the device group in response to the unit check indicating failure of one storage device in the device group and issue, a command to one storage device for the device group to end the busy condition.