Abstract: A plurality of multi-corner multimode (MCMM) databases are accessed, wherein at least one of the plurality of MCMM databases corresponds to a first optimization scenario, and at least one of the plurality of MCMM databases corresponds to a second optimization scenario. A first optimization move is performed on paths in the first optimization scenario. The first optimization move is verified using GBA on paths in the second optimization scenario to determine that the first optimization move does not cause timing violations outside an MCMM database associated with the first optimization scenario.

Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of clock routing trees. One embodiment involves accessing a circuit design and a clock tree hierarchy input indicating a nested list of partition or sink groups, each group of the nested list of groups comprising one or more clock tree elements of a plurality of clock tree elements from the circuit design. A routing topology associated with a source and a plurality of sinks are determined based on an ordering within the nested list of partition groups. These routing directions are used in synthesizing a clock tree for the circuit design. In additional embodiments, the clock tree hierarchy input provides clustering information, port placement for connections between partition groups of the clock tree, and parameters describing limitations or criteria for individual partition groups.

Abstract: A system and method place unit-level components in a macro within a unit of an integrated circuit that includes two or more of the units that each include two or more of the macros. The method includes detecting white space in a congestion plot of the macro. The white space represents potential placement areas for the unit-level components. The method also includes performing wire reach analysis between sources and sinks on different sides of the macro to determine an allowable region for the unit-level components, and deriving a buffer and latch placement reservation area in which to place the unit-level components based on the white space and the allowable region.

Abstract: A system and a computer implemented method for interior pinning in a macro block of an integrated circuit are provided. The method includes receiving child level information of the macro block including at least a location of a logic leaflet, receiving parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer, and selecting a pin location based on the child level information and the parent level information.

Abstract: In one embodiment, a method for building a clock tree for an integrated circuit design is provided. The clock tree may include a clock tree root node and a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design. The clock tree nodes may be arranged to distribute the clock signal to the sink pins. In synthesizing the clock tree, the sink pins may be clustered into one or more clusters. Clock tree nodes may be placed for the clock tree to distribute the clock signal to the one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters. For example, the clock tree timing variation parameters includes timing information for multiple process corners and/or multiple modes of operation.

Abstract: A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.

Abstract: Systems and techniques are described for context aware clock tree synthesis (CTS). A probability value can be computed for each clock sink in the set of clock sinks, wherein each probability value represents a probability that the corresponding clock sink has a critical clock latency. Next, the set of clock sinks can be clustered into a set of clock sink clusters based on the probability values. An optimization goal for each clock sink cluster can be selected, and an optimized subtree can be constructed for each clock sink cluster based on the selected optimization goal. The synthesized clock tree can be obtained by combining the optimized subtrees.

Abstract: A system and a computer implemented method for interior pinning in a macro block of an integrated circuit are provided. The method includes receiving child level information of the macro block including at least a location of a logic leaflet, receiving parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer, and selecting a pin location based on the child level information and the parent level information.

Abstract: A semiconductor device can be manufactured based on patterning groups to include a metal layer patterned according to separate patterning groups. The patterning groups are based on a layout pattern. Preparing the layout pattern includes selecting a first power pattern and a second power pattern, selecting a first pattern and a second pattern therebetween, and selecting a tie-connection pattern to connect the first power pattern to the first pattern. The manufacturing includes forming metal lines according to the patterning groups. Photomasks are manufactured according to the layout pattern, and the metal lines are formed according to the photomasks. A first photomask is manufactured based on the first power pattern and the second power pattern, the first pattern, and the tie-connection pattern, and a second photomask is manufactured based on the second pattern.

Abstract: The present disclosure relates to a system and method for evaluating spanning trees. Embodiments may include receiving, using at least one processor, a spanning tree including one or more sinks coupled by one or more edges. Embodiments may further include receiving a user-selected floating parameter. Embodiments may also include interchanging the one or more edges of the spanning tree based upon, at least in part, the user-selected floating parameter.

Abstract: A method can include separating a design area of a substrate for a semiconductor integrated circuit (IC) into cell blocks, where a distance between adjacent ones of the cell blocks can be greater than or equal to a minimum distance defined by a design rule for the semiconductor integrated circuit to provide separated cell blocks, designing a layout for the semiconductor IC in the separated cell blocks, and individually coloring the layout of each of the separated cell blocks.

Abstract: One example includes an RQL circuit simulation system. The system includes a circuit design tool that facilitates user inputs to design an RQL circuit design comprising at least one predetermined RQL circuit design component. The system also includes a memory system that stores the RQL circuit design and an RQL component library comprising predetermined RQL circuit design components from which the at least one predetermined RQL circuit design component is selected. Each of the predetermined RQL circuit design components includes predetermined RQL component metrics associated with performance of the respective one of the predetermined RQL circuit design components. The system also includes a circuit simulator configured to compile performance metrics associated with the RQL circuit design based on the predetermined RQL component metrics associated with the respective at least one of the predetermined RQL circuit design components and to simulate the RQL circuit design based on the performance metrics.

Abstract: Nets are assigned to wiring planes for generating a chip design. A computer is caused to execute a zero wire load timing session for a placed but unbufferred chip design. All nets of the chip design are set to a single wide wiring track without wiring plane assignments. A delta time delay is added to each sink of each of the nets to represent an estimated time of flight (TOF) delay. The nets wiring plane or width type for a particular pin is upgraded to a type having improved TOF characteristics. Each of the nets are compared against new predetermined slack and distance targets and new assigned wiring plane or width type determined to consume additional wiring track resources, and based on results, the upgrade is repeated or a design for session timing state for the nets is output to represent the unbufferred chip design.

Abstract: An clock skew adjusting structure is provided. The clock skew adjusting structure includes a substrate, a wiring structure, a first active component and a second active component. The wiring structure includes at least a wiring layer and at least a via, the via is configured for different wiring layers to be electrically connected with each other. The first active component is formed on the substrate and configured for delivering a clock signal to the wiring structure. The second active component is formed on the substrate and electrically connected to the first active component through the wiring structure thus forming a timing path. The second active component receives the clock signal through the timing path.

Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes determining clock resources in a design identifying operations to be performed by a PLD, determining available clock resources of the PLD, determining a flow network model corresponding to the design and the PLD, and determining a clock resource placement based on the flow network model. The flow network model may include a plurality of levels of vertices disposed between source and sink vertices, where vertices are coupled to each other using edges with unit capacity.

Abstract: Techniques for circuit concurrent gate sizing and repeater insertion considering the issue of size conflicts are described herein. Certain of these techniques can be directed to coupled gates within levels of a levelized circuit falling within a coupling window defined by a minimum slack gate and adjacent gates coupled to the minimum slack gate with an adjacency parameter less than a predefined adjacency limit.

Abstract: Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage, thereby alleviating congestion. Once the buffer chains have been reconstructed, the placement blockage can be removed from the circuit design. In some embodiments, congestion can be alleviated by spreading out buffer chains based on spreading out center of mass lines corresponding to the buffer chains.

Abstract: This application discloses performing a static timing analysis on a circuit design with an unbalanced clock tree, for example, to determine data arrival timing and clock arrival timing at multiple clock-driven circuits in a circuit design, and then performing clock tree synthesis on the circuit design to initially balance the unbalanced clock tree based, at least in part, on the data arrival timing relative to the clock arrival timing at the multiple clock-driven circuits. The clock tree after initial balancing includes a clock signal path configured to provide a clock signal to each of the multiple clock-driven circuits with a new clock arrival timing that corresponds to the data arrival timing.

Abstract: System and method of automatically performing flip-flop insertions for each net in a logic interface by using the RTL-estimated maximum count as a limit. Based on the timing analysis on the physical layout, a flip-flop insertion count needed for each net is derived and candidate locations for insertions are automatically detected. A set of constraints is applied to identify ineligible locations for flip-flop insertions. If more flip-flop insertions than the count limit are needed to satisfy the timing requirements for a net, timing-related variables are iteratively adjusted using the current layout until the timing requirements can be satisfied using the RTL count limit. If all the nets in the interface need fewer flip-flop insertions than the RTL count limit, the information can be fed back to update the RTL count limit. Each net is then parsed and flip-flops are inserted at appropriated locations.

Abstract: According to one aspect, a method may include receiving a circuit model that includes a clock mesh that controls each of a plurality of logic circuits by inputting a respective clock signal to an end-point of each logic circuit. The method may include providing an incremental latency adjustment to the circuit model by determining one or more end-points that are candidates for adjustment of a respective end-point's clock skew schedule. And, for each end-point that is associated with a negative front slack, adjusting a clock skew schedule of an end-point by a quantized amount. Further, for each end-point that is associated with a negative back-slack, adjusting the clock skew schedule of an end-point that is associated by a quantized amount. The method may also include repeating, the step of providing an incremental timing update. The method may include performing a timing evaluation upon the circuit model.

Abstract: An integrated circuit includes a clock source tier and at least two clock distribution tiers disposed in a vertical stack with the clock source tier. The clock source tier includes a clock circuit. Each of the at least two clock distribution tiers includes a clock distribution circuit. Each clock distribution circuit includes at least one pair of cross-coupled inverters.

Abstract: An approach for simulating a circuit design partitions the circuit design into pipeline regions that include one or more pipeline levels. A path length is computed for each combinational region within a pipeline region to compute an achievable timing goal for each pipeline region. A target retiming goal is determined for the set of pipeline regions based on the computed achievable timing goals of the pipeline regions. A pipeline region is identified from the set of pipeline regions that does not satisfy the target timing goal. A measure of slack is computed for each pipeline level in the identified pipeline region. Using the computed slack, path lengths of combinational regions in the pipeline levels of the identified pipeline region are iteratively retimed. The resulting circuit design is simulated using the retimed path lengths if the retimed critical path of the pipeline region satisfies the target timing goal.

Abstract: Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a first inverter configured to receive first and second clock signals and further includes a second inverter configured to receive the first and second clock signals. The first inverter is configured to provide to an output node an inverted first clock signal as controlled by the second clock signal. The second inverter is configured to provide to the output node an inverted second clock signal as controlled by the first clock signal. Another example apparatus includes a clock generator circuit to provide first and second clock signals responsive to an input clock signal, and further includes a duty phase interpolator circuit, a duty cycle adjuster and a duty cycle detector.

Abstract: A method and system to route connections of sub-networks in a design of an integrated circuit and a computer program product are described. The system includes a memory device to store instructions to route the connections of the sub-networks, and a processor to execute the instructions to determine a baseline route for each of the connections of each of the sub-networks, identify noise critical sub-networks in the integrated circuit design based on congestion, set a mean threshold length (MTL), segment the connections of the noise critical sub-networks based on the MTL, and re-route the baseline route based on segmenting. The MTL indicates a maximum length of each segment of each connection, each segment includes a different wirecode which is different from a wirecode of an adjacent segment, and each wirecode defines a width, a metal layer, and a spacing for each segment.

Abstract: In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable logic gates to gate clock signals to the plurality of flip flops; and minimizing timing variation of the clock signals to the plurality of flip flops.

Abstract: A method of forming a semiconductor arrangement is provided. The semiconductor arrangement includes an interconnection arrangement comprising a first connection between a driver and a receiver. At least one buffer is disposed along the first connection to reduce delay associated with the interconnection arrangement. However, buffers increase power consumption, and thus a determination is made as to whether a buffer is unnecessary. A buffer is determined to be unnecessary where removal of the buffer does not violate a timing constraint regarding an amount of time a signal takes to go from the driver to the receiver. If a buffer is determined to be unnecessary, the buffer is removed to reduce power consumption.

Abstract: Timing analysis of a chip component using feedback assertions without disrupting the timing of internal latch to latch paths in the chip component maintaining timing accuracy for all the boundary paths. This is achieved by using slack based feedback assertions for non-clock chip inputs and outputs which are used to dynamically derive the arrival time or the required arrival time assertions. The assertions on the clock inputs are not updated via feedback assertions to facilitate non-disruption of the latch to latch path timing. The timing non-disruption of the resulting latch to latch paths of the chip component increases the designer productivity during timing closure resulting in a shortened time to take the chip design through timing closure to manufacturing. This method is applicable for statistical as well as deterministic timing analysis.

Abstract: Techniques and systems for guiding circuit optimization are described. Some embodiments compute a set of aggregate slacks for a set of chains of logic paths in a circuit design. Each chain of logic paths starts from a primary input or a sequential circuit element that only launches a signal but does not capture a signal and ends at a primary output or a sequential circuit element that only captures a signal but does not launch a signal. Next, the embodiments guide circuit optimization of the circuit design based on the set of aggregate slacks.

Abstract: In accordance with some embodiments of the present disclosure a method for constructing a clock network comprises receiving design specifications for a clock network. The method further comprises determining a topology of the clock network based on the design specifications. The topology indicates at least one of a plurality of levels of the clock network, a buffer type for each level and a buffer fanout for each level. The method additionally comprises determining design parameters for the clock network based on the determined topology and generating a clock network synthesis tool specification file that includes the design parameters. The method also comprises synthesizing the clock network using the specification file such that the clock network includes the determined topology and such that the clock network synchronously distributes a clock signal from a clock generator to endpoints of the clock network.

Abstract: A processor of an aspect includes an on-die programmable architecturally-visible storage. The processor also includes a decode unit to receive a data access instruction of an instruction set of the processor. The data access instruction to indicate a data address that is to be associated with data to be stored in the on-die programmable architecturally-visible storage, to indicate a data size associated with the data to be stored in the on-die programmable architecturally-visible storage, and to indicate a destination storage location of the processor. An execution unit is coupled with the decode unit and the on-die programmable architecturally-visible storage. The execution unit is on-die with the on-die programmable storage. The execution unit is operable, in response to the data access instruction, to store the data, which is associated with the data address and the data size, in the destination storage location that is to be indicated by the instruction.

Abstract: Buffers on a clock tree are reduced, as long as there is enough set-up margin, in order to reduce power consumption in the clock tree. An FF group coupled to a partial tree, which is a part of the clock tree and expanded from the branch point being focused on, is defined as the target FF and the other FFs are defined as non-target FFs. The target buffer of an elimination candidate and the target and non-target FFs are defined so as not to change the slack in principle in a signal propagation path between the non-target FFs even if the buffer is eliminated. The buffer which can be eliminated is specified within a range in each signal propagation path which has a start point at the non-target FF and an end point at the target FF and in each signal propagation path between the target FFs.

Abstract: A clock transmission adjusting method applied to integrated circuit design is provided. The clock transmission adjusting method includes the following steps. At first, a timing path including a clock source and a sequential logic cell is provided. Then, at least one non-active wire delay module is inserted in the timing path to approach a predetermined clock arrival time. An integrated circuit structure utilizing the clock transmission adjusting method is also provided.

Abstract: A logic device includes a low-skew network that feeds a subset of elements on the logic device. The low-skew network includes a selector that can select from a plurality of signal sources which includes a first signal source and a second signal source, wherein the second signal source can reach at least one element outside of the subset.

Abstract: A method of validating timing issues in a gate-level simulation (GLS) of an integrated circuit design including multiple cells includes running a simulation routine of a behavioral model of the design and obtaining a first simulation result. If there is a possible timing violation at a cell corresponding to a forcing indeterminate value, the simulated output of the cell is forced to a first value and a second simulation result obtained. If this result is negative, a report of apparent timing violations at the cell is generated. If the second simulation result is positive, the output of the cell is then forced to a second value and a third simulation result is obtained. If this result is negative, a report of apparent timing violations at the cell is generated but, if it is positive, a report of no apparent timing violation is generated.

Abstract: A determining method includes obtaining terminal information indicating a first object terminal that is among terminals included among partial circuits and subject to determination of whether the first object terminal is an open terminal; obtaining for each terminal, connection information and first attribute information indicating an attribute of any one among an input terminal and an output terminal; generating, by a computer, for each terminal, second attribute information indicating an attribute opposite to the attribute indicated by the first attribute information; and determining, by the computer, whether a state of the first object terminal indicated by the terminal information becomes a high-impedance state, by simulating on the basis of the connection information and the second attribute information, a state of each terminal when a value of a terminal among the terminals and indicated as an output terminal by the second attribute information, is set at a first specified value.

Abstract: Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan.

Abstract: In some embodiments, in a method, a physical netlist of a placed IC chip design is received. The physical netlist comprises a plurality of registers. Timing criticalities of register pairs in the registers are obtained. Weights to the register pairs are assigned based on the timing criticalities of the register pairs. Candidate registers that are in physical vicinity of a first cluster are identified. If a first candidate register in the candidate registers of the first cluster is in a second cluster, selecting the first candidate register as the first register to be added to the first cluster if sum of weights of other candidate registers in register pairs across the boundary of the first cluster and the first candidate register in one or more register pairs across a boundary of the second cluster is optimized.

Abstract: In a timing delay characterization method, a signal path between an input terminal and an output terminal of a semiconductor circuit is divided into an input stage, a processing stage, and an output stage. An operation of the input stage is simulated at various input parameter values of an input parameter at the input terminal to obtain corresponding extrinsic input timing delays associated with the input stage. An operation of the processing stage is simulated to obtain an intrinsic timing delay associated with the processing stage. An operation of the output stage is simulated at various output parameter values of an output parameter at the output terminal to obtain corresponding extrinsic output timing delays associated with the output stage. A timing delay data store is generated or populated based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay.

Abstract: A layout method of a semiconductor integrated circuit includes detecting a path having a constraint violation in a laid-out semiconductor integrated circuit, determining an insertable range of a buffer to be inserted on a route of the path so as to remove the constraint violation, evaluating, with respect to a cell already placed in the insertable range, a wiring length, and presence or absence of a constraint violation if the cell is hypothetically moved to an empty space in a vicinity of the insertable range, determining an insertion position of the buffer based on a result of the evaluation, moving the cell already placed at the insertion position of the buffer to the empty space in the vicinity of the insertable range, placing the buffer at the insertion position, and rerouting the buffer and the moved cell.

Abstract: A method for performing latency optimization on a system design to be implemented on a target device includes inserting a variable latency indicator in the system design at a place where latency can be varied. The system design includes pipeline registers at the place where the variable latency indicator is inserted. Latency optimization is then automatically performed on the system design, during a computer aided design flow performed by an electronic Design Automation (EDA) tool, by varying the number of the pipeline registers at the variable latency indicator to obtain optimized latency without affecting system performance of the system design.

Abstract: A method for performing routing for a logic design includes utilizing signal transition time as a criteria for selecting resources to provide interconnection between the components of the logic design.

Abstract: Techniques generating a simulation model for a circuit design are disclosed. One of the techniques includes extracting a plurality design properties associated with the circuit design. The design properties are extracted from a netlist of the circuit design and may include an input/output (I/O) buffer setting extracted from a first netlist of the circuit design or an environmental condition associated with the circuit design. A second netlist for the circuit design is generated based on the design properties and is simulated based on the design properties. A simulation model for the circuit design is generated. In an exemplary embodiment, the simulation model reflects the I/O buffer setting or the environmental condition associated with the circuit design.

Abstract: A library of model diffraction patterns is generated where each represents a diffraction pattern expected from a target structure defined by a set of parameters and having a first part and a second part, the first part comprising a scattering object. The target structure is defined. The scattering effect of the first part of the target structure is defined by a set of first part parameters, for a plurality of different sets of first part parameters. The scattering effect of the second part of the target structure defined by a set of second part parameters, for a plurality of different sets of second part parameters. The results of the calculations is used to calculate the model diffraction patterns.

Abstract: Methods and apparatuses are described for optimizing local clock skew, and/or for synthesizing clock trees in an incremental fashion. For optimizing local clock skew, the circuit design can be partitioned into clock skew groups. Next, for each clock skew group, an initial clock tree can be constructed that substantially minimizes worst case clock skew in the clock skew group, and then the initial clock tree can be further optimized by substantially minimizing worst case local clock skew in the clock skew group. For performing incremental clock tree synthesis, a portion of a clock tree in the circuit design can be selected based on a set of modifications to the circuit design. Next, a new clock tree can be determined to replace the selected portion of the clock tree. The circuit design can then be modified by replacing the selected portion of the clock tree with the new clock tree.

Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.

Abstract: An automated method of modifying a semiconductor chip design includes creating a timing analysis of said semiconductor chip design, identifying a pluraility of gates in said semiconductor chip design which have either too fast a rising edge or falling edge, for each gate in said plurality of gates adding a stacked transistor to provide delay to the rising or falling edge of the gate. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure includes a CMOS device having a first transistor with a first input, a pair of stacked transistors having a second input, and an output.

Abstract: Disclosed is a method and system for clock tree construction across clock domains, an integrated circuit and fabrication method thereof. A method for clock tree construction includes acquiring a netlist describing an integrated circuit (IC), comprising data for describing physical locations and logic connections of clock sinks belonging to multiple clock domains on the pattern of the IC, and constructing the clock tree across clock domains based on the netlist, such that clock cells belonging to different clock domains can share more physical locations. Accordingly, clock trees can be constructed across clock domains to improve IC performance.

Abstract: A method of reducing current leakage in unused circuits performed during semiconductor fabrication and a semiconductor device or integrated circuit thereby formed. The method involves modifying a characteristic of at least one idle circuit that is unused in a product variant, to inhibit the circuit and reduce current leakage therefrom upon powering as well as during operation. The method can substantially increase the Vt (threshold voltage) of all transistors of a given type, such as all N-type transistors or all P-type transistors. The method is also suitable for controlling other transistor parameters, such as transistor channel length, as well as other active elements, such as N-type resistors or P-type resistors, in unused circuits which affect leakage current as well as for other unused circuits, such as a high Vt circuit, a standard Vt circuit, a low Vt circuit, and an SRAM cell Vt circuit.

Abstract: Techniques for generating timing constraints for an integrated circuit including a clock tree network are described. The techniques may be associated with a clock tree synthesis tool that receives a design of the integrated circuit and generates a clock tree network including a plurality of clocked components of the integrated circuit. The constraints may be generated as a function of the duration of propagation of a data signal from a transmitting clocked component coupled to a receiving clocked component.

Abstract: An ECO hold time fixing method fulfills a short path padding in a placed and routed design by a minimum capacitance insertion. In the method, a padding value determination step receives the placed and routed design and is based on a cell library, timing constraints, and a timing analysis report to determine padding values and locations required for each gate of the placed and routed design to output. A load/buffer allocation step is based on a spare cell information, a dummy metal information, and the padding values and locations to achieve the short path padding in the placed and routed design.