Abstract: A circuit analysis tool is provided, enabled with software instructions, for minimizing circuit crosstalk. The instructions provide a first circuit connected to an output mode, having a last gate with a plurality of inputs and an output. The instructions calculate a first circuit victim net delay range (timing window) having a minimum delay (Vmin) and a maximum delay (Vmax). A second circuit is provided having an output connected to the output node to supply an aggressor net delay range (A1) having a minimum delay (A1min) and a maximum delay (A1max). The aggressor net delay range at least partially overlaps the victim net delay range. Without increasing the value of Vmax (critical path timing), the first circuit victim net delay range is shrunk, thereby minimizing crosstalk between the first and second circuits without an increase in first circuit maximum signal delay.

Abstract: In one embodiment of the invention, a method for designing an integrated circuit is disclosed. The method includes automatically partitioning clock sinks of an integrated circuit design into a plurality of partitions; automatically synthesizing a clock tree from a master clock generator into the plurality of partitions to minimize local clock skew within each of the plurality of partitions; and automatically synthesizing clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions.

Abstract: Provided is a computer system (1) including a storage (2) for storing a netlist (31), and a contents generator (12) for generating a program (32) containing a statement to execute a plurality of operations of an operation portion contained in the netlist (31). The operation portion includes an operation performing logic operations of multiple stages and having a plurality of inputs, and an operation of a previous stage for a plurality of input sources.

Abstract: A computer program for generating an H-tree for an integrated circuit design stored on a computer readable medium includes code to receive from a user a set of parameters to configure the H-tree. The parameters include a starting segment length and an ending segment length. The computer program also includes code to select a starting location in the integrated circuit design. The computer program further includes code to place an anchor H at the starting location. The computer program further includes code to recursively place child Hs on the H-tree based on the starting segment length and the ending segment length to create a fan-out with equal weight on each child H. The number of levels of the H-tree is calculated according to a rounded down integer equal to a binary logarithm of a quotient of the starting segment length divided by the ending length.

Abstract: A circuit board analyzer includes a storage unit for storing mesh position information on an analyzed mesh-division model and extracted circuit constants in relation to each other; a division-model configuration unit for dividing the layout of a circuit board into meshes to configure a new mesh-division model; an identical-mesh determination unit for making a comparison between mesh position information on the new mesh-division model and mesh position information on the analyzed mesh-division model to determine identical meshes that have identical mesh position information; and a circuit-constant extraction unit for performing analytical processing based on the new mesh-division model to extract new circuit constants and reusing, as a new circuit constant associated with the identical meshes, an extracted circuit constant that is related to the mesh position information on the identical meshes.

Abstract: The present of the invention provides a method of manufacturing a semiconductor device, including the steps of: acquiring information on a graphic composing a physical layout of a semiconductor integrated circuit; carrying out calculation for a transferred image in the physical layout; carrying out calculation for a signal delay based on the physical layout, and obtaining a wiring not meeting a specification having the signal delay previously set therein; and setting a portion into which a repeater is to be inserted based on at least one result of results obtained from the information on the graphic and calculation for the transferred image, respectively, with respect to the wiring not meeting the specification.

Abstract: A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.

Abstract: A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one.

Abstract: A method, system and computer program product for implementing enhanced clock tree distributions to decouple across N-level hierarchical entities of an integrated circuit chip. Local clock tree distributions are constructed. Top clock tree distributions are constructed. Then constructing and routing a top clock tree is provided. The local clock tree distributions and the top clock tree distributions are independently constructed, each using an equivalent local clock distribution of high performance buffers to balance the clock block regions.

Abstract: A method to at least partially isolate a net of a circuit design is provided and includes testing a timing characteristic of a circuit design, identifying from a result of the testing a net of the circuit design to be at least partially isolated from an adjacent net and determining a percentage of the identified net to be partially isolated.

Abstract: Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.

Abstract: A method for routing a chip, involving forming a plurality of nets configured to connect components of the chip, wherein each of the plurality of nets is included in a netlist, assigning at least one repeater to each of the plurality of nets in the netlist, wherein the repeaters are assigned prior to performing physical routing of the plurality of nets, inserting the at least one repeater in a corresponding net, wherein the insertion of the at least one repeater divides the corresponding net into at least two subnets, and performing the physical routing of the plurality of nets by connecting each of the subnets.

Abstract: A device development tool selects a source component and identifies a plurality of sink components in a device design layout. The device development tool determines whether the sink components are configured in a single-sided layout, a multi-sided layout, or a multi-distance layout. Next, the device development tool computes a first level center of gravity for the plurality of sink components and also computes an X distance and a Y distance from the source component to the first level center of gravity. The device development tool then groups the plurality of sink components into sets and places buffers in the layout using an algorithm that is specific for the identified layout type.

Abstract: A method executed by a computer and for designing a semiconductor integrated circuit, includes detecting, from layout data of a semiconductor integrated circuit, a clock path that propagates the clock signal and of which clock buffers are single-gate inverting clock buffers; selecting sequentially data holding elements connected to the detected clock path; identifying an input clock buffer of each selected data holding element; determining whether the identified clock buffer outputs the clock signal according to non-inverting logic or inverting logic, based on the number of gates from the clock source to the clock buffer; replacing, based on a determination result, the data holding element with a first data holding element that takes in data in synchronization with a rising edge of the clock signal or with a second data holding element that takes in data in synchronization with a falling edge of the clock signal; and outputting a replacement result.

Abstract: The invention concerns a computer implemented method of circuit conception of a clock tree (200) comprising: a plurality of pulse generators (202) each being coupled to the input of one or more pulsed latches and being arranged to generate a pulsed signal (PS); and a tree of buffers (204) for supplying a clock signal (CLK) to the pulse generators, the method comprising: the conception of the clock tree without pulse generators based on a timing analysis by the computer of the propagation of clock edges in the clock tree; and replacing by the computer in the clock tree at least one buffer, coupled to the input of each pulsed latch, by a pulse generator.

Abstract: A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.

Abstract: The present disclosure is directed to a method for estimating an interconnect delay for a source-to-sink path of a net within a Very Large Scale Integration (VLSI) circuit, the source-to-sink path connecting a source and a sink in the net. The method may comprise estimating a total wire capacitance; calculating a delay contribution based on delay of the source-to-sink path and delay of a plurality of off-path sinks; and estimating the interconnect delay for the source-to-sink path based on the delay contribution.

Abstract: Achieving clock timing closure in designing an integrated circuit involves virtually synthesizing a clock network for the integrated circuit design to generate virtual clock buffering in the clock network before a point in the design flow at which the clock network is actually synthesized and committed to a netlist. Timing violations are determined for clock gates generated by the virtual clock buffering. Clock gating transforms are evaluated for the clock gates having the timing violations, based on recalculated clock and data path delays, to incrementally virtually synthesize the clock network. The clock gating transforms that result in the best timing gains are committed to the netlist. The clock network is then actually synthesized for the integrated circuit design, and design changes, due to the actual clock network synthesis, are committed to the netlist.

Abstract: A method of performing a pre-route repeater insertion methodology for at least part of a circuit design may include: partitioning at least part of a circuit design into a plurality of tiles; determining at least one attribute of one or more individual tiles of the plurality of tiles; and determining a repeater solution based at least in part on the determined attributes of the one or more individual tiles. A computer implemented tool for performing a pre-route repeater insertion methodology for at least part of a circuit design may include: a module configured to partition at least part of a circuit design into a plurality of tiles; a module configured to determine at least one attribute of one or more individual tiles of the plurality of tiles; and a module configured to determine a repeater solution based at least in part on the determined attributes of the one or more individual tiles.

Abstract: A device comprises a analysis section for detecting hold errors according to data including the values of the input and output nodes of the FF circuit, and identifying the node in which a hold error has occurred, a determining section for determining insertion of the trailing edge FF or the buffer into hold error sections on the basis of the results of the analysis by the analysis section, a FF insertion section for inserting the FF into a hold error section subjected to position determination so as to insert the trailing edge FF, and connecting a clock line to the FF based on the results of the determining section, and a buffer insertion section for inserting the buffer into the hold error section subjected to the position determination so as to insert the FF based on the results of data of the determining section.

Abstract: A power noise cycle is obtained from a dynamic IR drop analysis and a delay of a delay pass is a multiple of the noise cycle. Thereby, a delay increment and a delay decrement of a power noise amount (delay time×power noise amplitude) received when an internal signal of the semiconductor integrated circuit passes through a delay pass circuit are approximately the same.

Abstract: Systems and methods for synthesizing a gated clock tree with reduced clock skew are provided. A gated clock tree circuit with reduced clock skew may include a clock source and edge-triggered state elements. A gated clock tree disposed between the clock source and state elements may include a level in which each logic gate has a common logic type. Logic gates in the gated clock tree may also be configured as logic-gate buffers. The logic gates may also be configured as NAND-gated equivalents. The clock signal distributed through the gated clock tree may drive both positive-edge-triggered and negative-edge-triggered state elements.

Abstract: A method for analyzing an design of an integrated circuit, the method includes defining possible timings of signals to be provided to the integrated circuit and calculating hold violations; characterized by including a stage of determining relationships between clock events and corresponding data/control events that ideally precede the clock events, in response to the possible timing of signals; and determining hold parameters in response to the relationships. A computer readable medium having stored thereon a set of instructions, the set of instructions, when executed by a processor, cause the processor to define at least one internal delay of a designed component, characterized by causing the processor to define a cell that is characterized by multiple hold times and multiple setup values for a certain clock skew value.

Abstract: An IC designing method includes planning placement of a first isolated-power supplied region operating between common ground and power bus lines during a normal operation, and second/third isolated-power supplied regions each operating between the common ground bus line and first/second isolated power lines and supplied with potentials different from the common power supply, planning placement of first electrostatic protection circuits connected between the common ground power bus lines and between the common ground bus line and the first/second isolated power lines, and second electrostatic protection circuits connected between the first/second isolated power lines and the common power bus lines, judging presence of a signal transmission between non-adjacent regions among the first to third isolated-power supplied regions, and amending the circuit to insert a buffer circuit powered by the common power bus line in a transmission path when the signal transmission is present.

Abstract: A plurality of third fixed potential lines are wired in parallel. A group of high-potential-side fixed potential lines containing a first fixed potential line and a second fixed potential line are wired in a plurality at predetermined intervals in a direction perpendicular to the third fixed potential line. In a layout region, surrounded by a pair of adjacent third fixed potential lines and a pair of groups of adjacent high-potential-side fixed potential lines, where a first element or a second element is arranged, either one of the first fixed potential line and the second fixed potential line is wired between the pair of third fixed potential lines. In a layout region used for second elements, a second fixed potential line connecting a pair of second fixed potential lines contained respectively in a pair of groups of high-potential-side fixed potential lines that form the layout region is wired between a pair of third fixed potential lines that form the layout region.

Abstract: Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.

Abstract: A layout design method in accordance with an exemplary aspect of the present invention is a layout design method for a clock tree circuit, including disposing a first clock distribution circuit in a clock tree circuit, wiring the clock tree circuit in which the first clock distribution circuit is disposed, verifying timing of the wired clock tree circuit, and replacing the first distribution element by a second clock distribution circuit based on a result of the timing verification, the second clock distribution circuit having roughly a same input load capacitance as the first clock distribution circuit and a different delay value from the first clock distribution circuit.

Abstract: An algorithm and architecture are disclosed for performing multi-argument associative operations. The algorithm and architecture can be used to schedule operations on multiple facilities for computations or can be used in the development of a model in a modeling environment. The algorithm and architecture resulting from the algorithm use the latency of the components that are used to process the associative operations. The algorithm minimizes the number of components necessary to produce an output of multi-argument associative operations and also can minimize the number of inputs each component receives.

Abstract: The present disclosure is directed to a method for determining a plurality of buffer insertion locations in a net for an integrated circuit design. The method may comprise calculating a plurality of resistive-capacitive (RC) influences in parallel, each RC influence corresponding to one of a plurality of buffering options available for a first sub-tree for the addition of a wire segment to the first sub-tree; updating the plurality of RC influences for the addition of a buffer for the first sub-tree, the buffer comprising one of a plurality of buffer types; and merging the first sub-tree with a second sub-tree in parallel by grouping the plurality of buffering options available for the first sub-tree and a plurality of buffering options available for the second sub-tree into a plurality of merging groups, and merging at least two groups of the plurality of merging groups in parallel.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system is provided. A scheduling algorithm pre-computes return time data for data connected to DRAM buffer chips and stores the return time data in a table. The return time data is expressed as data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.

Abstract: In a timing analysis apparatus for use in a semiconductor integrated circuit, which analyzes operation timing of a semiconductor integrated circuit having a logic gate circuit including a plurality of logic gates, a controller detects at least one of a power supply voltage and a ground voltage of a power supply, decomposes the noise waveform into frequency components, classifies the frequency components into low-frequency components lower than a predetermined threshold frequency and high-frequency components higher than the threshold frequency, calculates a static delay time of each of the logic gates due to the low-frequency components, calculates a dynamic delay time of each of the logic gates due to the high-frequency components, and determines a delay time of each of the logic gates by synthesizing the calculated respective delay times.

Abstract: Buffers are placed on selected nets coupled to input and output pins of entities in an IC device. This includes loading selected input and output pins of entities prior to respectively buffering nets of the entities and buffering in successive iterations, which includes setting artificial loads on selected input pins. The buffering in a current iteration is limited to i) buffering nets on the current iteration entity for receivers on the current iteration entity and ii) buffering nets on the current iteration entity directly coupled to respective nets of an immediately adjacent entity that has been buffered already in a preceding one of iterations, but only if the already buffered net is coupled to a receiver on its own net or a receiver on some other already buffered net via nets that have all been buffered via one or more of the preceding iterations.

Abstract: An electronic design automation (EDA) tool for and method of optimizing a placement of process monitors (PMs) in an integrated circuit (IC). In one embodiment, the EDA tool includes: (1) a critical path/cell identifier configured to identify critical paths and critical cells in the IC, (2) a candidate PM position identifier coupled to the critical path/cell identifier and configured to identify a set of candidate positions for the PMs, (3) a cluster generator coupled to the critical path/cell identifier and configured to associate the critical cells to form clusters thereof and (4) a PM placement optimizer coupled to the candidate PM position identifier and the cluster generator and configured to place a PM within each of the clusters by selecting among the candidate positions.

Abstract: A design methodology and algorithms for the computer aided design of integrated circuits having clock distribution networks. The clustering of latch distribution tree components is combined with repositioning of such components within clock sector areas. The movement and clustering of components is such that the timing constraints are preserved. The methods is described in terms of reducing and balancing the load inside each clock sector, although the techniques may also be applied to balancing load between clock sectors.

Abstract: A designing method is provided for designing an electric circuit including a clock output circuit for delivering a clock signal and a plurality of processing circuits for receiving the clock signal from the clock output circuit via wirings for clock transmission so as to perform a predetermined process based on the clock signal. The method includes, as a method for designing the wirings for clock transmission to have a predetermined length, a first step of connecting wirings between each of the processing circuits and an arbitrary point (as a “first point”) so that the wirings have substantially the same length (as a “first length”), and a second step of connecting the first point to the clock output circuit by a single wire having the length that is obtained by subtracting the first length from the predetermined length. Thus, lengths of the wirings for transmitting the clock signal to the plurality of circuits are adjustable while the entire length of the wirings is minimized.

Abstract: A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design.

Abstract: A method of designing a semiconductor device is provided. According to the method, a group of cells that is a target of clock distribution is placed. After the group of cells is placed, a plurality of clock driver cells for driving the clock are placed such that each clock driver cell is prohibited from overlapping with a prohibited region of a predetermined size surrounding another clock driver cell.

Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

Abstract: A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.

Abstract: A method of verifying a semiconductor integrated circuit is provided. A controlling cell and a controlled cell controlled by a control signal output from the controlling cell are placed in an IO region of the semiconductor integrated circuit. The method includes: (A) providing a library that includes requirement information specifying the controlling cell required by the controlled cell; (B) obtaining a region information indicating a region within the IO region in which a signal interconnection through which the control signal is transmitted is provided; and (C) verifying whether or not the specified controlling cell is placed within the region, in a case where the controlled cell is placed within the region.

Abstract: A design method of a semiconductor integrated circuit sets an area having apices of opposing corners of a position of a start point logic cell and a position of an end point logic cell to a repeater search area, adds free area information to the repeater search area, sets a drive boundary in the repeater search area based on a drive ability of the start point logic cell, searches a repeater candidate that can be arranged in an area of the drive boundary based on the free area information, calculates a delay time from the start point logic cell to the end point logic cell based on delay time information and a coordinate of the repeater candidate that is searched, and determines a repeater arranged between the start point logic cell and the end point logic cell from the repeater candidate based on the delay time that is calculated.

Abstract: A method of forming a scan chain for testing an integrated circuit includes examining an interconnection of register elements in an integrated circuit design. A register element segment is identified which includes a source register element having an output and a destination register element having an input directly coupled to the output of the source register element. The segment is selectively coupled to another scan register element to form a portion of scan chain.

Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip.

Abstract: A computer readable storage medium includes executable instructions to construct a delay element to replicate the timing of critical gates and paths within a segment of an asynchronous circuit. The rise and fall delay mismatch of the delay element is minimized without obeying timing constraints. The position of each output of the delay element is determined to include a globally shared node within the segment and a non-shared local node in the segment.

Abstract: A clock-gating circuit insertion method includes inserting a clock-gating circuit into a position detected on the basis of a circuit data. Timing analysis of an enable signal is performed for the clock-gating circuit. An upper limit of delay variations for the enable signal is calculated to satisfy setup conditions on the basis of the result of the timing analysis. A selector-equipped clock-gating circuit including a selector circuit and a clock-gating circuit is inserted into the candidate position for insertion. The selector circuit selects and outputs the enable signal when delay variations are not above the upper limit. The selector circuit selects and outputs a signal designating the passing of a clock signal when the delay variations are above the upper limit. The clock-gating circuit passes or intercepts the clock signal on the basis of the output signal of the selector circuit.

Abstract: A method for reducing power consumption for an integrated circuit comprises the steps of (1) providing (i) a clock tree wherein the clock tree comprises a clock source, a plurality of clock sinks, and a plurality of internal nodes, (ii) the physical locations of the clock source, the clock sinks, and physical location of a gating-signal control logic circuit, (iii) the activity information of the sinks; (2) recursively determining a merging segment set containing merging segments for each internal node and computing switched capacitance of a subtree rooted at each internal node in a bottom up manner, wherein the merging segments have the same signal delay for the clock sinks in a subtree rooted at each internal node; and (3) recursively determining a location for each internal node selected from the merging segment set in a top down manner on a basis that the switched capacitance of a subtree rooted at each internal node is minimum.

Abstract: A design tool for automatically identifying minimum timing violation corrections in an integrated circuit (IC) design includes program instructions executable by a processor to identify locations to add a delay along each circuit path having a minimum timing violation. The tool may also sequentially try each of a plurality of circuit changes that add the delay and to evaluate a result of each circuit change until an acceptable percentage of the minimum timing violation has been corrected. In response to each circuit change, the design tool may update an internal node report, which includes a listing of circuit nodes and a maximum timing slack available at each node, by reducing a maximum slack value of each affected node by an amount of the added delay. The design tool may generate an output report that includes a listing of the circuit changes which correct the minimum timing violations.

Abstract: A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.

Abstract: An apex is extracted from a designed wiring layout. In start/end portion circular arc processing a circular arc is added to the apex-containing portion, and the layout data file is rewritten so that a portion, representing a region surrounded by circular arc and two lines, is added to the wiring line. In bend portion circular arc processing circular arcs are added to the respective apex-containing portions, and the layout data file is rewritten so that: a portion corresponding to a region surrounded by the circular arc and two lines is added to the apex-containing portion of the layout when the determined angle is less than 180 degrees; a portion corresponding to a region surrounded by the circular arc and two lines is removed from the apex-containing portion of the layout when the determined angle exceeds 180 degrees.

Abstract: A method and system for concurrent buffering and layer assignment in integrated current layout. Buffers are inserted and metal interconnects or “wires” are sized for every net, which consists of one driver and one or more receivers, such that timing skew constraints can be met. Long nets are promoted to a higher level if the slew violation can be fixed only by a promotion of the net or if the “slack” gain available by this promotion is equal to or greater than a predesignated layer of promotion threshold. In response to determining these layer assignments, the method and system then systematically demotes nets that are not critical and which do not impact the circuit and electrical constraints in order to minimize the use of high layer wire resources.