Abstract: An ECO hold time fixing method fulfills a short path padding in a placed and routed design by a minimum capacitance insertion. In the method, a padding value determination step receives the placed and routed design and is based on a cell library, timing constraints, and a timing analysis report to determine padding values and locations required for each gate of the placed and routed design to output. A load/buffer allocation step is based on a spare cell information, a dummy metal information, and the padding values and locations to achieve the short path padding in the placed and routed design.

Abstract: Methods for allocating spare latch circuits to logic blocks in an integrated circuit design are provided. A method includes determining logic blocks in the design and determining and determining an allocation of spare latch circuits among the logic blocks based on respective attributes of the logic blocks. The method further include placing the spare latch circuits in the design in accordance with the determined allocation based on local clock buffers corresponding with the logic blocks.

Abstract: An electronic design automation (EDA) tool alters a user's netlist to provide timing success for distribution of asynchronous signals. Distribution networks are used with the addition of pipeline registers before and/or after the distribution buffer. Or, a tree of pipeline registers is inserted between the asynchronous source and the destination registers. Or, any number of distribution networks are stitched together and pipeline stages may be inserted before and/or after each distribution buffer. Or, beneficial skew is utilized by introducing a delay component that skews a clock signal. The skewed clock signal drives a pipeline register that is inserted before a distribution buffer in order to improve timing margin. Any of various compilation techniques may be used within the EDA tool to solve the problem of distributing high-speed, high-fanout asynchronous signals.

Abstract: Method of placing and routing circuit components including: dividing a layout area of an integrated circuit (IC) design into an array of tiles, each tile having a plurality of edges that are common to adjoining tiles; placing of circuit components into the layout area of the IC design such that each tile including a plurality of circuit components, the placing of circuit components being performed for primarily routability without resort to a timing model, routability being measured by congestion of wiring nets at the tile edges; performing a virtual timing operation of the IC design with a virtual timing model assuming ideal buffering is done to test the placement of circuit components; performing a wire synthesis operation of the IC design for layer assignment, buffering and timing optimization while minimizing degradation in routability; and performing a plurality of timing optimizations of the IC design while minimizing degradation in routability.

Abstract: An extraction tool for, and method of, determining a stage delay associated with an integrated circuit (IC) interconnect. In one embodiment, the extraction tool includes: (1) a driver strength estimator configured to extract dimensions of a driver associated with the interconnect and estimate a driver strength therefrom, (2) a driver delay estimator coupled to the driver strength estimator and configured to estimate a driver delay based on the driver strength, (3) an interconnect delay estimator configured to estimate an interconnect delay based on extracted C and RC parameters associated with the interconnect and (4) a stage delay estimator coupled to the driver delay estimator and the interconnect delay estimator and configured to estimate the stage delay based on the driver delay and the interconnect delay.

Abstract: Systems and techniques are described for efficiently and accurately identifying candidate nets that would benefit from buffering. A buffering process can then be performed only on the identified candidate nets. Embodiments described herein can quickly and accurately identify nets for which performing buffering optimization would most likely waste computational time (so they can be skipped for the buffering transformation), thereby improving the overall performance of buffering optimization and overall physical synthesis optimization. Some embodiments use a buffer topology generating process to generate a buffer topology for a net and then use a numerical sizing process to size the buffers in the buffer topology and the driver gate.

Abstract: In an LSI design method of designing a clock tree that supplies a clock signal to a plurality of leaves from a clock supply point, when a high level clock tree is constituted by H-tree and a low level clock tree is formed by CTS, the number of stages of a high level clock tree is optimized without giving any constraint on the placement of a low level clock tree. The leaves are divided into a plurality of groups to form a low level local tree. A clock-supplied region including all leaves to be supplied with a clock is uniformly divided and for each divided region, a skew when a clock signal is supplied from an end of an H-tree to start points of a plurality of local trees included in that region is estimated. The clock-supplied region is more finely equally-divided to increase the number of stages of H-tree.

Abstract: A design tool with a direct current (DC) transformation analysis unit determines combinations of candidate sink locations for sector buffers within a sector of a clock network design. For each of the combination of candidate sink locations, the design tool transforms resistances of the sector with the combination of candidate sink locations into resistances of an electrical circuit. The design tool transforms capacitances of the sector with the combination of candidate sink locations into current sources of an electrical circuit. The design tool performs a DC circuit analysis, wherein results of the DC circuit analysis include a variance of voltage at nodes of the sector and a maximum value of current from currents flowing between pairs of the nodes of the sector. The design tool determines which of the combination of candidate sink locations has the minimum variance of voltage with the results of the DC circuit analysis.

Abstract: An algorithm and architecture are disclosed for performing multi-argument associative operations. The algorithm and architecture can be used to schedule operations on multiple facilities for computations or can be used in the development of a model in a modeling environment. The algorithm and architecture resulting from the algorithm use the latency of the components that are used to process the associative operations. The algorithm minimizes the number of components necessary to produce an output of multi-argument associative operations and also can minimize the number of inputs each component receives.

Abstract: To provide a design support device of a three-dimensional integrated circuit capable of, in the case where a placement position of a through-via changes in the design phase of a three-dimensional integrated circuit composed of a plurality of semiconductor chips in layers, avoiding change of respective placement positions of other parts as much as possible. A design support device includes a TSV placement unit that determines respective placement positions of through-vias on one semiconductor chip, the through-bias each penetrating to connect to another semiconductor chip, a TSV reserved cell placement unit that determines, based on the respective placement positions of the through-vias, respective placement positions of reserved cells as respective spare placement positions of the through-vias, and a mask data generation unit that generates layout data that includes the respective placement positions of the through-vias and the respective placement positions of the reserved cells.

Abstract: Methods and apparatuses are described for optimizing local clock skew, and/or for synthesizing clock trees in an incremental fashion. For optimizing local clock skew, the circuit design can be partitioned into clock skew groups. Next, for each clock skew group, an initial clock tree can be constructed that substantially minimizes worst case clock skew in the clock skew group, and then the initial clock tree can be further optimized by substantially minimizing worst case local clock skew in the clock skew group. For performing incremental clock tree synthesis, a portion of a clock tree in the circuit design can be selected based on a set of modifications to the circuit design. Next, a new clock tree can be determined to replace the selected portion of the clock tree. The circuit design can then be modified by replacing the selected portion of the clock tree with the new clock tree.

Abstract: Processing a circuit design for implementation on a target device includes, for a first driver that is a driver of a net having a plurality of loads, selecting a second driver that is a driver of the first driver. A representation of a rectilinear Steiner arborescence (RSA) tree is generated from the second driver and the plurality of loads. The RSA tree includes nodes representative of the plurality of loads and a plurality of Steiner points. A subset of the plurality of Steiner points in the RSA tree is selected for disposing respective replicated instances of the first driver. The respective replicated instances of the first driver are assigned to locations on the target device associated with the subset of Steiner points. The connections from each of the respective replicated instances of the first driver are assigned to a respective subset of the plurality of loads.

Abstract: A design tool with an initial sink locator unit determines a number of clock buffers for driving clock signals to loads in a clock distribution network. The design tool determines clusters of loads in the clock distribution network, wherein the number of clusters is equal to the number of clock buffers and the loads are uniformly distributed amongst the clusters. The design tool determines centers of the clusters as initial candidate sink locations for the clock buffers. The design tool iteratively determines new clusters and determines centers of the new clusters as optimized initial candidate sink locations.

Abstract: Roughly described, a method for synthesizing a circuit design from a logic design includes developing candidate solutions for a particular signal path, a first candidate solution identifying a first library cells followed immediately downstream thereof by a first set of zero or more buffers, and a second candidate solution identifying a second library cell followed immediately downstream thereof by a second set of zero or more buffers, the first library cell and first set of buffers in combination being different from the second library cell and second set of buffers in combination. The computer system selects among the candidate solutions at least in part in dependence upon sensitivity of the solution to load capacitance in the particular path, and stores the selected solution in the storage for subsequent use in further developing and fabricating an integrated circuit device.

Abstract: Computer implemented techniques are disclosed for fixing signal hold-time violations in semiconductor chips. Analysis includes estimation of hold-time requirements using ideal clocks. Allocation of placement regions within the design and near the macro circuits allows for later placement and wiring use during layout hold-time fixing. The placement region sizes are based on estimates of the needed buffers. Nets, within the design for detail routing, are ordered such that nets with hold-time violations are wired later, thus fixing hold-time violations without scaling or adding further buffers. Hold times are re-evaluated once wiring of track routes is complete.

Abstract: A technique for implementing an clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into consideration local capacitance distributions and conductor resistances. An AC-based sizing formulation is applied to the buffer and to the LC tanks so as to reduce the total buffer area. The technique is iterative and can be fully automated while also reducing clock distribution power consumption.

Abstract: A design tool with a direct current (DC) transformation analysis unit determines combinations of candidate sink locations for sector buffers within a sector of a clock network design. For each of the combination of candidate sink locations, the design tool transforms resistances of the sector with the combination of candidate sink locations into resistances of an electrical circuit. The design tool transforms capacitances of the sector with the combination of candidate sink locations into current sources of an electrical circuit. The design tool performs a DC circuit analysis, wherein results of the DC circuit analysis include a variance of voltage at nodes of the sector and a maximum value of current from currents flowing between pairs of the nodes of the sector. The design tool determines which of the combination of candidate sink locations has the minimum variance of voltage with the results of the DC circuit analysis.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: A design support apparatus includes a detecting unit, a determining unit, and an inserting unit. The detecting unit detects a via that connects wirings in a circuit to be designed that is expressed by layout information. The determining unit determines the connection position of a dummy via that does not connect wirings, to be on at least one of wirings connected to the via detected by the detecting unit. The inserting unit inserts the dummy via at the connection position determined by the determining unit.

Abstract: Technology is disclosed herein that provides for modifying a circuit design to reduce the potential occurrence of single event upset errors during operation of a device manufactured from the synthesized design. After a circuit design has been synthesized to a particular abstraction level, a static timing analysis procedure is run on the design. The slack values for paths within the design are determined based upon the static timing analysis procedure. Subsequently, delays are added to selected paths within the design based upon the slack values.

Abstract: A method of implementing a VLSI clock network is implemented. That method includes a step of generating an initial VLSI clock grid for incorporation on a silicon die. An input grid buffer is then sized and implemented for the VLSI clock grid. LC tanks are then placed and sized in the VLSI clock grid to implement a resonant tank clock grid and the input grid buffer is resized. A check of the resonant tank design criteria is then made. If the design criteria are met the resonant VLSI clock grid with its LC tanks is implemented. If not, another attempt at implementing a suitable LC tanks placement and sizing is made. The process iterates until a VLSI clock grid that meets the design criteria is obtained.

Abstract: A timing error removing method includes selecting a logic-level correction location and a first buffer to be inserted at the logic-level correction location, wherein the logic-level correction location and the first buffer are able to remove a timing error in a semiconductor integrated circuit to be designed; and searching for a vacant area in the semiconductor integrated circuit where the first buffer can be placed for the logic-level correction location, and if the vacant area is not found, further searching for a combination of a plurality of buffers smaller than the first buffer, the combination of the plurality of buffers being able to be placed in the semiconductor integrated circuit and being able to replace the first buffer in terms of a delay obtained as if the first buffer is inserted.

Abstract: A method of designing an integrated circuit, an EDA tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating a set of constraint equations representing clock-insertion delay values for the integrated circuit as variables, (2) determining bounds on each of the clock-insertion delay values based on the constraint equations and (3) generating a set of closing commands based on the bounds for driving a design of the integrated circuit to closure, wherein each step of the method is carried out by at least one EDA tool.

Abstract: Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation.

Abstract: Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.

Abstract: A method of manufacturing a system on a chip and a system on a chip including a set of pre-designed modules. These modules are place on a semiconductor and connecting by a set of busses formed according to a set of design rules specifying tracks having a minimum size of conductors and a minimum spacing between conductors. The busses are routed in a preferred direction. The busses include minimum size conductors at alternate tracks within a selected metal layer of the semiconductor and minimum size conductors at alternate tracks in a different metal layer. The conductors in the different metal layer are connected to corresponding connectors in the selected metal layer by vias. Shields of conductors not connected to the bus may be included in tracks not including bus conductors.

Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.

Abstract: An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and respective ones of a plurality of sink locations in the sector of the clock network design. The tool determines centers of the clusters of loads, and sink locations corresponding to the centers of the clusters for connecting output terminal points of sector buffers are determined. Each of the sector buffers drive a clock signal to a corresponding one of the clusters of loads.

Abstract: A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.

Abstract: A verification support apparatus includes a detecting unit that detects an inconsistency between a simulation result at an observation point in a circuit-under-test and an expected value; a setting unit that sets a portion of output values to logic values different from those of the simulation result when the detecting unit detects the inconsistency, wherein the output values are random values output from elements that receive a signal in a second clock domain that receives the signal from a first clock domain asynchronously; a comparing unit that compares the expected value and a simulation result at the observation point after the setting by the setting unit; and an identifying unit that identifies whether the portion of the output values are a cause of the inconsistency, based on a result of comparison by the comparing unit.

Abstract: In an LSI design method of designing a clock tree that supplies a clock signal to a plurality of leaves from a clock supply point, when a high level clock tree is constituted by H-tree and a low level clock tree is formed by CTS, the number of stages of a high level clock tree is optimized without giving any constraint on the placement of a low level clock tree. The leaves are divided into a plurality of groups to form a low level local tree. A clock-supplied region including all leaves to be supplied with a clock is uniformly divided and for each divided region, a skew when a clock signal is supplied from an end of an H-tree to start points of a plurality of local trees included in that region is estimated. The clock-supplied region is more finely equally-divided to increase the number of stages of H-tree.

Abstract: A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial signal. On chip, the serial signal is parallelized, decompressed, and then shifted into the scan chains. An inserted controller generates clocks and various control signals. Conventional test patterns from ATPG may be generated and applied during testing without the need to modify the ATPG program saving time and resources. Hierarchical testing of integrated circuits built with a multiplicity of cores, each having its own embedded compression logic, is also supported.

Abstract: The disclosure provides leakage power recovery that considers side transition times of multi-input cells. In one embodiment, a leakage power recovery system is disclosed that includes: (1) a power recovery module that considers side transitions when making a first conditional replacement of a cell in a path of a circuit design with a lower leakage cell and estimates delays and slack of the at least one path of the circuit design, and (2) a speed recovery module that makes a second conditional replacement of a slower lower leakage cell of the path with a higher leakage cell when there is a timing violation with respect to the path, determines if any other cells of the at least one path has a slower input transition and makes a third conditional replacement of a driver thereof to a higher leakage cell when the driver is one of the slower lower leakage cells.

Abstract: Apparatuses and methods for suppressing power supply noise harmonics are disclosed. A method includes selecting at least one flip-flop of a plurality of data paths of an integrated circuit based on a slack associated with the at least one flip-flop. The method also includes providing at least one delay circuit at an output of at least one flip-flop. The at least one delay circuit is configured to delay the output of the at least one flip-flop by a threshold clock cycle for managing current at a positive edge of a clock input and current at a negative edge of the clock input, thereby suppressing power supply noise harmonics of the integrated circuit.

Abstract: An integrated circuit (IC) chip having repeaters for propagating signals along relatively long wires that extend between and among lower-level physical blocks of the IC chip, wherein the repeaters are implemented as clocked flip-flops (or “repeater flops”). A method for automatically inserting and allocating such repeater flops during the logical and physical design of the IC chip is also provided.

Abstract: Latches and local-clock-buffers are automatically placed during integrated circuit physical synthesis. Prior to physically laying out the datapath, locations are assigned for the latches based on a logical representation of the datapath and on the fixed placements of pins. The computed latch locations optimize the datapath according to some predetermined criteria. Local-clock-buffers are also preplaced together with the latches further improving datapath performance.

Abstract: Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.

Abstract: Systems and techniques for incrementally updating Elmore pin-to-pin delays are described. During operation, an embodiment receives a representation of a physical topology of a routed net that electrically connects a driver pin to a set of load pins. The embodiment then computes a set of incremental Elmore delay coefficients based on the representation. Next, using the Elmore delay coefficients, the embodiment computes a set of delays based on the representation, wherein each delay in the set of delays corresponds to a delay between the driver pin and a corresponding load pin in the set of load pins. As load pin capacitances change during circuit optimization, the set of incremental Elmore delay coefficients can then be used to update the delays between the driver pin and the load pins in a very computationally efficient manner.

Abstract: Systems and methods are provided for designing integrated circuits using configurable delay cell (CDC) circuits that serve to expedite timing closure for an integrated circuit (IC) design by eliminating the need to iteratively repeat various design steps such as placement, signal distribution network synthesis, and routing. CDC circuits include footprint compatible circuits having different delay characteristics, which may be included as part of a standard cell library for designing integrated circuits. A CDC circuit can be used in an IC design to add a desired delay to a given clock path or data path, and then replaced with another footprint compatible CDC circuit to increase or decrease the delay in the given clock or data path to meet one or more timing requirements and achieve timing closure without having to repeat placement, signal distribution network synthesis or routing steps.

Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net and an aggressor net coupled together. For each timing arc in the timing graph, full timing delays may be computed for the timing arcs in each circuit stage.

Abstract: Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.

Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.

Abstract: A method for designing a system including optimizing path-level skew in the system and analyzing path-level skew in the system. Other embodiments are also disclosed.

Abstract: Aspects of the invention provide for spare latch distribution for an integrated circuit design. In one embodiment, aspects of the invention include a method of generating a computer system for spare latch distribution in an integration circuit design, the method including: providing a computer system operable to: receive design data for the integrated circuit design, the design data including a plurality of latches; segment the integrated circuit design into a plurality of equal sections; determine a latch density within each of the equal sections; and determine a number of spare latches, based on the latch density, for each of the equal sections. Further, it is understood that the above are performed for each clock domain within the integrated circuit design.

Abstract: In a particular embodiment, a method is disclosed that includes automatically adding a first power line in a channel between at least two macros when less than two system power supply lines with opposite polarities are detected within the channel.

Abstract: A method for automating input/output buffer information specification (IBIS) model generation. A wrapper utility combines components into an automated generation flow to model multiple input/output (I/O) buffers that conform to single-ended and differential I/O standards. Configuration data files are imported to properly configure the modeled I/O buffers according to a specific set of signal parameters across all process corners. Output and input termination impedance may also be modeled within the I/O buffer. A simulation setup file of the modeled I/O buffer is generated to determine the voltage/current (V/I) and voltage/time (V/T) data for the modeled I/O buffer for each process corner. A raw IBIS model is then created, formatted, and validated to determine the accuracy of the IBIS model. Execution steps of the IBIS model generator are then iterated to automatically generate, correlate, and compile IBIS models for each I/O standard into a single file.

Abstract: The invention concerns a computer implemented method of circuit conception of a clock tree (200) comprising: a plurality of pulse generators (202) each being coupled to the input of one or more pulsed latches and being arranged to generate a pulsed signal (PS); and a tree of buffers (204) for supplying a clock signal (CLK) to the pulse generators, the method comprising: the conception of the clock tree without pulse generators based on a timing analysis by the computer of the propagation of clock edges in the clock tree; and replacing by the computer in the clock tree at least one buffer, coupled to the input of each pulsed latch, by a pulse generator.

Abstract: Some embodiments provide techniques and systems for optimizing a circuit design's global leakage power. During operation, the system can determine leakage potentials for logic gates in the circuit design, such that a logic gate's leakage potential indicates an amount or degree by which the logic gate's leakage power is decreasable. The system can then determine a processing order for processing the logic gates based at least on the leakage potentials. Next, the system can optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order.

Abstract: A circuit analysis tool is provided for optimizing circuit clock operating frequency using useful skew timing analysis. The instructions supply clock signal with an optimized operating frequency. A first gate signal input slack time is determined with respect to the clock signal to the first gate. If the first gate signal input has a negative slack time, a delay is added to the first clock signal. A second gate signal input slack time is determined with respect to the clock signal to the second gate. If the second gate signal input slack time is negative, a delay is added to the second clock signal necessary to create a second gate signal input positive slack time. In response to the first and second gate signal input positive slack times, it is determined that the circuit successfully operates at the clock optimized operating frequency.