Patents Represented by Attorney, Agent or Law Firm Betty Formby
  • Patent number: 5651128
    Abstract: The integrated circuit memory has a matrix of cells and a plurality of circuits enabling the selective application, to the cells, of programming and erasure potentials. These circuits are controlled by an integrated state machine programmed to perform algorithms adapted to the operations to be performed. In order to facilitate the devising and perfecting of these algorithms, the memory includes selection means enabling an external tester to be substituted for the state machine. A particularly advantageous application is in "FLASH EEPROM" memories.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 22, 1997
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventor: Jean-Marie Gaultier
  • Patent number: 5649146
    Abstract: A circuit is provided for incrementing a current address of a circular buffer in an electronic memory by an increment to produce a next address including: an adder circuit for adding the current address to the increment and producing a first provisional next address; a circuit which causes the next address to be a base address plus an overshoot when the first provisional next address passes a limit address by a number equal to the overshoot, wherein for the calculation of the next address, there is provided an adder circuit including three adders receiving the current address, the increment and the limit address and producing a first and a second provisional next address and the difference between the first provisional next address and the limit address; and a selection circuit for selecting as the next address one of the two provisional next addresses, the selection being made upon the polarity of the difference between the first provisional next address and the limit address.
    Type: Grant
    Filed: March 30, 1995
    Date of Patent: July 15, 1997
    Assignee: SGS - Thomson Microelectronics S.A.
    Inventor: Marc Riou
  • Patent number: 5644267
    Abstract: A high-pass filter in particular for high-frequency applications and of the type comprising at least one input terminal (IN) and at least one output terminal (OUT) between which is defined a transfer function (FdT) and is inserted a biquadratic cell (18) incorporating a series of transconductance stages (2, 3, 4, 5) comprises a generator circuit (29) of variable currents (i.sub.K1, i.sub.K2) connected between a pair of stages (2, 3) of the biquadratic cell (18) and a voltage reference (GND). Said generator allows introduction of programmable zeroes in the transfer function (FdT) of the filter (20).
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: July 1, 1997
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Francesco Brianti, Roberto Alini, Valerio Pisati, Paolo Gadducci
  • Patent number: 5644216
    Abstract: In order to give the current the quality of low sensitivity to temperature, a first MOS transistor and a second MOS transistor supplied by a current mirror have their sources connected to the ground, with the drain and the gate of the first transistor being connected to the gate of the second transistor by means of a resistor. The quotient of the dimensional ratios of the transistors is equal to the coefficient of the current mirror and the transistors are doped so that the threshold of the second transistor is greater than that of the first one. Application notably to ramp generators for the programming of EEPROM cells.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: July 1, 1997
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventors: Joaquin Lopez, Jean-Michel Coquin
  • Patent number: 5644530
    Abstract: The disclosed device can be used to accelerate the tests carried out on memories by using a row and column address generator normally designed for operations of pre-erasure programming of the memory. The working in test mode is determined by a test word. During a test, row and/or column counters of the generator are selectively incremented by an incrementation signal given by a control unit that performs a pre-erasure programming operation. Application notably to FLASH EEPROM memories and the integrated circuits that incorporate these memories.
    Type: Grant
    Filed: April 7, 1995
    Date of Patent: July 1, 1997
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventor: Jean-Marie Bernard Gaultier
  • Patent number: 5640312
    Abstract: A power supply for a computer system having at least one energy demanding component. The power supply includes a transformer having a primary side coupled to an AC main and a secondary side coupled to an output line, a charging circuit coupled between the secondary side of the transformer and the output line, an optical switch coupled to the secondary side of the transformer and comprised of an optical transmitter and an optical receiver, a secondary side power switch coupled to the optical receiver, a pulse width modulator coupled to an output of the optical receiver and a transformer switch coupled to an output of the pulse width modulator. The pulse width modulator generates a pulse sequence which alternates between first and second states, each having respective durations and frequencies. At each change between the first and second states, the transformer switch selectively connects or disconnects the primary side of the transformer with the input line.
    Type: Grant
    Filed: September 13, 1995
    Date of Patent: June 17, 1997
    Assignee: Compaq Computer Corporation
    Inventor: Barry N. Carroll
  • Patent number: 5638330
    Abstract: An initialization circuit for memory registers, having a signal input being applied a supply voltage which rises linearly from a null value, and an initializing output connected to an input of a memory register and on which a voltage signal, being equal or proportional to the supply voltage, during the initialization step, and a null voltage signal, upon the supply voltage dropping below a predetermined tripping value, are produced. Additionally, the circuit has, between the input and the output, a first circuit portion connected to the input; a second circuit portion connected after the first and having a first output connected to the initializing output; and a third, inverting circuit portion having an input connected to a second output of the second portion and an output connected to the first portion to hold off that first portion while the supply voltage drops below the threshold voltage.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: June 10, 1997
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Pierangelo Confalonieri, Germano Nicollini
  • Patent number: 5636142
    Abstract: The invention relates to a digital processing circuit comprising a host interface (7) which provides access from the processing circuit's bus (6) to an external data processing system (8). The processing circuit is broken down into blocks (1, 2, 3) with test registers (4, 5) interposed between an upstream block and a downstream block. The test registers (4, 5) are connected to the bus (6) and identified by an address allowing data to be sent to them or read from them.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: June 3, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Oswald Colavin
  • Patent number: 5636112
    Abstract: An internal AC adapter which incorporates a space efficient EMI filter is positioned within a main chassis portion of a portable personal computer having at least one energy-demanding component also positioned within the main chassis portion. The internal AC adapter, which converts alternating current received from an alternating current main to direct current for transmission to the energy-demanding components, includes a first connector for electrically connecting the internal AC adapter to the alternating current main, a bridge rectifier circuit having an AC input side electrically connected to the first connector and a DC output side and a space efficient electromagnetic interference filter having an input side electrically connected to the DC output side of the bridge rectifier circuit and an output side. The bridge rectifier circuit converts alternating current received from the first connector to direct current for transmission to the electromagnetic interference filter.
    Type: Grant
    Filed: July 13, 1995
    Date of Patent: June 3, 1997
    Assignee: Compaq Computer Corporation
    Inventor: Richard A. Faulk
  • Patent number: 5636109
    Abstract: A power supply for a computer system includes a transformer having a primary side coupled to an AC main and a secondary side coupled to an output line, a charging circuit coupled between the secondary side of the transformer and the output line, an optical switch coupled to the secondary side of the transformer and comprised of an optical transmitter and an optical receiver, a secondary side power switch coupled to the optical receiver, a short circuit protection circuit coupled to the charging circuit, the output line and the optical receiver, a pulse width modulator coupled to an output of the optical receiver and a transformer switch coupled to an output of the pulse width modulator. The pulse width modulator generates a pulse sequence which alternates between first and second states, each having respective durations and frequencies. At each change between the first and second states, the transformer switch selectively connects or disconnects the primary side of the transformer with the input line.
    Type: Grant
    Filed: September 13, 1995
    Date of Patent: June 3, 1997
    Assignee: Compaq Computer Corporation
    Inventor: Barry N. Carroll
  • Patent number: 5635868
    Abstract: A circuit to limit the maximum current passed from a power transistor (T'p) to a load (ZL) which is connected to an output terminal of the transistor. The circuit includes an error amplifier (1'), a driver circuit (P') for the transistor (T'p), and a current detector for detecting the current (IL) flowing through the load (ZL). The current detector is provided with at least first and second terminals, includes a circuit block (2) having an input terminal connected to the control terminal of (T'p) and an output terminal connected to the current generator internal to the amplifier (1'), one input (B') of the amplifier (1') being connected to the first terminal of (Rs) and the other input (A') connected to the second terminal of (Rs). The introduction of the circuit block lowers the open-loop system gain making it stable and producing a smooth reduction of any rise in the load current (IL).
    Type: Grant
    Filed: August 11, 1994
    Date of Patent: June 3, 1997
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Natale Aiello, Sergio Palara, Salvatore Scaccianoce
  • Patent number: 5631588
    Abstract: A power stage of quasi-complementary symmetry, including a common-source FET and a common-drain FET, with a reduced absorption of current under the conditions of high impedance of the output. The driving node of the upper (common-drain) transistor from is decoupled from the output node of the stage, preventing the current generator Id, which discharges the control node, from absorbing current from the load connected to the output stage, during a phase of high output impedance. This is preferably realized by using a field effect transistor which has its gate connected to the output node of the stage, and is connected to provide the current drawn from the discharge generator of the driving node of the upper common-drain transistor, absorbing it from the supply node VDD instead of absorbing it from the voltage overdriven node Vb. This alternative solution avoids excessive loading of the high-voltage supply, and is particularly useful when the overdriven node Vb drives multiple output stages.
    Type: Grant
    Filed: April 29, 1994
    Date of Patent: May 20, 1997
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventor: Luca Bertolini
  • Patent number: 5631177
    Abstract: A manufacturing process for an integrated circuit which includes at least one vertical-current-flow MOS transistor. The patterned photoresist which screens the body implant is also used to mask the etching of a nitride layer over a pad oxide. After the photoresist is cleared, the nitride pattern is transferred into the oxide, and the resulting oxide/nitride stack is used to mask the source implant. The nitride/oxide stack is then removed, the gate oxide is grown, and the gate layer is then deposited.
    Type: Grant
    Filed: January 30, 1995
    Date of Patent: May 20, 1997
    Assignees: SGS-Thomson Microelectronics, S.r.l., Consorzio per la Ricerca sulla Microelecttronica nel Mezzogiorno
    Inventor: Raffaele Zambrano
  • Patent number: 5631551
    Abstract: A bandgap voltage reference circuit employs a Vbe voltage multiplier network in a feedback line of an output amplifier of the bandgap reference circuit, thus permitting to independently fix the output voltage that is produced and the temperature coefficient thereof. A voltage reference having a linear negative temperature coefficient in an extended temperature variation range may be obtained, starting from a bandgap reference voltage with a positive temperature coefficient.
    Type: Grant
    Filed: December 1, 1994
    Date of Patent: May 20, 1997
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Salvatore Scaccianoce, Sergio Palara, Natale Aiello
  • Patent number: 5629574
    Abstract: A control interface device for an electric motor, particularly an electric motor for operating servomechanisms on a vehicle, which includes a conductor frame, an active integrated component mounted on the conductor frame, and a plurality of electric connectors. A single insulating, one-piece enclosing body contains the conductor frame with the active integrated component and the electric connectors included to the conductor frame. Thus, all of the elements required for powering and controlling the motor are gathered inside a single enclosing body which is convenient to handle and connect.
    Type: Grant
    Filed: June 30, 1993
    Date of Patent: May 13, 1997
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Carlo Cognetti, Giuseppe Marchisi
  • Patent number: 5629558
    Abstract: A diode integrated on semiconductor material with BCD technology and of the type provided on a substrate having a first type of conductivity inside an isolation region having a second type of conductivity. The diode comprises also a buried anode region having a first type of conductivity and a cathode region having a second type of conductivity. The cathode region comprises an epitaxial layer located above the buried anode region and a highly doped region provided inside the epitaxial layer. The buried anode region comprises depressions opposite which is located the highly doped region with the depressions being achieved by the intersection of lateral diffusions of distinct and adjacent portions of the buried anode region.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: May 13, 1997
    Assignee: SGS-Thomson Microelectronics, S.rl
    Inventors: Paola Galbiati, Ubaldo Mastromatteo
  • Patent number: 5622876
    Abstract: A monolithically integrated, transistor bridge circuit of a type suiting power applications, comprises at least one pair of IGBT transistors (M1 , M2) together with vertically-conducting bipolar junction transistors transistors (T1, T2). These IGBT transistors are laterally conducting, having drain terminals (9, 19) formed on the surface of the integrated circuit (1), and through such terminals, they are connected to another pair of transistors (T1, T2) of the bipolar type.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: April 22, 1997
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Raffaele Zambrano, Sergio Palara
  • Patent number: 5623220
    Abstract: A zero-crossing circuit and method, in which the sign of inputs to a comparator is reversed after each zero crossing of the input signal. This means that delay introduced by the comparator does not affect the duty cycle of the output signal, so precision synchronization remains possible.
    Type: Grant
    Filed: September 13, 1994
    Date of Patent: April 22, 1997
    Assignee: SGS-Thomson Microelectonics, S.r.l.
    Inventors: Giorgio Betti, Paolo Gadducci, David Moloney
  • Patent number: 5622879
    Abstract: The invention relates to a novel electrically programmable and erasable memory cell.The cell comprises a single transistor, which is a floating gate transistor and has no selection transistor. Means are provided for establishing a high capacitive coupling between the drain (12) and the floating gate (18). The capacitive coupling between the source (10) and the floating gate is low, as is normally the case. Preferably, the control gate (22) only partly covers the floating gate (18). Another part of the floating gate is covered by a semiconductor layer (26) connected to the drain. It is the latter layer which establishes the high capacitive coupling according to the invention. Programming can then take place by the Fowler-Nordheim effect with the source under high impedance, i.e. without hot electron effect.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: April 22, 1997
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventor: Jean Devin
  • Patent number: RE35494
    Abstract: An integrated, low-pass filter of the first order made using the switched capacitors technique utilizes advantageously a single switched capacitor and only two switches in contrast to the filters of the prior art which utilize two switched capacitors and four switches. The filter of the invention requires a smaller integration area and moreover exhibits a greater precision of its DC gain.
    Type: Grant
    Filed: May 2, 1994
    Date of Patent: April 22, 1997
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventor: Germano Nicollini