Abstract: The etch resistance of a casein-based photoresist pattern to low specific gravity ferric chloride-based etchant solutions is increased by treating the photoresist pattern with a methylene blue solution, containing at least 0.1 weight percent methylene blue, prior to exposure to the etchant solution.
Abstract: Wafers have material removed from them in processes such as lapping or polishing without the use of hold down adhesives to secure the wafers to a wafer mounting plate. The front side of a polymeric mounting pad on a wafer mounting plate is moistened with a liquid, the wafers are rendered shedding of that liquid and substantially free of adhesion diminishing particles and powder and are mounted on the moistened mounting pad. It is critical that the wafers shed the liquid with which the pad is moistened. The wafers are pressed firmly against the mounting pad in order to assure their continued adhesion to the pad during the material removal process. The wafer mounting plate is then mounted in the lapping, polishing or other material removal machine and the wafers lapped or polished in a normal manner. After completion of the desired material removal the wafers may be removed from the mounting pad with tweezers or by floating the wafers off the mounting pad.
Abstract: A non-polluting, non-pyrolytic process to increase the electrical energy derived from coal comprises the reacting of coal with water at a sufficient temperature to form carbon monoxide and hydrogen with the further processing of the carbon monoxide to formate and the reacting of the formate and the hydrogen in separate fuel cells to generate electric current, water, and hydroxide, wherein the water and the hydroxide are recycled back into the initial coal-water reaction and the carbon monoxide-hydroxide reaction to provide further feedstocks for electrical power generation. Since the process does not involve combustion, the common air-pollutants, such as oxides of nitrogen and linear and aromatic carbonaceous free radicals, are not released into the atmosphere.
Abstract: A diffusion furnace having particular utility in the processing of SOS devices wherein a temperature gradient, per unit length of furnace tube, is provided at a section of a reaction tube extending between the furnace and the scavenger and load-unload chambers in order to minimize the thermal shock to which a sapphire wafer may be subject, either at the commencement of processing when the wafer is first introduced into the furnace or at the conclusion of the processing as the wafer is being withdrawn from the furnace.
Abstract: Partially devitrified porcelain compositions are provided which are comprised of a mixture, based on its oxide content, of barium oxide (BaO), magnesium oxide (McO) or a mixture of magnesium oxide with certain other oxides, boron trioxide (B.sub.2 O.sub.3) and silicon dioxide (SiO.sub.2). In accordance with this invention the porcelain compositions are applied to the metal core and fired to provide a partially devitrified porcelain coating on the metal core. The coating has a very low viscosity at its initial fusion point and then almost instantaneous high viscosity due to partial devitrification. The fired coating has a deformation temperature of at least 700.degree. C. and a high coefficient of thermal expansion of at least about 110.times.10.sup.-7 /.degree.C.
Abstract: A method of depositing a layer of semi-insulating gallium arsenide on a substrate by vapor phase epitaxy. The layer is deposited by thermally decomposing a gaseous mixture of arsine, gallium chloride and a small amount of water vapor to deposit a layer of gallium arsenide doped with oxygen.
Abstract: A structure for passivating semiconductor material comprises a substrate of crystalline semiconductor material, a relatively thin film of carbon disposed on a surface of the crystalline material, and a layer of hydrogenated amorphous silicon deposited on the carbon film.
Abstract: An improved gate injected, floating gate memory device is described having improved charge retention and endurance characteristics is described in which the barrier height for the injection of charge (electrons or holes) into the floating gate is reduced. This is accomplished by utilizing a layer of semi-insulating polycrystalline silicon between the control electrode and the insulating layer over the floating gate.
Abstract: A semiconductor power device comprises a semiconductor pellet having first and second opposing major surfaces, including, in series, emitter, base and collector regions forming a PNP transistor. The collector region is substantially planar and adjacent to the second surface; the base region is adjacent to the collector region and extends to the first surface; and the emitter region extends into the pellet from the first surface such that it is substantially surrounded by the base region. The emitter region substantially surrounds a substantially centrally located extension of the base region which also terminates at the first surface. Emitter, base and collector electrodes are ohmically disposed on the respective semiconductor regions and a Schottky barrier contact is formed on the base region extension, the Schottky contact being connected to the emitter electrode.
Type:
Grant
Filed:
July 3, 1980
Date of Patent:
February 24, 1981
Assignee:
RCA Corporation
Inventors:
John A. Olmstead, Sebastian W. Kessler, Jr.
Abstract: A method for making low leakage N-channel silicon-on-sapphire (SOS) transistor is described. The transistor has reduced edge leakage as a result of acceptor ion impurities introduced into the edges of the silicon islands on which the transistor is formed. The acceptor impurities are introduced into the epitaxial silicon layer immediately before etching the layer to produce the islands. The impurities are then diffused under the edge of the masking layer prior to the removal of the portions of the silicon epitaxial layer, and leaving the edges of the islands more heavily doped than the surface of the island.
Abstract: Thin, stable, low surface energy perfluorinated polymer films can be applied to a substrate by glow discharging the substrate in the presence of a perfluorocycloalkane or -cycloolefin or perfluoroalkyl-substituted derivatives thereof.
Abstract: Homopolymers of 1-aza-5-acryloxymethyl-3,7-dioxa-bicyclo[3.3.0]octane are useful as resists for recording information patterns having high sensitivity and excellent contrast between exposed and unexposed areas.
Type:
Grant
Filed:
November 13, 1978
Date of Patent:
February 24, 1981
Assignee:
RCA Corporation
Inventors:
Richard J. Himics, Michael Kaplan, Nitin V. Desai
Abstract: A crucible for containing a melt and die for EFG growth of sapphire is supported by a pyrolytic graphite crucible support plate having the C axis of the pyrolytic graphite perpendicular to the bottom of the crucible which is supported by the plate. This thermally insulates the crucible from the pedestal which supports the support plate.
Type:
Grant
Filed:
May 14, 1979
Date of Patent:
February 17, 1981
Assignee:
RCA Corporation
Inventors:
Samuel Berkman, Robert Metzl, Richard E. Novak, David L. Patterson
Abstract: A method of rounding a sharp semiconductor projection jutting out from a principal body of semiconductor material comprises the step of irradiating the projection with a laser pulse having an energy density of less than about 1.5 joules/cm.sup.2.
Abstract: A planar semiconductor device having a cathode region surrounding an anode region is flip chip mounted to a conductor film circuit. An anode contact extends from the anode region and is bonded to a first portion of the conductor film circuit such that that portion of the cathode region which overlaps the first portion of the conductor film circuit is minimized. That portion of the cathode region distal from the anode region is relatively wide, and a relatively large area cathode contact extends from the cathode region and is bonded to a second portion of the conductor film circuit.
Abstract: A method for protecting electronic circuitry formed on the obverse side of a wafer from flying debris produced either by the mechanical or laser scribing or scoring of the wafer and during separation. The device is provided with a layer of abrasion resistant material on the circuit side of the wafer and the scribing or scoring is done on the obverse side of the wafer. The cracking operation is performed by applying pressure to the wafer in such a manner as to have the reverse side in tension and the obverse or circuit side in compression in order to prevent any debris which may have been cast up during the scribing or scoring operation from contaminating or damaging the circuit side of the wafer while any debris cast up during the breaking operation is thrown away from the obverse or circuit side.
Abstract: The invention is a memory device which includes a metal-nitride-oxide semiconductor (MNOS) insulated gate field effect transistor (IGFET) which is built in series with the base of a bipolar transistor to provide both bipolar current handling capability and bipolar radiation hardness while retaining MNOS memory performance.
Abstract: A method of lapping the sharp point of a hard material using a silicon oxide, glow discharge deposited abrasive layer wherein the abrasive layer is thick enough to prevent penetration of the point into the substrate.
Abstract: The basewidth of a lateral, bipolar transistor is markedly reduced by first forming a layer of polycrystalline silicon over an oxide coated substrate. By utilizing a process for doping the exposed edges of the patterned polysilicon layer, a narrower basewidth dimension is achieved than heretofore possible with photolithographic techniques.
Abstract: An ablative recording medium comprises a substrate coated with a light reflecting layer which in turn is coated with a light absorptive layer of di-indeno[1,2,3-cd:1',2',3'-lm]perylene. During recording, portions of the light absorptive layer are ablated by a modulated focussed light beam, thereby exposing portions of the reflecting layer. Video information is recorded as a reflective-antireflective pattern.