Abstract: This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage.

Abstract: An integrated mass flow sensor is manufactured by a process of carrying out a micro-machining process on an N or P-type silicon substrate with orientation <100>. This mass flow sensor comprises a central thin-film heater and a pair of thin-film heat sensing elements, and a thermally isolated membrane for supporting the heater and the sensors out of contact with the substrate base. The mass flow sensor is arranged for integration on a same silicon substrate to form a one-dimensional or two-dimensional array in order to expand the dynamic measurement range. For each sensor, the thermally isolated membrane is formed by a process that includes a step of first depositing dielectric thin-film layers over the substrate and then performing a backside etching process on a bulk silicon with TMAH or KOH or carrying out a dry plasma etch until the bottom dielectric thin-film layer is exposed.

Abstract: This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of the RC network to prepare for carrying out a wafer-level measurement calibration of the semiconductor power device. The method further includes a step of connecting a probe card to a set of contact pads on the semiconductor wafer for carrying out the wafer-level measurement calibration followed by performing a gate resistance Rg measurement for the semiconductor power chips.

Abstract: A MOSFET device that includes a first Zener diode connected between a gate metal and a drain metal of said semiconductor power device for functioning as a gate-drain (GD) clamp diode. The GD clamp diode includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above the MOSFET device, having an avalanche voltage lower than a source/drain avalanche voltage of the MOSFET device wherein the Zener diode is insulated from a doped region of the MOSFET device for preventing a channeling effect.

Abstract: This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device.

Abstract: An image display system includes a reflecting screen that has a reflecting surface. The reflecting surface includes micro-ridges having a plurality of reflecting ridge-surfaces wherein the reflecting ridge-surfaces constituting a Fresnel mirror whereby the reflecting ridge-surfaces reflecting parallel reflecting light beams for all incident light beams projected from a light source located at a focal point of the Fresnel mirror. The micro-ridges further include a plurality of darkened ridge-surfaces with reduced reflectance for reducing ambient reflections. The micro-ridges further constitute a continuous concentric ridge having the reflecting ridge-surfaces facing a bottom direction toward the focal point of the Fresnel mirror for disposing a light source near a bottom location of the projecting screen. The continuous concentric ridge further has reduced reflectance ridge-surfaces facing a top direction away from the focal point of the Fresnel mirror.

Abstract: A switching device includes a high-side MOSFET chip having a first high-side source connected to a low-side drain of a low-side MOSFET chip. The switching device further includes a transient reverse current diversion circuit connected to a drain of the low side MOSFET chip for diverting a reverse transient current therethrough whereby a reverse transient current in turning off the low side MOSFET chip is diverted from passing through a body diode of the low side MOSFET chip reducing a transient ringing oscillation. The reverse transient current diversion circuit includes a diode for conducting the reverse transient current from the drain. The reverse transient current diversion circuit further includes a capacitor connected between the diode and a source of the low side MOSFET chip.

Abstract: An image display system includes a light source for projecting an illumination light. The image display system further includes a light source control unit that controls the light source to adjust the illumination intensity and/or light emission time of the illumination light. The display system further includes an SLM (Spatial Light Modulator) having a plurality of pixel elements. The SLM modulates the incident illumination light to generate gray scales. The light source control unit controls the light source during at least one time slice in one frame period, and the SLM uses that time slice to control a minimum adjustable gray scale.

Abstract: This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric liner layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate.

Abstract: This invention discloses a circuit trimming system that includes a one-time programmable memory (OTP). The OTP further includes a forward biased trim device connected between a voltage supply Vcc and a ground voltage wherein the Vcc having a reduced voltage substantially lower than a trimming voltage for a reversed biased device at ten volts or higher. The OTP further includes a drive circuit provided to select the OTP at a low current operating condition and for turning on a high trim current through the forward biased trim device for trimming and programming the OTP. The trimming system further includes a sense circuit connected across the forward biased trim device is for sensing a current and voltage of the forward biased trim device.

Abstract: A method is used for configuring an electronic device to reduce a skew of a parameter. The method includes a step of incorporating a plurality of controllable built-in parameter variation adjusting circuits for effecting a small step-change in the parameter at different points of the electronic device for reducing said skew of the parameter. A specific example of the method is to incorporate one or a plurality of field programmable gate arrays for reducing the skew of time delays. Another method is using the capability of programmable data path and loading of FPGA to create programmable delay line and controllable delays.

Abstract: The present invention discloses a pixel display configuration by providing a voltage controller in each pixel control circuit for controlling the voltage inputted to the pixel electrodes. The controller includes a function of multiplexing the voltage input to the pixel electrodes and also a bit buffering and decoupling function to decouple and flexible change the input voltage level to the pixel electrodes. The rate of DC balancing can be increased to one KHz and higher to mitigate the possibility of DC offset effects and the image sticking problems caused by slow DC balancing rates. This invention further discloses an enabling technology for switching from one DC balance state to another without rewriting the data onto the panels. Therefore, it is not required to implement a high voltage CMOS designs and standard CMOS technologies can be applied to manufacture the storage cells and control panel for the LCOS displays with lower production cost and higher yields.

Abstract: A circuit and method for controlling a MOSFET based switch that includes two back-to-back FET to block current flow in the OFF state irrespective of the polarity of the voltage differential across the switch. The MOSFET based switch further has a built-in current limit function by sensing the current flow through one of the two MOSFET switches. Furthermore, the bilateral current-limited switch further includes circuitry required for controlling both P type and N type FET in either common drain or common source configuration.

Abstract: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one active cell further includes a trenched source contact opened between the trenches wherein the trenched source contact opened through a source region into a body region for electrically connecting the source region to a source metal disposed on top of an insulation layer wherein a trench bottom surface of the trenched source contact further covered with a conductive material to function as an integrated Schottky barrier diode in said active cell. A shielding structure is disposed at the bottom and insulated from the trenched gate to provide shielding effect for both the trenched gate and the Schottky diode.

Abstract: A semiconductor power device includes a circuit to provide a gate signal wherein the gate signal has a negative temperature coefficient of gate driving voltage for decreasing a gate driving voltage with an increase temperature whereby the semiconductor power device has a net Ids temperature coefficient that is less than or equal to zero. In an exemplary embodiment, the gate voltage driver includes a diode that has a negative forward voltage temperature coefficient connected between a gate and a source of the semiconductor power device. In another embodiment, the gate voltage is integrated with the semiconductor power device manufactured as part of an integrated circuit with the semiconductor power device.

Abstract: The present invention discloses a pixel display configuration by providing a voltage controller in each pixel control circuit for controlling the voltage inputted to the pixel electrodes. The controller includes a function of multiplexing the voltage input to the pixel electrodes and also a bit buffering and decoupling function to decouple and flexible change the input voltage level to the pixel electrodes. The controller further includes a first switching stage and a second switching stage and each stage has a P-type transistor and a N-type transistor to expand the range of the switching voltages such that the improvement of the pixel control is further enhanced. The rate of DC balancing can be increased to one KHz and higher to mitigate the possibility of DC offset effects and the image sticking problems caused by slow DC balancing rates. This invention further discloses an enabling technology for switching from one DC balance state to another without rewriting the data onto the panels.

Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells and a junction barrier Schottky (JBS) area. The semiconductor power device includes the JBS area that further includes a plurality of Schottky diodes each having a PN junction disposed on an epitaxial layer near a top surface of a semiconductor substrate wherein the PN junction further includes a counter dopant region disposed in the epitaxial layer for reducing a sudden reversal of dopant profile near the PN junction for preventing an early breakdown in the PN junction.

Abstract: A method for configuring a testing system that includes a step of connecting a commercially available computer (CACMP) for directly controlling transmission of a plurality of test vectors to a test head. The method further includes a step of connecting a test vector memory between the CACMP and the formatter unit (FTM) with response unit (RP) for providing a required data width for storing the test vectors therein.

Abstract: The present invention includes a chip-embedded support-frame wrapped-by-flex-circuit package assembly. The package assembly includes a flex circuit having a plurality of patterned connecting-traces. The package assembly further includes a plurality of semiconductor chips mounted on the flex circuits wherein the semiconductor chips having a plurality of contact terminals connected to corresponding connecting traces on the flex circuit. The package assembly further includes a support frame-board having an edge surface placed along predefined folded lines on the flex circuit. The frame-board has a plurality of open spaces for disposing each of the semiconductor chips therein. The flex circuit is provided for folding onto the support frame along the predefined folded lines to form the chip-embedded support-frame wrapped-by-flex-circuit package.

Abstract: This invention discloses a junction barrier Schottky device supported on a substrate that has a first conductivity type. The Schottky device includes a first diffusion region of a first conductivity type for functioning as a forward barrier height reduction region. The Schottky device further includes a second diffusion region of a second conductivity type disposed immediately adjacent to the first diffusion region for functioning as a backward blocking enhancement region to reduce the backward leakage current.