Patents Represented by Attorney, Agent or Law Firm Bo-In Lin
  • Patent number: 7826126
    Abstract: The present invention provides a projection apparatus comprising: a light source, a light source control unit for controlling the output of the light source; at least one spatial light modulator for modulating the illumination light from the light source by multiple pixel elements; and an optical system for projecting, onto a screen, the illumination light deflected by the spatial light modulator, wherein: the light source control unit 1) modulates the output of the illumination light from the light source during a modulation period of the spatial light modulator, and 2) non-linearly controls the gray scale of an image projected onto the screen.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: November 2, 2010
    Assignees: Silicon Quest Kabushiki-Kaisha, Olympus Corporation
    Inventors: Hirokazu Nishino, Yoshiaki Horikawa, Akira Shiral, Fusao Ishii
  • Patent number: 7825431
    Abstract: A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: November 2, 2010
    Assignee: Alpha & Omega Semicondictor, Ltd.
    Inventors: Anup Bhalla, Xiaobin Wang, Wei Wang, Yi Su, Daniel Ng
  • Patent number: 7824977
    Abstract: A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage transistor with the high-voltage low-voltage decoupling layer etched off for further performance of a low-voltage manufacturing process thereon. The high-voltage low-voltage decoupling layer comprising a high temperature oxide (HTO) oxide layer of about 30-150 Angstroms and a low-pressure chemical vapor deposition (LPCVD) nitride layer.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: November 2, 2010
    Assignee: Alpha & Omega Semiconductor, Ltd.
    Inventors: YongZhong Hu, Sung-Shan Tai
  • Patent number: 7826128
    Abstract: The present invention provides a projection apparatus, comprising: a light source for emitting illumination light; at least one spatial light modulator with a plurality of movable mirrors corresponding to pixels to be displayed, for performing a modulation of the illumination light through operation of the movable mirrors; a light source control unit performing a modulation control of the light source; and a spatial light modulator control unit generating, from an input image signal, a control signal for driving the spatial light modulator, wherein: the light source control unit adjusts a pulse emission frequency of an emission pulse of the illumination light emitted from the light source while corresponding to an oscillation frequency of the movable mirrors.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: November 2, 2010
    Assignees: Silicon Quest Kabushiki-Kaisha, Olympus Corporation
    Inventors: Akira Shirai, Hirokazu Nishino, Yoshiaki Horikawa, Fusao Ishii
  • Patent number: 7816729
    Abstract: A trenched semiconductor power device that includes a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells in an active cell area and extending as trench-gate fingers to intersect with a trenched gate under the gate metal runner at a termination area. At least one of the trench-gate fingers intersects with the trenched gate under the gate metal runner near the termination area having trench intersection regions vulnerable to have a polysilicon void and seam developed therein.
    Type: Grant
    Filed: September 10, 2006
    Date of Patent: October 19, 2010
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7817330
    Abstract: A projection apparatus includes a light source for emitting a light including at least two different wavelengths; a light source control circuit for controlling a light source to emit the light as pulse emissions with a pulse modulation control; at least two spatial light modulators each comprises plurality of pixel elements are arranged in an array; a spatial light modulator control circuit for selectively controlling a modulation state of the respective pixel elements in each of the spatial light modulators in accordance with image data corresponding to the respective pixel elements; and the light source control circuit controls the light source so that a starting time of a pulse emission period of the pulse emissions of at least one of the wavelengths emitted from the light source is different from a modulation control timing of the pixel element of the spatial light modulator.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: October 19, 2010
    Assignees: Silicon Quest Kabushiki-Kaisha, Olympus Corporation
    Inventors: Kazuma Arai, Yoshihiro Maeda, Fusao Ishii
  • Patent number: 7812409
    Abstract: A trenched semiconductor power device that includes a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells wherein the layout of the trenched gate surrounding the transistor cells as closed cells having truncated corners or rounded corners. In an exemplary embodiment, the closed cells further includes a contact metal to contact a source and a body regions wherein the contact metal the trenched gate surrounding the transistor cell have a uniform space between them. In another exemplary embodiment, the semiconductor power device further includes a contact dopant region disposed below the contact metal to enhance an electrical contact between the metal contact and the source region and the body region, and the contact dopant region having substantially circular shape to achieve a uniform space between the contact dopant region and the trenched gate surrounding the closed cells.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: October 12, 2010
    Assignee: Force-MOS Technology Corp.
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7805687
    Abstract: A method of performing a programming, testing and trimming operation is disclosed in this invention. The method includes a step of applying a programming circuit for programming an OTP memory for probing and sensing one of three different states of the OTP memory for carrying out a trimming operation using one of the three states of the OTP memory whereby a higher utilization of OTP memory cells is achieved. Selecting and programming two conductive circuits of the OTP into two different operational characteristics thus enables the storing and sensing one of the three different states of the OTP memory. These two conductive circuits may include two different transistors for programming into a linear resistor and a nonlinear resistor with different current conducting characteristics. The programming processes include application of a high voltage and different programming currents thus generating different operational characteristics of these two transistors.
    Type: Grant
    Filed: September 30, 2006
    Date of Patent: September 28, 2010
    Assignee: Alpha & Omega Semiconductor, Ltd.
    Inventors: YongZhong Hu, Yu Cheng Chang, Sung-Shan Tai
  • Patent number: 7797997
    Abstract: This invention discloses a mass flow sensor manufactured by applying the micro-electromechanical system (MEMS) process to provide a new and improved mass flow sensor that is a self-calibrated in a time-of-flight manner with configuration to measure the flow velocity directly. The self-calibration of a mass flow rate sensor is achieved by providing an electric pulse to a heater in the flow and determining a temperature variations of the fluid. The method further includes a step of measuring a temperature variation by a temperature sensor disposed at a short distance from the heater. The method further includes a step of correlating the temperature variation measured at the temperature sensor with the temperature variation of the heater to determine a time delay and a corresponding flow velocity.
    Type: Grant
    Filed: August 24, 2008
    Date of Patent: September 21, 2010
    Assignee: Siargo Inc.
    Inventors: Xiaozhong Wu, Liji Huang
  • Patent number: 7800185
    Abstract: A semiconductor power device includes a plurality of closed N-channel MOSFET cells surrounded by trenched gates constituting substantially a square or rectangular cell. The trenched gates are further extended to a gate contact area and having greater width as wider trenched gates for electrically contacting a gate pad wherein the semiconductor power device further includes a source region disposed only in regions near the trenched gates in the closed N-channel MOSFET cells and away from regions near the wider trenched gate whereby a device ruggedness is improved. The source region is further disposed at a distance away from a corner or an edge of the semiconductor power device and away from a termination area. The semiconductor device further includes multiple trenched rings disposed in a termination area opposite the active area and the trenched rings having a floating voltage. The closed N-channel MOSFET cells are further supported on a red phosphorous substrate.
    Type: Grant
    Filed: January 28, 2007
    Date of Patent: September 21, 2010
    Assignee: Force-MOS Technology Corp.
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7796321
    Abstract: A spatial light modulator supported on a device substrate includes a plurality of light modulation elements to modulate a light emitted from a light source. The spatial light modulator and the device substrate further comprises a cyclic structure on a surface of the spatial light modulator and/or the device substrate for preventing a reflection of the incident light from the cyclic structure. In an exemplary embodiment the cyclic structure includes cyclic structural elements having a distance between two cyclic elements shorter than the wavelength of an incident light for preventing a reflection of the incident light from the cyclic structure.
    Type: Grant
    Filed: May 31, 2008
    Date of Patent: September 14, 2010
    Assignees: Silicon Quest Kabushiki-Kaisha, Olympus Corporation
    Inventors: Hirotoshi Ichikawa, Yoshihiro Maeda, Fusao Ishii
  • Patent number: 7795987
    Abstract: A transient voltage suppressing (TVS) circuit with uni-directional blocking and symmetric bi-directional blocking capabilities integrated with an electromagnetic interference (EMI) filter supported on a semiconductor substrate of a first conductivity type. The TVS circuit integrated with the EMI filter further includes a ground terminal disposed on the surface for the symmetric bi-directional blocking structure and at the bottom of the semiconductor substrate for the uni-directional blocking structure and an input and an output terminal disposed on a top surface with at least a Zener diode and a plurality of capacitors disposed in the semiconductor substrate to couple the ground terminal to the input and output terminals with a direct capacitive coupling without an intermediate floating body region.
    Type: Grant
    Filed: June 16, 2007
    Date of Patent: September 14, 2010
    Assignee: Alpha & Omega Semiconductor, Ltd.
    Inventor: Madhur Bobde
  • Patent number: 7790549
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: September 7, 2010
    Assignee: Alpha & Omega Semiconductor, Ltd
    Inventor: François Hébert
  • Patent number: 7786531
    Abstract: This invention discloses a new trenched vertical semiconductor power device that includes a capacitor formed between a conductive layer covering over an inter-dielectric layer disposed on top of a trenched gate. In a specific embodiment, the trenched vertical semiconductor power device may be a trenched metal oxide semiconductor field effect transistor (MOSFET) power device. The trenched gate is a trenched polysilicon gate and the conductive layer is a second polysilicon layer covering an inter-poly dielectric layer disposed on top of the trenched polysilicon gate. The conductive layer is further connected to a source of the vertical power device.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: August 31, 2010
    Assignee: Alpha & Omega semiconductor Ltd.
    Inventors: Sik K. Lui, Anup Bhalla
  • Patent number: 7787172
    Abstract: The present invention provides a projection apparatus, that includes: a light source; a light source control unit for controlling the output of the light source; at least one spatial light modulator for modulating the illumination light from the light source by a plurality of pixel elements; and an optical system for projecting, onto a screen, the illumination light deflected by the spatial light modulator, wherein: the light source control unit performs a gamma (?) correction on input image data by a modulation control of the light source.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: August 31, 2010
    Assignees: Silicon Quest Kabushiki-Kaisha, Olympus Corporation
    Inventors: Akira Shirai, Hirokazu Nishino, Yoshiaki Horikawa, Fusao Ishii
  • Patent number: 7782524
    Abstract: The mirror device comprising a plurality of deflectable mirrors for reflecting light, wherein the mirror is controllable to deflect to a first direction during an incident period with the light incident to the deflectable mirror and at an end of the incident period the mirror is controllable to deflect to a second direction opposite to the first direction during a non-incidence period in which the light is not incident to the present mirror.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: August 24, 2010
    Assignees: Silicon Quest Kabushiki-Kaisha, Olympus Corporation
    Inventors: Akira Shirai, Yoshihiro Maeda, Hirokazu Nishino, Fusao Ishii
  • Patent number: 7782523
    Abstract: An image display system includes an array of movable micromirrors each controlled by a mirror control system to oscillate between a fully ON and fully OFF positions. The mirror control system further includes at least electrode for applying voltages thereon according to an analog scale for controlling each of the micromirrors to oscillate substantially around a central angle of oscillation varying between the fully-On and fully-OFF angular positions, according to an analog angular scale corresponding to the analog scale of the voltage applied to the electrode(s). The brightness of a reflection from each of these micromirrors are therefore controllable according to an analog scale to generate a corresponding grayscale substantially according to an analog scale.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: August 24, 2010
    Inventor: Fusao Ishii
  • Patent number: 7781826
    Abstract: A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: August 24, 2010
    Assignee: Alpha & Omega Semiconductor, Ltd.
    Inventors: Shekar Mallikararjunaswamy, Madhur Bobde
  • Patent number: 7765679
    Abstract: A mass flow sensor is manufactured by a process of carrying out a micro-machining process on an N or lightly doped P-type silicon substrate with orientation <100>. This mass flow sensor comprises a central thin-film heater and a pair of thin-film heat sensing elements, and a thermally isolated membrane for supporting the heater and the sensors out of contact with the substrate base. The mass flow sensor is arranged for integration on a same silicon substrate to form a one-dimensional or two-dimensional array in order to expand the dynamic measurement range. For each sensor, the thermally isolated membrane is formed by a process that includes a step of first depositing dielectric thin-film layers over the substrate and then performing a backside etching process on a bulk silicon with TMAH or KOH or carrying out a dry plasma etch until the bottom dielectric thin-film layer is exposed.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: August 3, 2010
    Assignee: Siargo, Inc.
    Inventors: Yahong Yao, Chih-Chang Chen, Gafeng Wang, Liji Huang
  • Patent number: 7764105
    Abstract: This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: July 27, 2010
    Assignee: Alpha & Omega Semiconductor, Ltd
    Inventors: Anup Bhalla, Sik K. Lui