Abstract: A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a step of applying an source mask for implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes wherein the isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between the doped regions of different conductivity types.

Abstract: A micromirror device includes an elastic hinge for supporting a mirror on a substrate, and an address electrode for deflecting the mirror. The device further includes a protective layer and an oriented monolayer laid to cover a stopper also functioning as an address electrode provided below the mirror and between the mirror and the substrate.

Abstract: This invention provides a display control system that includes: a) a micromirror array comprising a plurality of mirrors; b) a first control function for controlling the mirrors in a first state; c) a second control function for controlling the mirrors in a second state; d) and a switchover controller for switching from the first state to second state, or from the second state to first state, wherein the switchover controller switches the state of at least two mirrors simultaneously at a same predetermined point within a frame period.

Abstract: The present invention provides a mirror device, comprising: a substrate; a mirror disposed approximately in parallel to the substrate above the substrate; and a hinge supported on and extended approximately perpendicularly from the substrate for supporting the mirror, wherein the hinge is connected to the mirror with a first edge part of the hinge buried in the mirror.

Abstract: The present invention provides a spatial light modulator, comprising: a plurality of mirror elements; a plurality of address electrodes for controlling the movement of each of the mirror elements; and first and second control circuits for generating a voltage in the address electrode, wherein the second control circuit applies a voltage to the address electrode when the mirror element is in a moving state.

Abstract: The present invention provides a display apparatus, comprising: a light source; at least one spatial light modulator for modulating a luminous flux emitted from the light source; and controller for processing video image information, which is input, and controlling the light source and the spatial light modulator, wherein the controller controls the light source and the spatial light modulator so as to perform pulse emission of the light source during a period shorter than a period in which the spatial light modulator is controlled under a modulation state and also controls the light source so as to modulate the pulse emission during a period shorter than a period in which the spatial light modulator is controlled under a modulation state.

Abstract: This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by manufacturing a MOSFET with a higher gate work function by implementing a P-doped gate in an N-MOSFET device. The P-type gate increases the threshold voltage and shifts the C-Vds characteristics. The reduced Cgd thus achieves the purpose of suppressing the shoot through and resolve the difficulties discussed above. Unlike the conventional techniques, the reduction of the capacitance Cgd is achieved without requiring complicated fabrication processes and control of the recess electrode.

Abstract: A trenched semiconductor power device that includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. Each of the body regions extended between two adjacent trenched gates further having a gap exposing a top surface above an epitaxial layer above said semiconductor substrate. The trenched semiconductor power device further includes a Schottky junction barrier layer covering the top surface above the epitaxial layer between the trenched gate thus forming embedded Schottky diodes between adjacent trenched gates.

Abstract: A transient voltage suppressing (TVS) circuit with uni-directional blocking and symmetric bi-directional blocking capabilities integrated with an electromagnetic interference (EMI) filter supported on a semiconductor substrate of a first conductivity type. The TVS circuit integrated with the EMI filter further includes a ground terminal disposed on the surface for the symmetric bi-directional blocking structure and at the bottom of the semiconductor substrate for the uni-directional blocking structure and an input and an output terminal disposed on a top surface with at least a Zener diode and a plurality of capacitors disposed in the semiconductor substrate to couple the ground terminal to the input and output terminals with a direct capacitive coupling without an intermediate floating body region.

Abstract: A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.

Abstract: This invention discloses a method to form a bottom-source lateral diffusion MOS (BS-LDMOS) device with a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The method includes a step of applying a sinker-channel mask for carrying out a deep sinker multiple energy implant to form a combined sinker-channel region in lower portion of an epitaxial layer to function as a buried source-body contact extending to and contacting a bottom of the substrate functioning as a bottom source electrode.

Abstract: A method for aligning a micro-mirror device die having a plurality of micro-mirror devices formed on a semiconductor substrate and fixing the micro-mirror device die on the semiconductor substrate can be provided. The method comprises a first alignment step of aligning a first guide portion of the micro-mirror device die and a second guide portion of the package substrate and a fixing step of fixing the micro-mirror device die on the package substrate in a position aligned by the first alignment step using the first and second guide portions.

Abstract: The present invention provides a spatial light modulator, comprising: a plurality of row lines each connected to a plurality of memory circuits; and a plurality of word lines and a plurality of plate lines connected to the memory circuits for selecting and controlling sets of the memory circuits connected to the selected row lines at pre-designated times for each of the row lines.

Abstract: One embodiment of the present invention uses plasma-driven gas flow to cool down electronic devices. The cooling device may comprise micro heat sink fins assembly, micro plasma actuators assembly, and magnetic circuit assembly. The plasma actuator assembly comprises electrodes and dielectric pieces. Voltages are applied to electrodes to drive the plasma gas flow. A magnetic circuit assembly may be used to provide the magnetic field to couple with plasma actuators to induce the plasma gas flow to cool down the heat sink fins and heat source.

Abstract: This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

Abstract: A micromirror device comprises a plurality of mirrors arranged on a substrate, an elastic hinge for supporting each mirror to be deflectable in a plurality of directions, an address electrode composed of first and second regions that are arranged across the deflection axis of each mirror, and a driving circuit for controlling the mirror to deflect in the directions of the first and the second regions.

Abstract: A method is disclosed in this invention for calibrating an offset Voffset and sensitivity Vsensitivity for an accelerometer implemented in a level gauge having a known value of an offset angle ?? and a known value of a relative angle between top-and-bottom surface ?s. The method includes a step of placing the level gauge implemented with the accelerometer on a table-top surface having a tilt angle ?1 and measuring a tilt angle ?F from the level gauge and an output voltage VF from the accelerometer, then rotating the level gauge 180 degrees on the table-top surface along a perpendicular axis relative to the table top surface and measuring a tilt angle ?B from the level gauge and measuring an output voltage VB from the accelerometer.

Abstract: A mirror device comprises: a plurality of electrodes disposed on a substrate; a hinge connected to at least one of the electrodes; a mirror connected to the hinge and corresponding to at least one of the electrodes, wherein a barrier layer is comprised between the hinge and mirror, and/or between the hinge and electrode. Also noted is a mirror device production method for producing such-configured mirror device. Further noted is a projection apparatus comprising such-configured mirror device.

Abstract: An electronic package for containing at least a top packaging module vertically stacked on a bottom packaging module. Each of the packaging modules includes a semiconductor chip packaged and connected by via connectors and connectors disposed on a laminated board fabricated with a standard printed-circuit board process wherein the top and bottom packaging module further configured as a surface mountable modules for conveniently stacking and mounting to prearranged electrical contacts without using a leadframe. At least one of the top and bottom packaging modules is a multi-chip module (MCM) containing at least two semiconductor chips. At least one of the top and bottom packaging modules includes a ball grid array (BGA) for surface mounting onto the prearranged electrical contacts. At least one of the top and bottom packaging modules includes a plurality of solder bumps on one of the semiconductor chips for surface mounting onto the prearranged electrical contacts.

Abstract: A novel integration scheme for forming power MOSFET, particularly forming salicides for both gate and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicides.