Abstract: A surface mountable device having a circuit device and a base section. The circuit device includes top and bottom layers having a top contact and a bottom contact, respectively. The base section includes a substrate having a top base surface and a bottom base surface. The top base surface includes a top electrode bonded to the bottom contact, and the bottom base surface includes first and second bottom electrodes that are electrically isolated from one another. The top electrode is connected to the first bottom electrode, and the second bottom electrode is connected to the top contact by a vertical conductor. An insulating layer is bonded to a surface of the circuit device and covers a portion of a vertical surface of the bottom layer. The vertical conductor includes a layer of metal bonded to the insulating layer.

Abstract: An image sensor and a method for using the same are disclosed. The image sensor includes an array of pixel sensors, a signal digitizing circuit, and a digitizing controller. The array of pixel sensors includes a plurality of pixel sensors. Each pixel sensor includes a photodetector, a charge conversion circuit, and a gate transistor. The charge conversion circuit generates a voltage signal that is related to a charge on the photodiode, and the gate transistor couples the voltage signal to a bit line in response to a first signal. The signal digitizing circuit converts the voltage signal to a plurality of output digital values. Each output digital value has a different level of digitization noise. One of the output digital values is selected for output in response to an output selection signal that is generated by the digitizing controller.

Abstract: An image sensor and method for using the image sensor to capture an image are disclosed. The image sensor includes an imaging array, a first block amplifier and a controller. A first plurality of pixels in the imaging array includes pixels having a photodiode connected to a first node by a gate transistor, a reset transistor connected between the first node and a reset node, a pixel amplifier having an input connected to the first node and an output, and an output gate for connecting the pixel amplifier output to an output bus. The sensor has a monitoring mode and an image capture mode. In the monitoring mode the reset node is connected to the first block amplifier whose output is monitored and used to trigger the image capture mode when the output exceeds a predetermined threshold.

Abstract: A device having a carrier, a light-emitting structure, and first and second electrodes is disclosed. The light-emitting structure includes an active layer sandwiched between a p-type GaN layer and an n-type GaN layer, the active layer emitting light of a predetermined wavelength in the active layer when electrons and holes from the n-type GaN layer and the p-type GaN layer, respectively, combine therein. The first and second electrodes are bonded to the surfaces of the p-type and n-type GaN layers that are not adjacent to the active layer. The n-type GaN layer has a thickness less than 1.25 ?m. The carrier is bonded to the light emitting structure during the thinning of the n-type GaN layer. The thinned light-emitting structure can be transferred to a second carrier to provide a device that is analogous to conventional LEDs having contacts on the top surface of the LED.

Abstract: A basic building block for wafer scale stacked integrated circuits is disclosed. The building block includes an integrated circuit device having an integrated circuit substrate having a circuit layer sandwiched between a buffer layer and a dielectric layer. The dielectric layer has a top side and a bottom side, the bottom side being in contact with the circuit layer. The top surface of the dielectric layer includes a plurality of pads. Each pad extends above the top surface by a predetermined distance. The pads have dimensions that reduce irregularities in the top surface of the pads. In addition, the pads are arranged in a manner to promote planarization of the surface of the wafer via CMP.

Abstract: A light source and method for fabricating the same are disclosed. The light source includes a substrate and a light emitting structure. The substrate has a first surface and a second surface, the second surface including a curved, convex surface with respect to the first surface of the substrate. The light emitting structure includes a first layer of a material of a first conductivity type overlying the first surface, an active layer overlying the first layer, the active layer generating light when holes and electrons recombine therein, and a second layer includes a material of a second conductivity type overlying the active layer and a second surface opposite to the first surface. A mirror layer overlies the light emitting structure.

Abstract: A light-emitting device and the method for making the same are disclosed. The device includes a substrate, a light-emitting structure and a light scattering layer. The light-emitting structure includes an active layer sandwiched between a p-type GaN layer and an n-type GaN layer, the active layer emitting light of a predetermined wavelength when electrons and holes from the n-type GaN layer and the p-type GaN layer, respectively, combine therein. The light scattering layer includes a GaN crystalline layer characterized by an N-face surface. The N-face surface includes features that scatter light of the predetermined wavelength. The light-emitting structure is between the N-face surface and the substrate.

Abstract: A diagnostic test interface circuit and method for using the same are disclosed. The circuit isolates communication links at a junction box having one pin for each of the communication links. The circuit includes a bus, a plurality of switches, and a plurality of connection leads. The switches each have a first terminal connected to the bus. Each connection lead includes a first end having a connector that connects to one of the pins and a second end that connects to a corresponding one of the switches such that the switch connects the connection lead to the bus when the switch is closed. The circuit can be used to diagnose a fault in a vehicle having a plurality of modules that communicate over a star-configured network.

Abstract: An image sensor having a two-dimensional array of CMOS pixel sensors, a row decoder and a column decoder is disclosed. The two-dimensional array of CMOS pixel sensors is organized as a plurality of rows and columns that are addressed with the aid of row and column decoders. At least one of the column decoder or the row decoder is located between two of the rows or two of the columns, respectively. X-rays are converted to light that is detected by the image sensor by a layer of scintillation material that overlies the two-dimensional array. The internally located decoder or decoders facilitate sensors in which the two-dimensional array includes a rectangular array having a chamfered corner such that rows or columns that extend into the chamfered corner have lengths that are less than rows or columns, respectively, that do not extend into the corners.

Abstract: A light sensor having a light conversion element between first and second electrodes is disclosed. The light conversion element includes a body of semiconductor material having first and second surfaces. The body of semiconductor material is of a first conductivity type and has doping elements in a concentration gradient that creates a first electrostatic field having a magnitude that varies monotonically from the first surface to the second surface. A bias circuit applies a variable potential between the first and second electrodes to create a second electrostatic field having a direction opposite to that of the first electrostatic field and a magnitude determined by the potential. One of the electrodes is transparent to light in a predetermined band of wavelengths. The body of semiconductor material can include an epitaxial body having a monotonically increasing concentration of a doping element as a function of the distance from one the surfaces.

Abstract: An image sensor having a first substrate on which a CCD array is fabricated in a first fabrication system is disclosed. The CCD array includes a node through which charge from the pixels passes during a readout operation. The first substrate also includes a first FET fabricated on the first substrate in the first fabrication system, the first FET having a gate connected to the node and a source or drain connected to a first conducting pad on the first substrate. A capacitor connects the node to a second conducting pad on the first substrate. A switch is connected across the first capacitor such that the first capacitor is shorted when the first switch is closed. The first switch is controlled by a reset signal on a third conducting pad on the first substrate. The first substrate can be connected to a second substrate having amplification and control circuitry.

Abstract: A surface mountable device having a circuit device and a base section. The circuit device includes top and bottom layers having a top contact and a bottom contact, respectively. The base section includes a substrate having a top base surface and a bottom base surface. The top base surface includes a top electrode bonded to the bottom contact, and the bottom base surface includes first and second bottom electrodes that are electrically isolated from one another. The top electrode is connected to the first bottom electrode, and the second bottom electrode is connected to the top contact by a vertical conductor. An insulating layer is bonded to a surface of the circuit device and covers a portion of a vertical surface of the bottom layer. The vertical conductor includes a layer of metal bonded to the insulating layer.

Abstract: An image sensor having a two-dimensional array of pixel sensors, a layer of scintillation material, and a controller is disclosed. The layer of scintillation material is adjacent to the two-dimensional array, the scintillation material emits light in response to x-rays impinging thereon. The pixel sensors detect this light. The controller reads out data stored in the two-dimensional array of pixel sensors and forms an image therefrom. The controller corrects the data for errors resulting from x-rays that generate electrons that are stored in the pixel sensors in the process of forming the image. In one aspect of the invention, the controller forms the image by causing the two-dimensional array to form a plurality of frames, each frame includes a measurement of a charge stored on each photodiode during a preceding time period. The controller selectively combines data from the frames to form the image.

Abstract: An image sensor and a method for using the same to capture an x-ray image are disclosed. The image sensor includes an output bus, a two dimensional array of pixel sensors that receives light from a layer of scintillation material and a controller. Each pixel sensor includes a capacitor, a plurality of light sensors, a charge converter and a transfer gate. Each of the light sensors includes a photodiode and a photodiode transfer gate that connects the photodiode to the capacitor. During readout, the charge on selected ones of the photodiodes is transferred to the capacitor. The charge on the capacitor is converted to a signal that is coupled to the output bus through the transfer gate by the controller. The number of photodiodes that are connected to the capacitor during the readout can be controlled to assure that the charge converter does not saturate.

Abstract: A camera having an exposure detector is disclosed. The camera includes an array of pixel sensors, CMOS circuitry that is separate from the array of pixel sensors, a guard region, and a current detector. The guard region separates the CMOS circuitry from the array of pixel sensors. The guard region is positioned such that the guard region is exposed to light when the array of pixel sensors is exposed to light. The current detector measures the current flowing from the guard region to a power rail when the guard region is biased to a predetermined potential and generates a start trigger signal when the current exceeds a threshold value. A controller resets the pixel sensors in response to the start trigger signal.

Abstract: A surface mountable device having a circuit device and a base section. The circuit device includes top and bottom layers having a top contact and a bottom contact, respectively. The base section includes a substrate having a top base surface and a bottom base surface. The top base surface includes a top electrode bonded to the bottom contact, and the bottom base surface includes first and second bottom electrodes that are electrically isolated from one another. The top electrode is connected to the first bottom electrode, and the second bottom electrode is connected to the top contact by a vertical conductor. An insulating layer is bonded to a surface of the circuit device and covers a portion of a vertical surface of the bottom layer. The vertical conductor includes a layer of metal bonded to the insulating layer.

Abstract: A CCD imaging array and a charge measurement amplifier for use in such imaging arrays is disclosed. The array includes a plurality of pixels that accumulate charge when exposed to light, a readout amplifier having input and output ports. The readout amplifier has a variable gain that is set by a gain control signal. The readout amplifier also includes a reset path between the input and output ports, the path having an impedance controlled by a reset signal. A controller generates the gain control signal and the reset signal during a charge measurement cycle. Initially the gain is set to a first value after generating the reset signal. The gain is changed to a second value during the charge measurement cycle if the output signal exceeds a first threshold value. The readout amplifier can be constructed from an operational amplifier having a capacitive feedback loop.

Abstract: A circuit having an interconnect network and plurality of processing blocks is disclosed. The interconnect network has a plurality of network nodes arranged in a two-dimensional array on a first substrate. Each network node has a plurality of communication ports and is connected to each adjacent network node by a communication bus that connects only those two network nodes and processing blocks adjacent to that communication bus. A programmable switch within each node connects one of the input ports to one of the output ports in response to connection information stored in a memory in that node. Three-dimensional embodiments can be constructed by including a second substrate that overlies the first substrate and includes a second such interconnect network that is connected vertically through one or more nodes. The circuit easily accommodates spare processing blocks that can be substituted for defective blocks by altering the connection information.

Abstract: An imaging array having a CCD imaging array that includes a plurality of pixels that accumulate charge when exposed to light and a readout amplifier is disclosed. The readout amplifier includes an operational amplifier having an input and an output port and a feedback capacitor connecting the input and output ports and a variable impedance path between the input and output ports, the path having an impedance controlled by a reset signal. A reset signal generator generates the reset signal in three sequential phases in which the path between the input and output ports has three impedance values to provide a starting voltage at the amplifier input prior to the measurement of charge from each pixel that has reduced noise.

Abstract: A circuit element that includes a ferroelectric device connected to a substrate device. The circuit element is constructed by fabricating the substrate device in a semiconductor substrate and depositing a dielectric layer over the semiconductor substrate. A via is then etched in the dielectric layer to provide access to the substrate device and filled with copper or tungsten. A layer of a conducting metallic oxide is then deposited on the conducting plug, and a layer of ferroelectric material is deposited on the layer of conducting metal oxide. The layer of conducting metallic oxide is deposited at a temperature below 450° C., preferably at room temperature.