Abstract: A draw bar clamping locking mechanism for locking and unlocking rapidly a draw bar mounted on the front end of a trolley to the rear end of an automatic guided vehicle. The locking bar mechanism includes a locking bar which is moveable rotatably between a locked position where the draw bar is received in a U-shaped slot and an unlocked position where the draw bar is disengaged from the U-shaped slot. A release paddle is provided for unlocking and releasing rapidly the draw bar from the U-shaped slot when depressed downwardly.

Abstract: A fixture assembly of a unique construction is provided for use with a decapsulating machine so as to prevent damage to a FBGA package during decapsulation. The fixture assembly includes a retaining gasket for holding and aligning the FBGA package in the decapsulating machine, a spacer element for protecting the solder balls of the FBGA package, and a cover for receiving the pressure from a spring-loaded arm of the decapsulating machine. As a result, the FBGA package is prevented from being over etched by the sulfuric acid during decapsulation. In addition, damage to the solder balls are prevented due to excess pressure from the spring-loaded arm.

Abstract: An apparatus and method for attenuating high frequency transients on AC power lines from damaging sensitive electrical and electronic circuits in an electrical load coupled to the AC power lines is provided. The AC power line has an earth ground and the electrical load has an electrical load ground. A continuous attenuator circuit is used for attenuating high frequency transients electrically coupled between the earth ground and the electrical load ground. The continuous attenuator circuit includes a plurality of toroid cores and a single continuous strand of wire being wound individually and sequentially a number of turns around each of the plurality of toroid cores.

Abstract: An improved level shifter circuit is provided which is designed for use with an extremely low power supply voltage. The level shifter circuit includes a fourth NMOS transistor, a third PMOS transistor, and a fifth NMOS transistor connected in series and interconnected between the high voltage and the output terminal. As a result, the high voltage will still be passed to the output terminal when the high voltage is lowered to be equal to the low power supply voltage.

Abstract: There is provided a method for applying a lower viscosity coating liquid onto a semiconductor wafer substrate so as to prevent adhesion loss and to maintain low defect level characteristics. This is achieved by priming the substrate with a bonding agent at a temperature in the range of 18° C. to 50° C. for a short amount of time. This is performed prior to the application of a liquid solvent. As a result, there is overcome the problems of poor adhesion to the substrates and high defect levels in the coated UTR films.

Abstract: An interconnection test structure for evaluating more accurately and reliably electromigration characteristics is provided. The test structure includes an elongated metal test conductor having a first end and a second end, small extension metal conductors connected to the first end and the second end of the test conductor, and a plurality of vias disposed in the small extension metal conductors adjacent the first end and the second end of the test conductor. As a result, the current density of the plurality of vias is made to be less than the current density of the test conductor.

Abstract: There is provided a method for enhancing the contrast between oxide film and ultra-thin resists in deep-ultraviolet lithography for use with a wafer defect inspection system in order to maximize defect inspection sensitivity. This is achieved by varying the thickness of the oxide film for a given ultra-thin resist thickness so as to produce a high contrast. As a result, defect inspection of the ultra-thin resist pattern is easily obtained. In a second embodiment, the ultra-thin resist thickness is varied for a given oxide film thickness. In a third embodiment, both the oxide film and the ultra-thin resist thicknesses are varied simultaneously so as to obtain an optimum contrast.

Abstract: A MOS transistor and a method of fabricating the same for Ultra Large Scale Integration applications includes a composite gate structure. The composite gate structure is comprised of a main gate electrode and two assisted-gate electrodes disposed adjacent to and on opposite sides of the main gate electrode via an oxide layer. Areas underneath the two assisted-gate electrodes form ultra-shallow “pseudo” source/drain extensions. As a result, these extensions have a more shallow depth so as to enhance immunity to short channel effects.

Abstract: A tracking circuit is provided for performing an erase verify/erase operation so as to prevent over-erasure in an array of EEPROM memory cells. A binary counter is used to count the number of erase pulses during a normal erase verify/erase operation. Counter registers are used to store 50%, 25%, and 12.5% of a diagonal erase pulse count obtained from the binary counter during a diagonal erase verify operation. A multiplexer selectively pre-loads a target count prior to the normal erase verify/erase operation. A comparator circuit compares a pulse count during the normal erase verify/erase operation with the 50% of the diagonal erase pulse count and generates a high logic signal when the pulse count equals the 50% diagonal erase pulse count to indicate that the target has been reached. The target count may be varied by the multiplexer to be 25%, 37.5%, 50%, 62.5%, or 75% of the diagonal erase pulse count.

Abstract: A method for eliminating source/drain shorting generated during the highly-doped source/drain implant steps in a standard STI process is provided. This is achieved by reducing the RTA temperature to be less than 1000° C. so as to minimize enhanced doping diffusion. Further, the energy level for the highly-doped source/drain implant steps is increased so to compensate for poly depletion in the gate electrodes.

Abstract: Control circuitry and a method for generating an accurate drain voltage for selected memory core cells in a semiconductor memory device during a Read mode of operation is provided. Select gate transistors are provided which have their conduction path being coupled between a power supply voltage and a drain of one of the selected memory core cells. A differential amplifier circuit is responsive to a bitline voltage corresponding to a drain voltage of the selected memory core cells and a reference voltage for generating a select gate voltage. The select gate voltage is decreased when the bitline voltage is higher than a target voltage and is increased when the bitline voltage is lower than the target voltage. A source follower circuit is responsive to the select gate voltage for generating the bitline voltage which is maintained at the target voltage.

Abstract: Control circuitry and a method for generating an accurate boosted wordline voltage for selected memory core cells in a semiconductor memory device during a Read mode of operation is provided. Memory core transistors are provided which have their conduction path being coupled between a power supply voltage and a ground potential. Differential amplifier circuitry is responsive to a boost signal and a reference voltage for generating a select wordline voltage. The select wordline voltage is decreased when the wordline voltage is higher than a desired voltage and is increased when the wordline voltage is lower than the desired voltage. The control gates of the memory core transistors are responsive to the select wordline voltage.

Abstract: An improved method of fabricating a non-volatile semiconductor device having a PECVD nitride cap layer formed under a BPTEOS oxide film is provided. The present method utilizes the step of forming a LPCVD nitride film under the PECVD nitride cap layer and over the floating gate so as to protect the floating gate from charge loss.

Abstract: There is provided a method of applying a developing liquid onto a semiconductor wafer substrate having a UTR film thereon so as to minimize unexposed film thickness loss during development. This is achieved by applying the developing liquid from a developer nozzle which is off-set from the central position of the wafer substrate. The developing liquid is allowed to contact the wafer substrate for less than 10 seconds. As a result, there is overcome the problems of unexposed film thickness loss and critical dimension variations due to the developer nozzle effects.

Abstract: A method of erasing a flash electrically-erasable programmable read-only memory (EEPROM) device is provided which includes a plurality of memory cells. An erase pulse is applied to the plurality of memory cells. The plurality of memory cells is overerase verified and an overerase correction pulse is applied to the bitline to which the overerased memory cell is attached. This cycle is repeated until all cells verify as not being overerased. The plurality of memory cells is erase verified and another erase pulse is applied to the memory cells if there are undererased memory cells and the memory cells are again erase verified. This cycle is repeated until all cells verify as not being undererased. After erase verify is completed, the plurality of memory cells is soft program verified and a soft programming pulse is applied to the those memory cells in the plurality of memory cells which have a threshold voltage below a pre-defined minimum value.

Abstract: There is provided a new polysilicon fuse structure for implementation within integrated circuit devices so as to permit programming of the same. The polysilicon fuse structure includes a first electrical contact region, a second electrical contact region, and multiple fuse regions interconnected between the first electrical contact region and the second electrical contact region. The multiple fuse regions are formed of a plurality of strips, each being of a different width and/or length, which are disposed in a spaced-apart relationship so as to form a small opening between adjacent strips. A number of the plurality of strips is selectively blown when a predetermined amount of current is passed from one of the first and second electrical contact regions through the plurality of strips to the other one of the first and second electrical contact regions so to limit the current passing to an integrated circuit device connected thereto during normal operating conditions.

Abstract: There is provided an improved resist coating/developing processing method and apparatus for a wafer track system so as to increase its throughput. In a preferred embodiment, this is achieved by integrating a wafer edge exposure unit with a temperature control plate unit into a single integrated processing unit having the functionality of the two separate processing units.

Abstract: A deep submicron MOS device having a self-aligned silicide gate structure and a method for forming the same is provided so as to overcome the problems of poly-Si depletion and boron penetration. A first Nickel silicide layer is formed between a gate oxide and a polycrystalline silicon gate electrode. Further, second Nickel silicide layers are formed over highly-doped source/drain regions. In this fashion, the reliability of the MOS device will be enhanced.

Abstract: In a preferred embodiment, there is disclosed a method of forming a tungsten plug at the via level. A metal line is formed in a top portion of a first insulating layer. A second insulating layer is formed on the first insulating layer and over an exposed surface of the metal line. An etching process is applied to a region of the second insulating layer formed over the exposed surface of the metal line to create a contact hole within the region. The metal line is exposed at the region. A tungsten nitride thin film is deposited over the second insulating layer and the exposed metal line. A blanket tungsten thin film is deposited to fill the contact hole and to form a planar layer successively to the depositing of the tungsten nitride thin film. The tungsten nitride thin film and the blanket tungsten thin film are chemically mechanically polished until the upper surface of the second insulating layer is exposed.