Abstract: A boost level clamping circuit and a method for clamping a boosted wordline voltage from a booster circuit used in a semiconductor memory device is provided which is power supply and process corner independent. The clamping circuit is formed of a plurality of parallel-connected clamp stages connected to the boosted wordline voltage from the booster circuit. Each of the plurality of clamp stages serves to clamp the boosted wordline voltage at different predetermined levels. Each of the clamp stages is formed of a sampling circuit, a comparator circuit, a pulse generator circuit, and a pull-down circuit.

Abstract: A method of minimizing mechanical stress generated during the trench-forming/trench-filling process steps in a standard shallow trench isolation (STI) process is provided. This is achieved by forming trenches with a more sloped and smoother profile, and/or limiting the trench depth to be less than 0.4 &mgr;m, and/or reducing or increasing the trench densification temperature, and/or performing the densification step after the chemical-mechanical polishing step. In addition, a furnace TEOS oxide film is used as the trench-filling material.

Abstract: A unified program method and circuitry for performing concurrently a programming and verifying operation in an array of Flash EEPROM memory cells is provided. Each of the memory cells includes a floating gate array core transistor. A single bandgap voltage is provided which corresponds to a predetermined amount of drain current at which programming is to be terminated. A program voltage is selectively connected to at least one of the columns of array bit lines containing the array core transistor which is to be programmed. A control gate bias voltage corresponding to a programmable memory state is selectively connected to the gate of the array core transistor. A core cell current flowing through the array core transistor and the predetermined amount of drain current is compared. The program voltage is disconnected so as to terminate automatically programming of the array core transistor when the core cell current falls below the predetermined amount of drain current.

Abstract: A tube holder assembly is provided for use with an output track assembly of an IC test handler so as to eliminate the need of transferring tested SOIC packages loaded in plastic tubes to metal tubes for a “burn-in” process. The tube holder assembly is comprised of an output tube guide member, a tube holder member, a tube holder guide member, and a holder screw. The tube holder member is vertically slidable relative to the tube holder guide member between a lower position and an upper position. The tube holder member is pushed downwardly into the lower position so as to load directly SOIC packages into plastic tubes and is raised to the upper position so as to load directly the SOIC packages into metal tubes.

Abstract: An impedance blocking filter circuit is provided for use in telecommunication systems for interconnecting between incoming telephone lines and customer's terminal equipment so as to unconditionally block impedances above 20 KHz due to the customer's terminal equipment from an ADSL network unit and/or home networking interface unit. The filter circuit includes first, second, and third inductors connected in series between a first input terminal and a first common point. A first resistor has its one end connected also to the first common point and its other end connected to a first output terminal. Fourth, fifth and sixth inductors are connected in series between a second input terminal and a second common point. A second resistor has its one end also connected to the second common point and its other end connected to a second output terminal. A capacitor has its ends connected across the first and second common points.

Abstract: An apparatus and a method for reducing capacitive loading in a Flash memory X-decoder so as to accurately control the voltages as selected wordlines and block select lines are provided. A decoding structure separately applies a first boosted voltage to the wordline N-well region and a second boosted voltage to the selected wordline so as to reduce capacitive loading on the selected wordline due to heavy capacitive loading associated with the wordline N-well region. The decoding structure further applies a third boosted voltage to the select gate N-well region and a fourth boosted voltage to the block select line so as to reduce capacitive loading on the block select line due to heavy capacitive loading associated with the select gate N-well region. As a consequence, an accurate voltage can be created quickly at the selected wordline since its capacitive loading path is very small.

Abstract: An improved silicon nitride etch bath system is provided. The improved etch bath system includes a silicon dioxide condensing system formed of a heat exchanger and a secondary filter. The heat exchanger is provided for removing a small portion of phosphoric acid from an etching bath and for cooling of the same. The secondary filter is used for extracting silicon dioxide particles in the small portion of the phosphoric acid and is operatively connected to the heat exchanger before returning the same to the etching bath. In this manner, the concentration of silicon dioxide in the etching bath will be prevented from being saturated.

Abstract: A reference trimming verify circuit and method is provided for performing a program verify operation on a reference cell transistor in an array of Flash EEPROM memory cells. A reference current branch is used to generate a reference current corresponding to a predetermined overdrive voltage of the reference cell to be programmed. A drain current branch is coupled to the reference cell transistor to be programmed and generates a drain current at a fixed gate voltage applied to its control gate and at a predetermined drain voltage applied to its drain when the drain current is at the desired level. A comparator is used to compare a sensed voltage corresponding to the drain current and a reference voltage corresponding to the reference current. The comparator generates an output signal which is at a low logic level when the sensed voltage is less than the reference voltage and which is at a high logic level when the sensed voltage is greater than the reference voltage.

Abstract: An impedance blocking filter circuit is provided for use in telecommunication systems for interconnecting between incoming telephone lines and customer's terminal equipment so as to unconditionally block impedances above 20 KHz due to the customer's terminal equipment from an ADSL network unit and/or home networking interface unit. The filter circuit includes first, second, and third inductors connected in series between a first input terminal and a first common point. A first resistor has its one end connected also to the first common point and its other end connected to a first output terminal. Fourth, fifth and sixth inductors are connected in series between a second input terminal and a second common point. A second resistor has its one end also connected to the second common point and its other end connected to a second output terminal. A capacitor has its ends connected across the first and second common points.

Abstract: An impedance blocking filter circuit is provided for use in telecommunication systems for interconnecting between incoming telephone lines and customer's terminal equipment so as to unconditionally block impedances above 20 KHz due to the customer's terminal equipment from an ADSL network unit and/or home networking interface unit. The filter circuit includes first, second, and third inductors connected in series between a first input terminal and a first common point. A first resistor has its one end connected also to the first common point and its other end connected to a first output terminal. Fourth, fifth and sixth inductors are connected in series between a second input terminal and a second common point. A second resistor has its one end also connected to the second common point and its other end connected to a second output terminal. A capacitor has its ends connected across the first and second common points.

Abstract: An output noise control circuit with significantly reduced power/ground bounce characteristics when multiple outputs thereof are being simultaneously switched is provided. The output noise control circuit includes a plurality of output buffers each being formed of an output driver stage, a first pre-driver stage, and a second pre-driver stage. Each of the output driver stages includes a pull-up drive transistor and a pull-down drive transistor. Each of the first pre-driver stages includes a first inverter, and each of said second pre-driver stages includes a second inverter. A shared pull-up resistor has its one end coupled to each of the first pre-driver stage inverters and its other end connected to a ground potential node. A shared pull-down resistor has its one end coupled to each of the second pre-driver stage inverters and its other end connected to a power supply potential node.

Abstract: A unified erase method used in an array of flash EEPROM memory cells arranged in a plurality of sectors for performing either a single-sector, multiple-sector, or all-sector erasing operation with a reduced amount of total erase time and a uniform VT distribution as good as that of a single-sector erase operation is provided. An erase-verify operation is performed sequentially on the plurality of sectors from a first sector to a last sector beginning with a first address of each sector if its corresponding erase-on signal is not turned OFF. The current address of each sector is stored at a point where the erase-verify operation failed. An erase pulse is applied only to all sectors simultaneously that have not passed the erase-verify operation. The erase-verify operation is then repeated beginning at the current address stored. The erasing operation is terminated when the erase-on signal has been turned OFF in all sectors in the plurality of sectors.

Abstract: A wordline tracking structure for use in an array of Flash EEPROM memory cells is provided. The tracking structure serves to match reference and sector core wordline voltages across the entire chip regardless of sector location. The tracking structure includes a second VPXG conductor line operatively connected between sector wordlines of a "far" sector and a reference cell mini-array. The second VPXG conductor line has a substantially smaller time constant than in a first VPXG conductor line operatively connected between an output of a boosting circuit and the sector wordlines of the "far" sector. As a consequence, the reference wordline voltage associated with the reference cell mini-array will track closely the sector wordline voltage during the read operation regardless of the location of the selected sector.

Abstract: There is provided a hotplate offset ring of a unique construction for use in a heat treatment unit of wafer track system so as to achieve a more uniform heat transfer. In a preferred embodiment, this is achieved by a plurality of spacer tabs formed on the offset ring which prevent the possibility of non-uniformities in a gap formed between the wafer and the hotplate by eliminating any raised surfaces.

Abstract: A reference voltage generator circuit is provided for use with an extremely low power supply voltage. The reference voltage generator circuit produces a lower reference output voltage which is compensated for temperature variations and is independent of changes in the supply voltage. The reference output voltage relies upon the threshold voltage V.sub.T of a MOSFET transistor as a reference source.

Abstract: There is provided a MOS device with self-compensating threshold implant regions and a method of manufacturing the same which includes a semiconductor substrate, a partial first threshold implant forming a higher concentration layer, a gate oxide formed on the surface of the higher concentration layer, and a gate formed on a surface of the gate oxide. The MOS device further includes a second threshold implant for forming self-compensating implant regions in the substrate which is subsequently heated to define pockets. A third implant is performed to create lightly-doped source/drain regions. A sidewall spacer is formed on each side of the gate. A fourth implant is performed to create highly-doped source/drain regions between the lightly-doped source/drain regions and the pockets.

Abstract: An improved EEPROM cell having a field-edgeless tunnel window is provided which is fabricated by a STI process so as to produce reliable endurance and data retention. The EEPROM cell includes a floating gate, a programmable junction region, and a tunneling oxide layer separating the programmable junction region and the floating gate. The tunneling oxide layer defines a tunnel window which allows for programming and erasing of the floating gate by tunneling electrons therethrough. The programmable junction region has a width dimension and a length dimension so as to define a first area. The tunnel window has a width dimension and a length dimension so as to define a second area. The second area of the tunnel window is completely confined within the first area of the programmable junction region so as to form a field-edgeless tunnel window.

Abstract: An improved EEPROM cell structure and a method of fabricating the same is provided so as to improve data retention. The EEPROM cell includes a stacked dielectric structure consisting of a thin tunnel oxide layer and a high-k dielectric layer to function as the tunneling dielectric barrier so as to suppress leakage current.

Abstract: An improved chemical mechanical polishing apparatus for polishing a semiconductor wafer used in the fabrication of silicon-based semiconductor devices is provided so as to eliminate an air pocket bubble from being formed underneath a polishing pad without the need for cutting the same. This is achieved by a CMP platen plug which is disposed in a recess formed in a top cover plate member so as to completely fill the recess in order to displace the air pocket. The polishing pad is then secured over the platen plug and the top cover plate member. As a result, the useful life of the polishing pad has been prolonged.