Abstract: A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer is formed on a top surface of a semiconductor substrate. A barrier oxide layer is formed on a top surface of the epitaxial layer. A nitride layer is deposited on a top surface of the barrier oxide layer. Trenches are formed through the epitaxial layer and the barrier oxide layer to a depth greater than 4000 .ANG. below the surface of the epitaxial layer so as to create isolation regions in order to electrically isolate active regions in the epitaxial layer. A liner oxide is formed on sidewalls and bottom of the trenches to a thickness between 750 .ANG. to 1500 .ANG.. As a result, leakage current in the sidewalls are prevented due to less thinning of the liner oxide layer by subsequent fabrication process steps.

Abstract: A CMOS device and a method for forming the same is provided so as to overcome the problem of boron penetration through the thin gate oxide of P-channel devices. Silicon is implanted into the polysilicon gate electrode of the PMOS device functioning as a diffusion barrier for preventing boron penetration through the thin gate oxide and into the semiconductor substrate. As a result, the reliability of the CMOS device will be enhanced.

Abstract: An improved input tube unloader assembly is provided for use with an IC handler structure so as to eliminate damage to IC packages and/or jamming of tubes. The input tube unloader assembly is comprised of a frame member and a pair of opposed main side plate members being supported on opposite ends of the frame member. Each of the pair of opposed main side plate members includes an upright section, a pair of transverse bracket portions joined to opposed sides of the upright section, and a tube guide portion mounted on an interior surface of the upright section. The tube guide portion is formed of an inverted T-shaped configuration and includes a longer vertical leg and a shorter horizontal leg joined integrally to a lower end of the longer vertical leg in its middle area.

Abstract: There is provided a method of correcting overerased memory cells in a flash EEPROM memory cell after erase so as to produce a narrow threshold voltage distribution width. A ground potential is applied to all of the sources and substrates of the cells in the array of memory cells. First positive pulse voltages are simultaneously applied to each word line in a first timed sequence on a word line by word line basis. A second positive pulse voltage is simultaneously applied to each bit line in a second timed sequence in a bit line by bit line basis when the first positive pulse voltages are being applied to a first word line and is then repeated for each subsequent word line until a last word line is applied.

Abstract: There is provided an improved metallization stack structure so as to produce a higher electromigration resistance and yet maintain a relatively low resistivity. The metallization stack structure includes a pure copper layer sandwiched between a top thin doped copper layer and a bottom thin doped copper layer. The top and bottom thin doped copper layers produce a higher electromigration resistance. The pure copper layer produces a relatively low resistivity.

Abstract: A chip carrier tube for packing and shipping of Flash miniature cards in a side-by-side arrangement includes a tubular body member (24), a first end stop member (26a), and a second end stop member (26b). The tubular body member has a first end and a second end. The tubular body member has a bore of a rectangular cross-section extending therethrough between the first end and the second end. The tubular body member includes an upper wall section (34), a lower wall section (36), and a pair of opposed side walls (38,40) all integrally connected together. There are provided a stepped end portion (50) formed on the lower wall section for supporting only a small portion of the bottom surface adjacent to the side edge opposite to a plurality of terminal leads of the miniature cards and a rib member supporting the plurality of terminal leads so that top and bottom surfaces thereof are substantially suspended freely between raised mid-portions on the respective upper and lower wall sections of the tubular member.

Abstract: There is provided an improved NAND logic gate circuit for use in microprocessors and a method for fabricating the same so as to be capable of operating at higher speeds. The NAND logic gate circuit includes a parallel structure formed of a plurality of P-channel MOS together in parallel and a stacked structure formed of a plurality of N-channel MOS transistors all connected together in series. Each of the plurality of P-channel MOS transistors has a first sub-nominal channel length and reduced overlap capacitance. Each of the plurality of N-channel MOS transistors has a second sub-nominal channel length and reduced overlap capacitance.

Abstract: A CMOS device and a method for forming the same is provided so as to overcome the problem of boron penetration through the thin gate oxide of P-channel devices. Silicon is implanted into the polysilicon gate electrode of the PMOS device functioning as a diffusion barrier for preventing boron penetration through the thin gate oxide and into the semiconductor substrate. As a result, the reliability of the CMOS device will be enhanced.

Abstract: A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.

Abstract: There is provided a method of measuring the value of the threshold voltage of a memory core cell in an array of flash EEPROM memory core cells. The memory core cell includes an array core transistor having a corresponding array threshold voltage which is to be measured. There is provided a reference current level at a constant value which is generated by a reference cell transistor having a fixed bias condition and a fixed threshold voltage so that the relationship of the bias voltage applied to its gate and the fixed threshold voltage is linear. A control gate bias voltage applied to the gate of the array core transistor having the array threshold voltage which is to be measured is varied continuously.

Abstract: A dual-purpose carrier tray is specially adapted for packing and shipping either a plurality of ceramic substrates and/or ceramic BGA packages. The carrier tray includes a tray member having a plurality of pockets disposed therein for packing and storing the plurality of ceramic substrates and/or ceramic BGA packages. Semicircularly depressed support members are provided to support only the lower surface adjacent corresponding corners of the plurality of ceramic substrates and/or ceramic BGA packages. A plurality of stand-offs are provided for contactly engaging only the top surface of the plurality of substrates and/or BGA packages adjacent its corners in a lower tray member when stacked so as to retain firmly the substrates and/or BGA packages in the pockets.

Abstract: A method for fabricating metal lines in multilevel VLSI semiconductor integrated circuit devices is provided so as to reduce parasitic capacitance. An undercutting etching step is performed so as to form trenches underneath the metal lines for accommodating air voids, followed by forming an intra-layer dielectric between the metal lines and into the trenches so as to form air voids underneath the metal lines. As a result, the parasitic capacitance will be decreased.

Abstract: A method and system for preventing a source of ultra-purified water from being contaminated with chemicals includes a source of ultra-purified water and a reservoir containing a chemical source. The reservoir has a chemical delivery valve and a chemical outlet pipe coupled to a chemical delivery line for supplying chemicals to a process chamber during a chemical delivery mode of operation. A first controllable inlet valve has its outlet coupled to the chemical delivery line and the source of ultra-purified water for supplying the ultra-purified water from the source of ultra-purified water to the process chamber during a flushing mode of operation. A second controllable inlet valve has an outlet coupled to the inlet of the first controllable inlet valve and an inlet coupled to the source of ultra-purified water. A source of gas under pressure is coupled between the outlet of the second controllable inlet valve and the inlet of said first controllable inlet valve for creating a virtual air gap.

Abstract: A recursive voltage booster circuit is provided for generating a boosted output voltage to be higher than the low power supply potential to drive control gates via row decoder circuits and wordlines in an array of Flash EEPROM memory cells during a Read mode of operation. The voltage booster circuit includes a plurality of recursively connected boosting stages. The lower power supply potential has a voltage of +2.0 volts or lower. The boosted output voltage is significantly higher than what is traditionally available so as to enable reading of Flash EEPROM memory cells in a very low power supply voltage environment.

Abstract: A deep submicron MOS device having a self-aligned silicide gate structure and a method for forming the same is provided so as to overcome the problems of poly-Si depletion and boron penetration. A first Nickel silicide layer is formed between a gate oxide and a polycrystalline silicon gate electrode. Further, second Nickel silicide layers are formed over highly-doped source/drain regions. In this fashion, the reliability of the MOS device will be enhanced.

Abstract: A reference voltage generation circuit is provided for use in gate oxide protected circuits for generating an NMOS reference voltage and PMOS reference voltage in which the NMOS reference voltage is independent of an I/O buffer power supply potential and in which the PMOS reference voltage tracks the supply voltage. The reference voltage generation circuit includes a bandgap voltage reference circuit, a first operational amplifier, a voltage divider and a second operational amplifier. In one embodiment, the NMOS reference voltage is approximately +2.2 volts and is referenced with respect to ground. The PMOS reference voltage is approximately +1.1 volts and referenced with respect to the I/O buffer power supply voltage and the NMOS reference voltage.

Abstract: There is provided an improved high-voltage generation circuit for use in a mixed signal circuit for multiplying an external power supply potential applied on its input to produce a higher output voltage at an output terminal. The high-voltage generation circuit is formed of a voltage multiplier circuit (114), a voltage comparator circuit (116), and switching circuitry (118). The voltage multiplier circuit is formed of a first stage (122) and at least one second stage (124) connected in series between the input terminal and the output terminal. The second stage is formed of a CMOS transistor (MP4) whose substrate is connected to a controlled node (N23). The voltage comparator circuit compares the external power supply potential and the output voltage and generates a control logic signal.

Abstract: There is provided an improved metallization stack structure and a method for fabricating the same so as to produce a higher electromigration resistance and yet maintain a relatively low resistivity. The metallization stack structure includes a pure copper layer sandwiched between a top thin doped copper layer and a bottom thin doped copper layer. The top and bottom thin doped copper layers produce a higher electromigration resistance. The pure copper layer produces a relatively low resistivity.

Abstract: A PCMCIA card carrier for packing and shipping of a plurality of PCMCIA cards in a vertical side-by-side arrangement is formed of a tray member and a cover member. The tray member includes a plurality of first vertical slots disposed therein. A plurality of PCMCIA cards are disposed in the plurality of first vertical slots. The cover member has a plurality of second vertical slots disposed therein which are vertically aligned with corresponding ones of the first vertical slots in the tray member when the cover member is placed on top of the tray member. The tray and cover members have ledge portions in which are formed interlocking members so as to latch together the cover member with the tray member.

Abstract: A high density leaded ball-grid array package for packaging an integrated-circuit die includes a laminated substrate formed of a non-conductive layer sandwiched between first and second conductive trace patterns. A leadframe is directly attached onto the first conductive trace pattern of the laminated substrate by a non-conductive adhesive so that the open portion thereof overlies a central region of the laminated substrate. An integrated-circuit die is mounted in the central region of the laminated substrate. Bonding wires are interconnected between bonding pads formed on the integrated-circuit die and bonding fingers formed on the leadframe. A plastic material is molded over the top surface of the die, bonding fingers and bonding wires. A solder mask is applied on the second conductive trace pattern so as to form selective solderable areas. Finally, solder balls are attached to the selective solderable areas.