Abstract: A transceiver includes a receiver unit including a clock and data recovery unit. The transceiver includes a transmitter unit and a digital core coupled to the receiver unit and the transmitter unit. A switch circuit is positioned after the clock and data recovery unit, and is configured to route data from the receiver unit to the transmitter unit in a test mode of the transceiver.

Abstract: One aspect is an integrated circuit arrangement. The arrangement includes a first terminal, which can be brought to a first supply potential, a second terminal, which can be brought to a second supply potential, and a supply potential path formed between the first terminal and the second terminal. There is an electrostatic discharge element at least in the supply potential path. There is a signal input pad, to which an input signal can be applied and a signal output, at an output signal can be provided. A first inductance is arranged between the signal input pad and the signal output, and a second inductance is arranged between the signal output and the first terminal.

Abstract: A semiconductor component including a lateral transistor component is disclosed. One embodiment provides an electrically insulating carrier layer. A first and a second semiconductor layer are arranged on above another and are separated from another by a dielectric layer. The first semiconductor layer includes a polycrystalline semiconductor material, an amorphous semiconductor material or an organic semiconductor material. In the first semiconductor layer: a source zone, a body zone, a drift zone and a drain zone are provided. In the second semiconductor layer; a drift control zone is arranged adjacent to the drift zone, including a control terminal at a first lateral end for applying a control potential, and is coupled to the drain zone via a rectifying element at a second lateral end. A gate electrode is arranged adjacent to the body zone and is dielectrically insulated from the body zone by a gate dielectric layer.

Abstract: A semiconductor device includes a substrate having a chip island, a chip attached to the chip island, and encapsulation material deposited on the chip and part of the chip island. The chip island includes a first main face to which the chip is attached opposite a second main face, with the second main face of the chip island defining at least one cavity.

Abstract: Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element.

Abstract: A semiconductor arrangement including a load transistor and a sense transistor that are integrated in a semiconductor body. One embodiment provides a number of transistor cells integrated in the semiconductor body, each transistor cell including a first active transistor region. A number of first contact electrodes, each of the contact electrodes contacting the first active transistor regions through contact plugs. A second contact electrode contacts a first group of the first contact electrodes, but not contacting a second group of the first contact electrodes. The transistor cells being contacted by first contact electrodes of the first group form a load transistor, with the second electrode forming a load terminal of the load transistor. The transistor cells being contacted by first contact electrodes of the second group form a sense transistor.

Abstract: One aspect is a circuit arrangement having a load current path with a load transistor having a first and a second load path terminal and a control terminal. A first measurement current path includes a measuring transistor having a first and a second load path terminal and a control terminal. The control terminals and first load path terminals of the load transistor and the measuring transistor are coupled. A first regulating circuit has a controllable resistor and is designed to drive the resistor depending on electrical potentials at the second load path terminals of the load transistor and of the measuring transistor. A current mirror circuit is coupled between the first measurement current path and a second measurement current path. A deactivation circuit is designed to deactivate the first regulating circuit depending on a current flowing through the measuring transistor.

Abstract: A system including a sense layer, a first pinned layer and a first interlayer. The first pinned layer is held in a fixed magnetic orientation. The first interlayer is configured to couple the sense layer and the first pinned layer and provide a magnetic orientation in the sense layer that is 90 degrees from the fixed magnetic orientation. The magnetic orientation in the sense layer rotates in response to an external magnetic field.

Abstract: The invention concerns a module comprising a carrier element, a semiconductor device mounted on said carrier element and a silicon-based insulating layer. The silicon-based insulating layer is arranged on the side of the carrier element opposite to the semiconductor device. The invention further concerns a module comprising a semiconductor device, a mold compound at least partly covering the semiconductor device and a silicon-based passivation layer. The silicon-based passivation layer covers at least partly the periphery of the mold compound.

Abstract: An integrated circuit including a storage capacitor suitable for use in a DRAM cell, as well as to a method of manufacturing such a storage capacitor is disclosed. The storage capacitor is formed at least partially above a semiconductor substrate surface. The invention also includes a memory array employing the storage capacitor.

Abstract: A semiconductor component includes a semiconductor body having a first side, a second side, an edge delimiting the semiconductor body in a lateral direction, an inner region and an edge region. A first semiconductor zone of a first conduction type is arranged in the inner region and in the edge region. A second semiconductor zone of a second conduction type is arranged in the inner region and adjacent to the first semiconductor zone. A trench is arranged in the edge region and has first and second sidewalls and a bottom, and extends into the semiconductor body. A doped first sidewall zone of the second conduction type is adjacent to the first sidewall of the trench. A doped second sidewall zone of the second conduction type is adjacent to the second sidewall of the trench. A doped bottom zone of the second conduction type is adjacent to the bottom of the trench. Doping concentrations of the sidewall zones are lower than a doping concentration of the bottom zone.

Abstract: An integrated circuit including a field effect controllable trench transistor having two-control electrodes is disclosed. One embodiment provides a trench having a first control electrode and a second control electrode. A first electrical line is provided in an edge structure for electrically contact-connecting second control electrode.

Abstract: A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high resistivity region and at least an insulating structure is provided insulating the first well from the second well. The insulating structure extends through the buried high resistivity region and includes a conductive plug in Ohmic contact with the first semiconductor region. A method for forming an integrated semiconductor device is also provided.

Abstract: An electronic assembly includes electronic modules connected in a series circuit such that a particular number of input connections of one of the electronic modules is connected with the particular number of output connections of another of the electronic modules. Each electronic module is configured to pass on an information which each electronic module receives on an input side at an nth of each electronic module's input connections to an nth of each electronic module's output connections. The input connections and output connections of each electronic module are arranged in a same geometric arrangement.

Abstract: A semiconductor device includes a semiconductor chip having a through-connection extending between a first main face of the semiconductor chip and a second main face of the semiconductor chip opposite the first main face, encapsulation material at least partially encapsulating the semiconductor chip, and a first metal layer disposed over the encapsulation material and connected with the through-connection.

Abstract: A system and method allow accurate calculation of probe float through optical free-hanging and electrical planarity measurement techniques. In accordance with an examplary embodiment, probe float may be determined by acquiring a free-hanging planarity measurement, obtaining a first electrical contact planarity measurement, and calculating probe float using results of the acquiring and the obtaining operations.

Abstract: A system including a first concentrator, a second concentrator, and a magnet. The first concentrator has a first partial hub. The second concentrator has a second partial hub aligned with the first partial hub to form a bore. The magnet is situated in the bore and the first concentrator and the second concentrator guide magnetic flux from the magnet to sense movement of the magnet relative to the first concentrator and the second concentrator.