Abstract: A semiconductor module having a semiconductor chip stack and a method for producing the same is disclosed. In one embodiment, a thermally conductive layer with anisotropically thermally conductive particles is arranged between the semiconductor chips. The anisotropically thermally conductive particles have a lower thermal conductivity in a direction vertically with respect to the layer or the film than in a direction of the layer or the film.

Abstract: In a semiconductor memory system having a loop forward architecture, the command, address and write data stream and the separate read data stream in form of protocol-based frames transmitted to/from memory chips in the following order: memory controller to the first memory chip, to the second memory chip, to the third memory chip and to the fourth memory chip and the read data stream is transferred from the fourth memory chip to the memory controller. With each command usually one of four memory chips is accessed for data processing, while three of four memory chips have only to fulfil a simple re-drive of CAwD stream and read data stream. By separately transferring a rank select signal not embedded in the frame from the memory controller to each memory chip a lot of more flexibility for these tasks can be achieved.

Abstract: A recipient verification system including a strap, a pocket, a tether, and a label strip. The strap is configured for placement about a wearer's appendage (e.g., wrist, ankle, etc.). The pocket is coupled to the strap and forms an interior region that is exteriorly accessible via an open end. A portion of the tether is permanently captured at the pocket. The label strip is attached to the tether. The tether and the attached label strip are repeatedly transitionable between a first state and a second state. In the first state, the tether and at least a majority of the label strip is within the pocket, and thus protected. In the second state, at least a majority of the label strip is outside of the interior region of the pocket, and available for use by a user.

Abstract: A semiconductor component having a semiconductor body includes an active region and a marginal region surrounding the active region. The marginal region extends from the active region as far as an edge of the semiconductor body. A zone composed of porous material is formed in the marginal region.

Abstract: A pseudo dual-port memory device is disclosed. One embodiment provides an internal data RAM for a microprocessor, and a method for operating a memory device. In one embodiment, a memory device for a microprocessor or microcontroller comprises: a first part with memory cells that are single-port memory cells; and a second part with memory cells that are dual-port memory cells. In another embodiment, a method for operating a memory device is provided, the memory device including at least one single-port memory and at least one dual-port memory, the method including: accessing the single-port memory of the memory device when a non-conflicting access is to be carried out at the memory device; and accessing the dual-port memory of the memory device when a conflicting access is to be carried out at the memory device.

Abstract: An integrated circuit includes a semiconductor substrate, a first electrical contact formed on the semiconductor substrate, and a first heat sink element bonded to the first electrical contact via a galvanic bond.

Abstract: A semiconductor device with a charge carrier compensation structure in a semiconductor body and to a method for its production. The semiconductor body includes drift zones of a first conduction type and charge compensation zones of a second conduction type complementing the first conduction type. The drift zones include a semiconductor material applied in epitaxial growth zones, wherein the epitaxial growth zones include an epitaxially grown semiconductor material which is non-doped to lightly doped. Towards the substrate, the epitaxial growth zones are provided with a first conduction type incorporated by ion implantation over the entire surface and with selectively introduced doping material zones of a second, complementary conduction type. Towards the front side, the epitaxial growth zones are provided with a second, complementary conduction type incorporated by ion implantation over the entire surface and with selectively introduced doping material zones of the first conduction type.

Abstract: A method of manufacturing a semiconductor device includes placing a chip on a carrier, and applying an electrically conducting layer to the chip and the carrier. The method additionally includes converting the electrically conducting layer into an electrically insulating layer.

Abstract: A drug pump including a housing, reservoir, access port, flow restrictor mechanism, and refill port. The housing defines a discharge outlet, and maintains the reservoir in fluid communication with the refill port. The access port is fluidly connected to the discharge outlet. The flow restrictor mechanism is fluidly connected between the discharge outlet and the access port, positioned to establish outflow and inflow directions. The flow restrictor mechanism has flow restriction characteristics in the outflow direction that differ from flow restriction characteristics in the inflow direction. The flow restrictor mechanism partially restricts fluid flow in the outflow direction such that a clinician can sense a difference between an available injection rate through the access port as compared to through the refill port. Further, the flow restrictor mechanism does not overtly impede fluid withdrawal procedures via the access port.

Abstract: A method for producing a buried n-doped semiconductor zone in a semiconductor body. In one embodiment, the method includes producing an oxygen concentration at least in the region to be doped in the semiconductor body. The semiconductor body is irradiated via one side with nondoping particles for producing defects in the region to be doped. A thermal process is carried out. The invention additionally relates to a semiconductor component with a field stop zone.

Abstract: A transistor component having a shielding structure. One embodiment provides a source terminal, a drain terminal and control terminal. A source zone of a first conductivity type is connected to the source terminal. A drain zone of the first conductivity type is connected to the drain terminal. A drift zone is arranged between the source zone and the drain zone. A junction control structure is provided for controlling a junction zone in the drift zone between the drain zone and the source zone, at least including one control zone. A shielding structure is arranged in the drift zone between the junction control structure and the drain zone and at least includes a shielding zone of a second conductivity type being complementarily to the first conductivity type. The shielding zone is connected to a terminal for a shielding potential.

Abstract: One aspect is a circuit arrangement including a first semiconductor switching element, a second semiconductor switching element connected in series with the first semiconductor switching element and a freewheeling element connected in parallel with the second semiconductor switching element.

Abstract: A film frame aligner for automatically aligning a film frame includes a film frame support, a film frame pusher for pushing the film frame, and a film frame location mechanism for locating at least one notch in the film frame.

Abstract: A method for insulating a semiconducting material in a trench from a substrate, wherein the trench is formed in the substrate and comprising an upper portion and a lower portion, the lower portion being lined with a first insulating layer and filled, at least partially, with a semiconducting material, comprises an isotropic etching of the substrate and the semiconducting material, and forming a second insulating layer in the trench, wherein the second insulating layer covers, at least partially, the substrate and the semiconducting material.

Abstract: A semiconductor device and method. One embodiment provides an integral array of first carriers and an integral array of second carries connected to the integral array of first carriers. First semiconductor chips are arranged on the integral array of first carriers. The integral array of second carriers is arranged over the first semiconductor chips.