Abstract: An open eye needle including an elongated portion, a tip portion and an open eye portion. The tip portion is attached to the elongated portion. The open eye portion is attached to the elongated portion. The open eye portion includes a tongue portion, an eye region and a channel. The eye region is defined by the tongue portion. The channel extends around the tongue portion and intersects the eye portion. The channel includes a first channel portion and a second channel portion that extends from the first channel portion. The first channel portion is oriented at an acute angle with respect to the second channel portion. The second channel portion is in communication with the eye region.

Abstract: One embodiment provides a circuit arrangement integrated in a semiconductor body. At least one power semiconductor component integrated in the semiconductor body and having a control connection and a load connection is provided. A resistance component is thermally coupled to the power semiconductor component and likewise integrated into the semiconductor body and arranged between the control connection and the load connection of the power semiconductor component. The resistance component has a temperature-dependent resistance characteristic curve. A driving and evaluation unit is designed to evaluate the current through the resistance component or the voltage drop across the resistance component and provides a temperature signal dependent thereon.

Abstract: A power semiconductor module is disclosed. One embodiment includes a multilayer substrate having a plurality of metal layers and a plurality of ceramic layers, where the ceramic layers are located between the metal layers.

Abstract: An implantable medical device system includes an implantable device and an external locator device for percutaneously locating detecting port opening of the implantable device. The implantable device includes a port chamber forming the port opening, a septum sealing the port chamber relative to an exterior of the device, and a coil positioned at a known location relative to the port opening. The locator device includes a controller, at least one X-loop electrically coupled to the controller and oriented along a first major axis, and at least one Y-loop electrically coupled to the controller and oriented along a second major axis differing from the first major axis. The system is configured such that when the locator is spatially proximate the coil, an induced voltage in at least the Y-loop(s) is read by the controller to indicate a location of the coil relative to the locator device.

Abstract: A system including a spinning current Hall sensor and a chopping circuit. The spinning current Hall sensor is configured to provide input signals and the chopping circuit is configured to receive the input signals. Spinning phases of the spinning current Hall sensor are lengthened in residual offset adjustment phases to obtain signals that correspond to the residual offset voltages of the spinning phases.

Abstract: A method for reducing variations in the bending of rolled metal base plates for semiconductor modules is disclosed. In this method, the base plates are rolled in their longitudinal direction in a specific manner.

Abstract: An integrated circuit includes a substrate and an inductive device on a first side of the substrate. The integrated circuit includes a first ferromagnetic material on a second side of the substrate opposite the first side.

Abstract: A circuit assembly includes a power semiconductor module and, arranged externally thereto, a controller wherein the power semiconductor module comprises at least one controllable power semiconductor as well as at least one driver gating the latter, and controller and power semiconductor module each comprising a transceiver configured to communicate control signals between the controller and the power semiconductor module via an electromagnetic communication link unidirectionally or bidirectionally.

Abstract: A method of signal communication includes receiving a selection signal, and selecting a selected frequency range used for a multi-carrier signal communication from a set of predetermined frequency ranges for signal communication depending on the selection signal. The set of predetermined frequency ranges includes a first frequency range and a second frequency range including the first frequency range.

Abstract: One aspect relates to a computer system including a first data processing unit, a second data processing unit and a data transmission/memory device. The data transmission/memory can transmit sets of data from the first data processing unit to the second data processing unit. The data transmission/memory device includes a first memory region and a second memory region.

Abstract: A rail car extension system including a first main rail section, a second main rail section and a plurality of bow structures. The first main rail section is mounted with respect to an upper surface of the first side wall. The first main rail section includes a first upper rail portion and a first lower rail portion that extends from the first upper rail portion. The second main rail section is mounted with respect to an upper surface of the second side wall. The second main rail section includes a second upper rail portion and a second lower rail portion that extends from the second upper rail portion. The plurality of bow structures are each attached to and extend between the first main rail section and the second main rail section.

Abstract: A system including an output node and receiver front ends. The receiver front ends are configured to receive an input signal. Each of the receiver front ends is configured to receive the input signal and provide an output signal at the output node. At least one of the receiver front ends is configured to selectively consume less power.

Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first surface, an active area and a peripheral area. The semiconductor device further includes least one channel stop trench formed in the semiconductor substrate, wherein the channel stop trench extends from the first surface at least partially into the semiconductor substrate and is arranged between the active area and the peripheral area. At least one electrode is arranged in the channel stop trench. The semiconductor substrate includes at least a peripheral contact region, which is arranged in the peripheral area at the first surface of the semiconductor substrate. A conductive layer is provided and in electrical contact with the electrode arranged in the channel stop trench and in electrical contact with the peripheral contact region. The conductive layer is electrically connected to the semiconductor substrate merely in the peripheral area and electrically insulated from the semiconductor substrate in the active area.

Abstract: An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate.

Abstract: A device including two mounting surfaces. One embodiment provides a power semiconductor chip and having a first electrode on a first surface and a second electrode on a second surface opposite to the first surface. A first external contact element and a second external contact element, are both electrically coupled to the first electrode of the semiconductor chip. A third external contact element and a fourth external contact element, both electrically coupled to the second electrode of the semiconductor chip. A first mounting surface is provided on which the first and third external contact elements are disposed. A second mounting surface is provided on which the second and fourth external contact elements are disposed.

Abstract: A method of automatically classifying a concurrency object includes intercepting a call that is configured to create the concurrency object. Concurrency type information for the concurrency object is identified based on the call. The type information indicates whether the concurrency object is a lock object or a synchronization object. The concurrency type information is associated with the concurrency object.

Abstract: A semiconductor module and a method. One embodiment provides a housing with a housing frame and a pluggable carrier which is plugged in the housing frame. The pluggable carrier is equipped with a lead which includes an internal portion which is arranged inside the housing, and an external portion which is arranged outside the housing. The internal portion is electrically coupled to an electric component of the power semiconductor module. The external portion allows for electrically coupling the power semiconductor module.

Abstract: A semiconductor device includes a first sensor element in a first branch of a Wheatstone bridge and a second sensor element in a second branch of the Wheatstone bridge. The semiconductor device includes a first reference element in the first branch and a second reference element in the second branch. The semiconductor device includes a circuit configured to switch the first sensor element to the second branch and the second sensor element to the first branch.

Abstract: A sensor module. One embodiment provides a cap whose perimeter defines a rim. A first semiconductor chip is attached to the cap. The first semiconductor chip includes first connection elements. The rim and the first connection elements define a common plane.

Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.