Abstract: A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

Abstract: A pulse width modulation (PWM) modulator includes an integrator generating an integrated signal based on an input signal and an output signal, a low pass filter (LPF) receiving the integrated signal and performing low pass filtering, a comparator receiving an output signal of the LPF and a predetermined reference signal, comparing the received signals, and outputting a PWM signal, a dead time setup block outputting a first signal and a second signal having a predetermined phase difference therebetween based on the PWM signal, and a power stage buffering the first and second signals and generating the output signal based on a result of buffering. In the PWM modulator and a class-D amplifier having the PWM modulator, EMI can be reduced.

Abstract: An integrated circuit comprising a memory cell array capable of simultaneously performing data read and write operations is provided. The integrated circuit to which inputs and outputs (IOs) are separately provided and to which a write address and a read address are simultaneously input during one period of a clock signal comprises a plurality of memory blocks, the memory blocks comprising a plurality of sub-memory blocks, a plurality of data memory blocks corresponding to the memory blocks, and a tag memory controlling unit, which writes data to the memory blocks or reads data from the memory blocks in response to the write address or the read address, wherein access to the same sub-memory block is not simultaneously performed when the write address and the read address are the same.

Abstract: A method of verifying the power off effect of a design entity of a digital system includes a device model, a test input signal model, and a test output signal model specified in a hardware design language, at a register transfer level (RTL). The device model describes function blocks for performing predetermined functions using a plurality of power sources. The device model includes a model for a case where all of the power sources are supplied and a model for a case where one or more of the power sources are blocked. The test input signal model describes a test input signal to be input to the device model to verify the case where all of the power sources are supplied and the case where one or more of the power sources are blocked. The test output signal model describes a test output signal to be output from the device model in response to the test input signal.

Abstract: Disclosed is a transmissive and reflective type LCD. In the LCD, a second substrate faces a first substrate. A liquid crystal layer is formed between the first substrate and the second substrate. A first polarizing plate is formed on an outer surface of the first substrate. A second polarizing plate is formed on an outer surface of the second substrate. A backlight is arranged for irradiating incident light onto the polarizing plate. A transparent transflective film is arranged between the first polarizing plate and the backlight for partially reflecting and partially transmitting the incident light. The transparent transflective film includes at least a first layer and a second layer, the first and second layers having different refractivity indexes from each other and are alternatively stacked.

Abstract: A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface of the substrate and elongated direction, the cross section having a predetermined curvature, a channel region partially formed along the circumference of the semiconductor body, a tunneling insulating layer disposed on the channel region, a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region, an intergate insulating layer disposed on the floating gate, a control gate disposed on the intergate insulating layer and electrically insulated from the floating gate, and source and drain regions which are aligned with both sides of the control gate and formed within the semiconductor body.

Abstract: Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side region of a memory transistor, a drain region located on one side region of the selection transistor facing the source region, and a floating junction region formed between the memory transistor and the selection transistor, wherein the floating junction region includes a first doped region extended toward the source region under a region occupied by the memory transistor and a second doped region doped with the opposite conductive dopant to the first doped region and formed to surround the first doped region.

Abstract: A semiconductor memory device and a dummy line biasing method in which in the semiconductor memory device of a diode structure including a plurality of memory cells each having one variable resistance device and one diode device, the memory device includes a plurality of normal word lines, a plurality of normal bit lines, at least one or more dummy word lines and at least one or more dummy bit lines. The plurality of normal word lines are each arrayed in a first direction as a length direction. The plurality of normal bit lines are each arrayed in a second direction as a width direction, intersected with the first direction, so that the plurality of normal bit lines are intersected with the normal word lines. At least one or more dummy word lines are arrayed in the same structure as the normal word lines in the first direction, the at least one or more dummy word lines having a constant level of applied voltage.

Abstract: A method of programming a plurality of memory cells in a flash memory device from a first state to a second state includes verifying the plurality of memory cells using a verify voltage having a level increased according to an increase in a program loop number; and programming the plurality of memory cells using a program voltage having an increment decreased according to an increase in the program loop number, wherein the verifying and programming steps constitute a program loop, the program loop being terminated at a point in time when a level of the verify voltage reaches to a voltage range of the second state.

Abstract: There is provided a display apparatus including a data drive IC. The data drive IC includes a current-mode analog to digital converter (DAC) comprising a plurality of dynamic circuits (instead of conventional level shifters). In response to an enable signal received, each of the dynamic circuits convert a bit of an image data signal received from a signal input circuit into a high voltage level and outputs the resulting signal to a current switch that outputs current to a current node connected to a pixel. The data drive IC including the dynamic circuit has reduced chip area and reduced power consumption (compared to conventional ones comprising a plurality of level-shifters).

Abstract: Provided are a memory controller that selectively changes a frequency of a memory clock signal, a smart card including the memory controller, and a method of controlling a read operation of a memory. The memory controller includes a central processing unit (CPU), a memory interface, and a frequency change controller. The CPU outputs a read command signal in response to a data read request signal and outputs a write command signal in response to a data write request signal. The memory interface outputs a plurality of control signals in response to one of the read command signal and the write command signal, generates a memory clock signal based on a system clock signal, and changes a frequency of the memory clock signal in response to a frequency change control signal. The frequency change controller outputs the frequency change control signal in response to the plurality of control signals and the memory clock signal.

Abstract: Provided are a memory controller for controlling a refresh cycle of a memory and a method thereof. In this method, a temperature measure command is generated to measure an operating temperature of the memory. Next, a measured temperature in response to the temperature measure command is received. Then, a temperature difference between the measured temperature and a reference temperature is detected if the measured temperature is different from the reference temperature to change the refresh cycle according to the temperature difference, and if the measured temperature is equal to the reference temperature the method returns to the temperature measure command generating step. Thereafter, a refresh command is applied to the memory in response to the changed refresh cycle.

Abstract: An apparatus of driving a lamp for a display device is provided. The driving apparatus includes an inverter (920), a lamp current sensor (940), and an inverter controller (930). The lamp current sensor (940)senses a current flowing in the lamp and output a feedback signal having a magnitude depending on the sensed current. The inverter controller (930) compares a dimming control signal from an external device with the feedback signal and controls the inverter (920) based on the comparison. The inverter (920) includes a transformer (T1) for applying a lamp drive voltage to a lamp for turning on or off the lamp and a voltage sensor (928) sensing the lamp drive voltage. The inverter (920) adjusts a turns ratio of the transformer in accordance with the sensed lamp drive voltage.

Abstract: A method an apparatus for drying a wafer, and an apparatus for cleaning and drying a wafer are provided. In the apparatus for cleaning and drying a wafer, the wafer is dipped into a cleaning solution in a cleaning tank. The wafer is then dried using a drying gas in a drying chamber disposed over the cleaning tank. A shutter separates the cleaning tank from the drying tank. A wafer boat moves the wafer vertically between the cleaning tank and the drying tank. Nozzles for providing the cleaning solution onto the wafer are disposed at both inner sides of the drying tank. The nozzles are connected to a drying gas supply unit to alternately and periodically provide the drying gas onto the wafer.

Abstract: A memory device comprises a semiconductor substrate of a first conductive type, a memory transistor, a select transistor, a floating junction region, a common source region, and a bit line junction region. The floating junction region is formed of a second conductive type on the semiconductor substrate below a tunnel insulating film. The common source region of a second conductive type is formed on the semiconductor substrate adjacent a memory transistor gate and separated from the floating junction region. A bit line junction region of a second conductive type is formed on the semiconductor substrate adjacent a select transistor gate and is separated from the floating junction region, wherein the common source region includes a single junction region with a first doping concentration, and a depth of the common source region is shallower than a depth of the floating junction region and the bit line junction region.

Abstract: A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided.

Abstract: A method of controlling signal power level and a Bluetooth device for performing the same are provided. The method for controlling a power level of a signal to be transmitted to a remote Bluetooth device via a Bluetooth link, comprises: a local Bluetooth device for receiving a first signal from a remote Bluetooth device for determining if the remote Bluetooth device is providing a request to control a power level of the first signal to be transmitted; determining if a power level of a second signal is to be controlled based on a condition of a wireless link when the remote Bluetooth device does not provide the request to control the power level of the first signal; and controlling the power level of the second signal to be transmitted to the remote Bluetooth device.

Abstract: A drive circuit having impedance control includes an impedance matching array unit having a plurality of transistors, the plurality of transistors selectively driven in accordance with an array drive control signal generated by control code data, and an update prohibition control unit for generating a transfer control signal to prohibit driving the transistors during a first time interval occurring when internal data transition, and applying the transfer control signal to the impedance matching array unit.

Abstract: A memory controller and a semiconductor device comprising the same are provided. The semiconductor device comprises a memory block comprising a plurality of memory banks and a memory controller. The memory controller outputs an auto refresh command and memory bank information indicating a memory bank that is to be auto refreshed in an auto refresh mode. Thus, only the selected memory bank performs an auto refresh operation in the auto refresh mode while reducing current consumption in the semiconductor device.

Abstract: A circuit for enabling a sense amplifier in a semiconductor memory device includes a delay unit for outputting the delayed sense amplifier enable signal as a sense amplifier enable delay signal after delaying a sense amplifier enable signal in response to a delay control signal; and a delay control unit for controlling an intensity of the delay control signal by receiving a reference signal having a temperature reduction dependent characteristic. The length of the sensing time can increase by adjusting the delay at the sense amplifier enable signal according to a temperature decrease when a memory cell is formed on a silicon on insulator, and the sense amplifier enabling circuit is formed on a bulk silicon layer. In addition, the enable time point in the sense amplifier can be smoothly adjusted, and the possibility of operation failure in the semiconductor memory device can be reduced by reducing the occurrence of the sensing failure at the sense amplifier.