Abstract: A semiconductor device includes: a trench device isolating region formed in a substrate to define a photodiode active region; a channel stop impurity region formed in the substrate contacting the device isolating region, wherein the channel stop impurity region surrounds a bottom and a sidewall of the device isolating region; and a photodiode formed within the photodiode active region.

Abstract: A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided.

Abstract: A semiconductor memory device includes a memory cell array having memory cells arranged in rows and columns, a row decoder selecting one of the rows and activating the selected row, a bit-line sense amplifier detecting and amplifying data of the memory cells coupled to the selected row through the columns, a data-bus sense amplifier detecting and amplifying data output from the bit-line sense amplifier, and a control logic block enabling the bit-line and data-bus sense amplifiers in a reading operation, operating the data-bus sense amplifier in a semi-latch type mode for a predetermined period, and operating the data-bus sense amplifier in a full-latch type mode after the predetermined period.

Abstract: Noise may cause malfunction and reduction of yield in semiconductor devices operating with a low supply voltage, and a logic test is generally performed for testing characteristics of input/output pads. In the logic test, High Level Input Voltage (VIH), Low Level Input Voltage (VIL), and Input Signal Fault Detection may be considered. In a normal operation mode, the noise propagates through a logic chain by toggling of the test logic circuit, and a circuit can prevent the noise propagation using logical operations. Thus, a characteristic degradation due to the noise propagation may be reduced.

Abstract: A liquid crystal display includes a first substrate, a first electrode formed on the first substrate, a passivation layer formed between the first substrate and the first electrode, a second substrate facing the first substrate, a second electrode formed on the second substrate, a columnar spacer formed between the second substrate and the first substrate, and a liquid crystal layer having liquid crystal molecules vertically aligned with respect to the first and second substrates, and formed between the first and second substrates. The passivation layer and the columnar spacer are made of substantially the same material at the same layer.

Abstract: A device and method for preventing an integrated circuit from malfunctioning due to a surge voltage are provided. The device which is interposed between a node and a ground in the integrated circuit includes: a first material which is conductive; and a second material which is insulative, wherein a surface of the second material contacts a surface of the first material.

Abstract: An apparatus for manufacturing a liquid crystal display (LCD) device includes a table receiving an LCD panel thereon, a first grinding part grinding a surface of the LCD panel to a first surface roughness, a second grinding part grinding the surface of the LCD panel grinded to the first surface roughness to a second surface roughness, wherein the second surface roughness is smoother than the first surface roughness, and a polishing part polishing the surface of the LCD panel which is grinded to the second surface roughness.

Abstract: A display device includes a thin film transistor (TFT) substrate, a countering substrate facing the TFT substrate, a sealant, and a liquid crystal layer interposed between the TFT substrate and the countering substrate. The TFT substrate includes a substrate having a display area and a peripheral area, a first TFT formed in the peripheral area and including a semiconductor layer and a resistive contact member formed on the semiconductor layer, a light blocking semiconductor pattern, a second TFT formed in the display area and including a gate electrode. The sealant couples the TFT substrate to the countering substrate, and covers the first TFT.

Abstract: An electric fuse circuit including a first nonvolatile memory cell connected to a first bit line, a second nonvolatile memory cell connected to a second bit line, a latch connected to the first and second bit lines, and a bias current circuit supplying one of the first and second bit lines with variable bias currents through the latch in response to a bias control signal during a test operation.

Abstract: A fully differential amplifier includes a first single-ended current mirror type fully differential amplifier outputting a first output signal by two stage amplifying a difference between a first input signal and a second input signal and a second single-ended current mirror type fully differential amplifier outputting a second output signal by two stage amplifying a difference between the first input signal and the second input signal. A first tail of the first single-ended current mirror type fully differential amplifier and a second tail of the second single-ended current mirror type fully differential amplifier are connected to each other and the first output signal and the second output signal are differential signals.

Abstract: A liquid crystal display apparatus is disclosed. A first transparent electrode is disposed on an upper surface of the liquid crystal display panel for displaying an image. A second transparent electrode is disposed on a lower surface of a polarizer, and the second transparent electrode is opposite to the first transparent electrode. Accordingly, the entire thickness of the liquid crystal display apparatus may be decreased, and the manufacturing cost of the liquid crystal display apparatus may be reduced.

Abstract: Disclosed is a method of forming a pattern. A first organic polymer layer is formed on a substrate on which an underlying layer, and then a second organic polymer layer, which has an opening partially exposing the first organic polymer layer, is formed on the first organic polymer layer. Next, a silicon-containing polymer layer is formed on the second organic polymer layer to cover the opening. The silicon-containing polymer layer is oxidized and simultaneously the second organic polymer layer and the first organic polymer layer are ashed by oxygen plasma to form a pattern having an anisotropy-shape. The underlying layer is etched using the silicon-containing polymer layer and the first organic polymer layer as an etching mask to form a pattern.

Abstract: A universal serial bus (USB) device is comprised of a receiver for receiving signals from a USB host through data lines, and a pull-up resistor circuit connecting pull-up resistors to data lines in response to control signals. The pull-up resistor circuit selectively connects a plurality of pull-up resistors with a data line in response to control signals. The pull-up resistor circuit controls a number of the plurality of pull-up resistors connected with the data line to cause a voltage level of the signal to be lower than a threshold voltage when the USB host resets the USB device.

Abstract: An electronic circuit includes a transmission circuit transmitting an input signal of a first node as an output signal of a second node in response to a control signal and a discharge circuit selectively discharging the input signal of the first node in response to the control signal.

Abstract: A semiconductor memory device and a self-refresh method in which the semiconductor memory device includes a plurality of input/output ports having respective independent operation, a period of self-refresh through one of the plurality of input/output ports being subordinate to a kind of operation through another input/output port. Whereby, a refresh characteristic in a multi-port semiconductor memory device including a dual-port semiconductor memory device may be improved.

Abstract: An apparatus and method for removing a jammer signal in a wireless communication receiver, in which a frequency converter down-converts a radio frequency (RF) signal including a desired and a jammer signal into a baseband signal. A first filter removes the desired signal from an output signal of the frequency converter and outputs a jammer signal as an output signal. The frequency converter up-converts the jammers signal output from the first filter. The second filter outputs the up-converted jammer signal as an output signal. The first adder receives the RF signal and the output signal of the second filter and removes the jammer signal from the RF signal using the RF signal and the output signal of the second filter. Accordingly, the frequency converter down-converts the RF signal including the attended jammer signal.

Abstract: The present invention provides a semiconductor memory device comprising a memory cell array including a plurality of memory regions, an address decoding portion for decoding an address applied from an external portion for simultaneously selecting all of the plurality of memory regions during a test read operation, a data IO control portion for receiving test pattern data and writing the test pattern data to each of the plurality of memory regions during a test write operation, and reading the test pattern data from one of the plurality of memory regions and outputting the test pattern data during the test read operation, a data IO portion for receiving the test pattern data from the external portion and applying the test pattern data to the data IO control portion during the test write operation, and receiving the test pattern data output from the data IO control portion and conditionally outputting the test pattern data as test status data to the external portion in response to an output control signal durin

Abstract: A sense amplifier circuit of a semiconductor memory device and a method of operating the same, in which the sense amplifier circuit includes a bit line sense amplifier connected with a bit line to sense and amplify a signal of the bit line, and a calibration circuit calibrating a voltage level of the bit line based on a logic threshold value of the bit line sense amplifier. The bit line sense amplifier senses and amplifies the signal of the bit line after the voltage level of the bit line is calibrated. The bit line sense amplifier may include a 2-stage cascade latch, which includes a first inverter having an input terminal connected with the bit line; and a second inverter which has an input terminal connected with an output terminal of the first inverter and an output terminal connected with the bit line and is enabled/disabled in response to a sensing control signal.

Abstract: A liquid crystal display (LCD) driver including a normal mode circuit, a test pattern generating circuit, a selection circuit, and a timing controller. The normal mode circuit generates a normal mode signal related to a normal image data writing operation of an LCD. The test pattern generating circuit generates a test mode signal related to a test image data writing operation of the LCD. The selection circuit selects one of the normal mode signal and the test mode signal. The timing controller includes a memory storing image data that constructs a normal image pattern or a test image pattern displayed on an LCD panel of the LCD in response to an output signal of the selection circuit.

Abstract: An electronic circuit includes a digital-to-analog converter (DAC), and an active integrator. The DAC converts a digital output of the electronic circuit to an analog signal and feeds back the analog signal. The active integrator includes an operational amplifier having a first input terminal that receives a summed signal of an input signal and the fed back analog signal, and a second input terminal that receives a reference voltage. The DAC includes a coupling capacitor, first switches, at least one current source, second switches, and a third switch.