Abstract: A bit-line equalizer, a semiconductor memory device including the bit-line equalizer, and a method for manufacturing the bit-line equalizer, in which the bit-line equalizer includes: first and second polysilicon gates formed in a first direction in proximity to each other, the first and second polysilicon gates having a predetermined distance between them; and a plurality of equalizing transistors formed in a second direction along the first and second polysilicon gates, the equalizing transistors equalizing bit-line pairs, with the equalizing transistors being alternately formed in proximity to the first and second polysilicon gates. The bit-line equalizer can vary the widths of the equalizing transistors irrespective of a memory cell pitch in order to improve an equalizing time.

Abstract: An apparatus includes a drop unit, a transfer unit and a position adjusting unit. The drop unit drops droplets of an organic material. The transfer unit transfers the drop unit along a first direction. The position adjusting unit is interposed between the drop unit and the transfer unit to adjust a position of the drop unit. Therefore, the apparatus of dropping the organic material has a small size and may drop droplets of the organic material onto an accurate position. Furthermore, the transfer unit moves the drop unit quickly, and the position adjusting unit adjusts the position of the drop unit accurately. Therefore, a time difference for drying the organic material injected into a cavity is reduced.

Abstract: A synchronization circuit includes a first level-shifting unit receiving an input reference signal having a first swing voltage and generating a first level change signal having a second swing voltage and a second level change signal having a third swing voltage, and a synchronization unit generating first and second output signals by synchronizing the first level change signal with the second level change signal.

Abstract: A DC offset elimination device includes a first signal path that delivers a differential input signal pair from an input node to an output node and a second signal path that delivers a differential output signal pair from the output node to the input node. The second signal path includes a first transconductor having an input terminal coupled to the output node, an amplifier having an input terminal coupled to an output terminal of the first transconductor, a capacitor coupled in parallel to the amplifier, and a second transconductor coupled to the output terminal of the amplifier and to the input node.

Abstract: A light generating part generates a first light based on a first control signal. A first driving part outputs a panel driving signal. A display panel receives the first light or a second light that is provided from an exterior to display an image based on the panel driving signal. A sensing part outputs a sensing signal based on the second light. A second driving part compares a reference voltage range with the sensing signal to output the first control signal. The reference voltage range is determined by a first reference voltage and a second reference voltage. Therefore, the light generating part is turned on/off based on the second light to decrease the power consumption of the light generating part, and an operation of the light generating part is stabilized.

Abstract: A CCD-based solid state image sensing (imaging) device and a driving method, enabling three-color still or video image signal charge processing without requiring a frame memory buffer. By using horizontal electrodes to selectively assert predetermined vertical-driving signals of the vertical CCDs, the vertical CCDs receive and vertically transmit the image signals (charges) of active pairs of vertically adjacent rows. Each active pair of adjacent rows is separated by (at least) two (a pair of) inactive adjacent rows, and the image signal (charges) of the active pair of adjacent rows represent all three colors (R, G, B) of one line (or one field) of real-image pixels. A horizontal CCD receives the selected image signals (charges) for each active row among the active pairs of rows, and outputs the image signals (charges) for each active row by conventional horizontal transmission to an interpolator adapted to continuously output three-color pixel signals (e.g., digital signals), e.g.

Abstract: Provided are an integrated circuit device having two or more ports and a system for the device, where the device includes a first port for inputting and outputting data and a second port for inputting the data, and either the first port and/or the second port is selected by an external command when the data is input; the second port has ½n the number of pins of the first port, where n is a natural number; the device includes two or more ports that operate independently so that turn around time is reduced and the data bus efficiency of the integrated circuit device and the system are improved.

Abstract: A method of post-programming a flash memory device includes the steps of: post-programming memory cells of a selected word line in a predetermined unit; determining, after incrementing an address for selecting the next word line, whether the incremented address matches one of reference addresses; and varying the post-programming unit of the selected memory cells whenever the incremented address matches one of reference addresses.

Abstract: A semiconductor memory device and a read data skew control method thereof, in which a point of time when read data is output can he controlled using pad bonding in stack packages. The semiconductor memory device includes a bonding option pad and a delay control circuit that controls the point of time when data is output from an output buffer depending on logic states of a signal applied to the bonding option pad. Thus, when using the semiconductor memory device in stack packages, the read data skew generated as a result of a load on a bonding wire can be compensated by connecting the bonding option pad to ground voltage or a supply voltage.

Abstract: Provided is a semiconductor memory device testable with a single data rate (SDR) or a dual data rate (DDR) pattern in a merged data input/output pin (DQ) test mode. The device includes a first path circuit, a second path circuit, and a merged output generator configured to generate a merged data bit having a SDR and/or DDR pattern.

Abstract: An integrated circuit for generating a clock signal includes a voltage conversion unit, a maximum power determination unit, a clock control unit and a clock generator. The voltage conversion unit converts an external power supply voltage into an internal power supply voltage and detects a variance in current consumption of a functional block to generate a detected voltage wherein the functional block consumes a predetermined current using the internal power supply voltage. The maximum power determination unit determines a maximum current consumption of the functional block and converts the maximum current consumption to a corresponding maximum allowed voltage. The clock control unit generates at least one frequency control signal based on a comparison between the detected voltage and the maximum allowed voltage. The clock generator generates the clock signal whose frequency is adjusted according to the frequency control signal.

Abstract: A supply voltage removal detecting circuit, a display device and method for removing a latent image when a supply voltage is disconnected, in which the supply voltage removal detecting circuit includes a voltage controller, a detection signal generator, and an output unit. The voltage controller controls voltages such that when a first supply voltage and a second supply voltage stay at a first level, the voltage at a first node is greater than the voltage at a second node, and when the first supply voltage or the second supply voltage becomes a second level, the voltage at the second node stays at a specific level, and the voltage at the first node is less than the specific level. The detection signal generator generates a detection signal by comparing the voltage at the first node with the voltage at the second node.

Abstract: A semiconductor circuit for reducing flicker noise includes a negative-conductance generator and a body bias voltage supplying circuit. The negative-conductance generator includes a pair of cross-coupled field effect transistors in order to generate negative-conductance, wherein each field effect transistor includes a body. In order to remove flicker noise generated by the pair of the field effect transistors, the body bias voltage supplying circuit supplies a body bias voltage to the body of each of the pair of the field effect transistors so that a forward bias voltage is supplied to the body and source of each of the pair of the field effect transistors. The field effect transistors are preferably NMOS transistors or CMOS transistors. The semiconductor circuit is used in a voltage controlled oscillator (VCO) or a phase-locked loop (PLL).

Abstract: A memory core having an open bit line structure and a semiconductor memory device having the memory core includes an edge sub-array and a dummy bit line control circuit. The edge sub-array has a plurality of word lines, a plurality of bit lines and a plurality of dummy bit lines. The dummy bit line control circuit amplifies and latches voltage signals of the dummy bit lines in a test sensing mode. Accordingly, the semiconductor memory device having the memory core may test defects of the edge sub-array included in the memory core.

Abstract: A memory system includes at least one memory module, each of which has a pattern data generating circuit for generating a pattern data, which has a plurality of memories to which a command signal is commonly applied and corresponding data is applied respectively; and a memory controller for respectively applying the command signal and the corresponding data to the plurality of memories, applying a pattern data generating command to the memory module during a timing control operation, calculating time differences among data of reaching each of the plurality of memories using the pattern data outputted from each of the memories and receiving and outputting data using the calculated data reaching time difference. Therefore, a stable data transmission is achieved between the memory controller and the memories.

Abstract: A chip on film (COF) package comprising a test pad for testing the electrical function of a semiconductor chip and a method for manufacturing same are provided. The COF package comprises a semiconductor chip mounted on a base film, a signal-input portion for receiving data and control signals and transmitting the data and control signals to the semiconductor chip, a plurality of passive elements connected to terminals of the semiconductor chip, and a plurality of test pads for testing one or more terminals of the semiconductor chip that are not connected to the signal-input portion. The test pads of the COF package are capable of testing a plurality of internal terminals which are integrated into one terminal and do not connected to the signal-input portion, thereby easily testing the electrical function of the chip.

Abstract: A semiconductor memory device including a trimmed voltage generator and a method of generating a trimmed voltage in the semiconductor memory device, in which the semiconductor memory device includes a voltage trimming unit, memory cell array, and a trimming current generator. The voltage trimming unit outputs a first trimming current control signal corresponding to a difference between a predetermined internal voltage and an external voltage supplied from outside of the semiconductor memory device in a trimming mode. The memory cell array stores the first trimming current control signal in the trimming mode and outputs a second trimming current control signal corresponding to the first trimming current control signal in a normal mode. The trimming current generator outputs a trimming current corresponding to the first trimming current control signal in the trimming mode and outputs a trimming current corresponding to the second trimming current control signal in the normal mode.

Abstract: There is provided a source driver having a repair amplifier and method of processing signals. There is also provided a liquid crystal display device containing the source driver. The source driver drives adjacent source lines with source line driving signals. The repair amplifier amplifies the source line driving signal to drive a part of a source line.

Abstract: A data copy method includes designating data stored in a non-volatile memory device as data packages, reading at least one data package to store the read at least one data package in a temporary memory device, transferring the at least one data package stored in the temporary memory device to a volatile memory device using a direct memory access (DMA) operation, and reading a next at least one data package stored in the non-volatile memory device to store the next at least one data package in the temporary memory device. Transferring the at least one data package and reading the next at least one data package are simultaneously and parallelly performed. The data copy method according to exemplary embodiments of the present invention may improve data copy speed, and may reduce occupancy of a memory bus by performing the auto-loading function and simultaneously and parallelly performing the data package storing process and the data package transferring process.

Abstract: A photosensor is provided, which includes: a light receiver receiving an external light and generating a photovoltage corresponding to an amount of the received light; a voltage selector selectively outputting the photovoltage and a reference voltage; a current generator generating a sensor current depending on an output voltage of the voltage selector; and an output unit selectively outputting the sensor current from the current generator.