Abstract: A stack-type nonvolatile semiconductor device comprises a memory device formed on a substrate including a semiconductor body elongated in one direction, having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region on the semiconductor body along the circumference, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate on the semiconductor body, an inter-insulating layer on the memory device, and a conductive layer on the inter-insulating layer, and a memory device formed on the conductive layer including, a semiconductor body elongated in one direction having a cross section perpendicular to a main surface, having a predetermined curvature, a channel

Abstract: A backlight unit includes: a power supplying part; a non-dimming point light source receiving power from the power supplying part and providing a feed back signal to the power supplying part; a dimming control part outputting a dimming signal; and a plurality of dimming point light sources receiving power from the power supplying part, and receiving the dimming signal from the dimming control part.

Abstract: A semiconductor memory device includes an array having memory cells arranged in rows and columns; a clock-to-address converter for counting an external clock signal to generate an address for accessing the array based on the counted value, during a test operation mode; and a redundancy circuit for storing the address generated by the clock-to-address converter.

Abstract: An ambient light processing system for controlling a display device by sensing ambient light and a method using the system. The ambient light processing system includes a photo-detector, an amplification unit, an analog-to-digital converter and a controller. The photo-detector outputs a sensed signal corresponding to the luminous intensity of the ambient light. The amplification unit amplifies the sensed signal with a high amplification factor to output a first amplified signal and amplifies the sensed signal with a low amplification factor to output a second amplified signal. The analog-to-digital converter respectively converts the first amplified signal and the second amplified signal into a first digital signal and a second digital signal. The controller outputs a first control signal and a second control signal for controlling the display device in response to the first digital signal and the second digital signal.

Abstract: A time-to-digital converter includes a first delay line, a second delay line, comparators, and an encoder. The first delay line includes first resistors coupled in series and receives a first signal through a start node. The second delay line includes second resistors coupled in series and receives a second signal through a node corresponding to an end node of the first delay line. The comparators compare first voltages of nodes on the first delay line with second voltages of corresponding nodes on the second delay line. The encoder generates a digital code based on outputs of the comparators. Therefore, the time-to-digital converter may decrease a chip size thereof and lower power consumption, and the time-to-digital converter may increase a range of a maximum delay time between two signals.

Abstract: Provided are an apparatus and method for generating an internal voltage adaptively with respect to an external supply voltage. The apparatus includes a class detector and an internal voltage generator. The class detector outputs detection signals indicating a class of a plurality of classes, which correspond to predetermined voltages, to which an input external voltage belongs with respect to a first reference voltage. The internal voltage generator generates and outputs an internal voltage corresponding to the class to which the external voltage belongs as indicated by the detection signals.

Abstract: A liquid crystal display includes: a substrate; a pixel electrode disposed on the substrate and having a first subpixel electrode and a second subpixel electrode; and a common electrode facing the pixel electrode, wherein the first subpixel electrode has a pair of bent edges substantially parallel to each other, the second subpixel electrode has a pair of bent edges substantially parallel to each other, and the second subpixel electrode has a height greater than a height of the first subpixel electrode.

Abstract: Provided are a phase-change memory device and method that maintains a resistance of a phase-change material in a set state within a constant resistance range. In the method, data is provided to a first phase-change memory cell and then it is first determined whether data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are not identical, a complementary write current is provided to the first phase-change memory cell and it is second determined whether the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical, data is provided to a second phase-change memory cell.

Abstract: A voltage generation circuit and semiconductor memory device including the same are provided.

Abstract: Provided is a smart card for communicating with a host computer through a universal serial bus (USB). The smart card includes an internal clock signal generator to generate an internal clock signal, a period detector to detect a period of the internal clock signal and to generate a control code according to the detected period, and a transmission clock generator to generate a transmission clock signal which varies from the internal clock signal according to the control code. The smart card transfers data in sync with the transmission clock signal.

Abstract: A current mode bus interface system includes a host interface device configured to transmit a reference current and a clock current, and to transmit a data current during a first transfer mode, and to receive a reverse direction data current and compare the reverse direction data current with the reference current to generate a reverse direction data voltage during a second transfer mode; and a client interface device configured to receive the reference current and the clock current and compare the reference current with the clock current to generate a clock voltage, to receive the data current and compare the data current with the reference current to generate a data voltage during the first transfer mode, and to transmit the reverse direction data current through a conducting wire over which the data current is received during the second transfer mode.

Abstract: A gain controllable wide-band low noise amplifier includes a first transistor coupled to an input node and an output node and amplifying an input signal to generate an output signal, a second transistor allowing the output signal to feedback to the input node, and a control circuit complementarily controlling transconductance of the first and second transistors.

Abstract: A CMOS image sensor and a method for forming the same are provided. According to the method, a gate insulating layer and a doped polysilicon layer which are sequentially stacked on a substrate are patterned to form a transfer gate and a reset gate set apart from each other. A floating diffusion layer between the transfer gate and the reset gate, a light receiving element at a side of the transfer gate away from and opposite to the floating diffusion layer and a source/drain region at a side of the reset gate away from and opposite to the floating diffusion layer are formed. An insulation layer and a mold layer are sequentially formed on an entire surface of the substrate, and the mold layer is planarized until the insulation layer is exposed. The exposed insulation layer is removed to further expose an upper surface of the gates. A selective silicidation process is carried out using a metal gate layer to form a metal gate silicide on the exposed gate.

Abstract: A method of converting image signals for a display device including six-color subpixels is provided, which includes: classifying three-color input image signals into maximum, middle, and minimum; decomposing the classified signals into six-color components; determining a maximum among the six-color components; calculating a scaling factor; and extracting six-color output signals.

Abstract: A flash memory device including: a memory cell array having memory cells arranged in rows and columns; and a high voltage generator configured to generate a high voltage supplied into a source line of the memory cell array during a programming operation. The high voltage generator operates to vary the high voltage along an amount of current supplied into the memory cell array during the programming operation.

Abstract: Circuits and methods for controlling data I/O operations in semiconductor memory devices to provide variable data I/O widths for read, write and active memory operations. Circuits and methods for selectively controlling a data width of a data I/O buffer “on the fly” to enable variable data I/O widths during memory access operations.

Abstract: A high input voltage tolerant input/output circuit includes a pad, a clamping circuit clamping a high voltage applied to the pad to generate a clamping signal, and a buffer unit transmitting an input signal received by the pad to an internal circuit and outputting data of the internal circuit to the pad in response to the clamping signal. The buffer unit includes stacked NMOS transistors. When a high voltage higher than a power supply voltage is applied to the pad, the stacked NMOS transistors are turned on, and the stacked NMOS transistors are prevented from being destroyed by the high voltage. When an electrostatic discharge voltage is applied to the pad, the stacked NMOS transistors are turned off, and the stacked NMOS transistors are prevented from being destroyed by electrostatic discharge current.

Abstract: A method of driving a non-volatile memory device includes programming a plurality of memory cells based on a first data copied from a program data buffer to a verification data buffer, verifying the memory cells by overwriting a result of the verification of the programmed memory cells to a verification data buffer, and re-verifying the memory cells by repeating the programming and verifying operations at least once with respect to the memory cells that were successfully verified, based on the verification result written to the verification data buffer.

Abstract: A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided.

Abstract: A high-performance programmable logic array (PLA) includes an AND plane that is initialized when a reset signal is activated and that evaluates a plurality of input signals when the reset signal is inactivated; and or OR plane that receives output signals of the AND plane, that is disabled when one of the output signals is activated, and that evaluates the rest of the output signals of the AND plane to output a final result signal when the one of the output signals of the AND plane is inactivated. The PLA uses a reset signal as a driving signal, instead of a clock signal. Accordingly, it is possible to realize a PLA with both low power consumption and high operation speed.