Abstract: A voltage reference circuit and a current reference circuit using a vertical bipolar junction transistor (BJT) implemented by a deep N-well complementary metal-oxide semiconductor (CMOS) process, wherein the voltage reference circuit generates a constant reference voltage regardless of temperature and includes an amplifier element having a positive input terminal and a negative input terminal, a first transistor, and a second transistor. The first transistor is electrically connected to the positive input terminal and the second transistor is electrically connected to the negative input terminal. Each of the first and second transistors is a vertical BJT implemented by a deep N-well CMOS process, and the reference voltage is calculated by adding a base-emitter voltage of one of the first and second transistors to a value obtained by multiplying a thermal voltage by a predetermined factor.

Abstract: A nonvolatile memory device includes a semiconductor substrate; a source region that is formed in the semiconductor substrate; a gate insulating film that is formed so as to partially overlap the source region on the semiconductor substrate; a floating gate that is formed on the gate insulating film so as to have a structure forming a uniform electric field in the portion that overlaps the source region; a control gate that is formed so as to be electrically isolated along one sidewall of the floating gate from an upper part of the floating gate, an inter-gate insulating film that is interposed between the floating gate and the control gate, and a drain region that is formed so as to be adjacent the other side of the control gate.

Abstract: Provided is a wordline driving circuit and method for a semiconductor memory, in which the wordline driving circuit includes an address decoding signal generator and a wordline voltage supplier. The address decoding signal generator receives a first row address decoding signal (URA) and generates a delayed URA signal (PXID). The wordline voltage supplier has a pull-up transistor for providing the PXID signal to a selected wordline in response to a second row address decoding signal (LRA). The address decoding signal generator sets the PXID signal to a floating state before the selection of the wordline to prevent a leakage current from flowing through the pull-up transistor in a standby mode.

Abstract: An output driver capable of controlling a short circuit current includes a driving unit and a driving control unit. The driving unit receives a first driving signal and a second driving signal in response to a control signal and generates an output signal. The driving unit control unit includes a driving unit copying unit having the same construction as the driving unit and compares an output copying signal generated from the first and second driving signals by the driving unit copying unit with a reference voltage and generates the control signal that controls delays of the first and second driving signals in a test mode.

Abstract: A pre-emphasis circuit capable of controlling the slew rate of a signal output from a buffer that transfers the output signal to an output driver to increase the range of a controllable voltage step includes a first buffer, a second buffer, and an output driver. The first buffer buffers first and second main input signals having phases opposite to each other, outputs first and second main output signals, and controls slew rates of the first and second main output signals using at least one main control signal. The second buffer buffers first and second sub-input signals having phases opposite to each other, outputs first and sub-output signals, and controls slew rates of the first and second sub-output signals using at least one sub-control signal. The output driver generates first and second output signals having opposite phases using at least two control signals and the output signals of the first and second buffers.

Abstract: A flash memory device includes a memory cell array having a first region and a second region that include memory cells arranged in a plurality of rows and columns; an address storage circuit adapted to store address information for defining the second region; a row decoder circuit adapted to select one of the first and second regions in response to an external address; a voltage generating circuit adapted to generate a read voltage to be provided to a row of the selected region by the row decoder circuit during a read operation; a detecting circuit adapted to detect whether the selected region is included in the second region on the basis of address information and external address information that are stored in the address storage circuit; and a control logic adapted to control the voltage generating circuit in response to an output of the detecting circuit during the read operation.

Abstract: A single slope ADC using a hysteresis property includes a first comparator, a second comparator, and a code generating unit. The first comparator outputs a compared signal by receiving and comparing an input signal having a constant level with a ramp signal, the second comparator has a hysteresis property having an input terminal connected to an output terminal of the first comparator, and the code generating unit is connected to the second comparator and outputs a digital code corresponding to a time-point of a state transition of an output signal of the second comparator. The second comparator can be embodied as a Schmidt trigger or a Schmidt-trigger inverter. The single slope ADC further includes a controller that controls at least one of a rising threshold or a failing threshold of the Schmidt trigger or of the Schmidt-trigger inverter.

Abstract: In a method of fabricating a liquid crystal display device, when a photoresist film formed on a substrate for the liquid crystal display device is exposed and developed, protrusions are formed on the substrate for increasing a viewing angle of the liquid crystal display device. Although the substrate is formed with step differences thereon caused by various intermediate films, the protrusions may have a same size since an exposure amount to the photoresist film is varied according to the step differences of the substrate on which the protrusions are formed. Thus, the liquid crystal display device may have an improved display quality.

Abstract: A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes a read command buffer to provide the read signal. The latency circuit receives the read signal, and provides a latency signal having a difference of a predetermined time corresponding to CAS latency with respect to the read signal in response to the transfer signal.

Abstract: A non-volatile memory device includes isolation layers, a cell trench, a floating gate, a common source region and a word line. The isolation layers define an active region of a substrate. The cell trench is formed in the active region. The cell trench extends in a first direction. The floating gate is formed on the active region and in the cell trench. The common source region is formed on the active region adjacent a second side face of the floating gate and extends in a second direction substantially perpendicular to the first direction. The word line is formed on the active region, which is adjacent to a first side face of the floating gate opposite to the second side face, and the isolation layers and in the cell trench. The word line extends in the second direction.

Abstract: An operational amplifier includes a differential amplifier including an active load, a current mirror including a first branch and a second branch, a first switch connected between a first power source and an output node and switched in response to a voltage of a first output terminal of the differential amplifier, a first bias circuit to control an amount of a reference current flowing in the first branch in response to a voltage of a second output terminal of the differential amplifier, a second bias circuit to control a voltage of the second branch in which a mirror current flows, in response to a voltage of the first output terminal, a second switch connected between the output node and a second power source and switched in response to a voltage of the second branch, and a capacitor connected between the output node and the first output terminal.

Abstract: A first wiring is formed on an array substrate, such that the first wiring has a first protrusion. A second wiring is formed on a different layer from that of the first wiring, such that a portion of the second wiring overlaps with the first protrusion. A protection layer that covers the first and second wirings is formed, such that the protection layer has first and second contact holes that expose the first and second wirings, respectively. Then, a third wiring that electrically connects the first wiring to the second wiring through the first and second contact holes is formed. When electrical connection between the first and second wirings is abnormal, a laser beam is irradiated toward the first protrusion, so that the electrical connection may be repaired.

Abstract: The present invention relates to a thin film transistor and a liquid crystal display. A gate electrode is formed to include at least one portion extending in a direction perpendicular to a gain growing direction in order to make electrical charge mobility of TFTs uniform without increasing the size of the driving circuit. A thin film transistor according to the present invention includes a semiconductor pattern a thin film of poly-crystalline silicon containing grown grains on the insulating substrate. The semiconductor pattern includes a channel region and source and drain regions opposite with respect to the channel region. A gate insulating layer covers the semiconductor pattern. On the gate insulating layer, a gate electrode including at least one portion extending in a direction crossing the growing direction of the grains and overlapping the channel region is formed.

Abstract: A temperature detecting circuit is provided. The temperature detecting circuit includes a reference and detection voltage generator for generating a reference voltage corresponding to a first and a second reference current, and changing first to M-th (M being a natural number) detection currents based on first to M-th temperature detection codes to generate first to M-th detection voltages corresponding to the changed first to M-th detection currents and the second reference current; a temperature detection signal generator for comparing each of the first to M-th detection voltages with the reference voltage to generate first to M-th temperature detection signals; and a temperature detection controller for detecting an operation temperature of a semiconductor device while changing the first to M-th temperature detection codes in response to the first to M-th temperature detection signals from the temperature detection signal generator.

Abstract: A CMOS active pixel sensor includes a photodiode, a transmitting transistor, a reset transistor, a fingered type source follower transistor and a selecting transistor, where the photodiode generates charge in response to incident light, the transmitting transistor transmits the charge stored in the photodiode to a sensing node, the reset transistor, coupled to a power supply voltage, resets a voltage of the sensing node so that the sensing node has substantially a level of the power supply voltage, the fingered type source follower transistor amplifies the voltage of the sensing node, the selecting transistor transmits a voltage of a source electrode of the fingered type source follower transistor into an internal circuit in response to a selection signal, thus, the channel width of the source follower transistor may be increased, and the MOS device noise due to the source follower transistor may be reduced.

Abstract: A liquid crystal display having improved retardation plate is described. In the liquid crystal display, at least one of two panel plates has a polarizer placed on an outer side which is opposite to a liquid crystal layer and a quarter wavelength retardation plate between a substrate glass and the polarizer. The quarter wavelength retardation plate is composed of two retardation films including a half wavelength and a quarter wavelength retardation film. A slow axis of a half ? film which is adjacent to the polarizer makes an angle of ?1 with a transmissive axis of the polarizer and that of a quarter ? film which is adjacent to the substrate glass makes an angle of ?2 where ?2=2×?1±45 degree. The retardation films are single-axial films. The specific angle ?1 is one of degree values (15, 75, 105, and 165).

Abstract: A liquid crystal display is provided, which includes: groups of gate lines transmitting a gate-on voltage; data lines alternately transmitting normal data voltages and an impulsive data voltage; pixels arranged in a matrix and including switching elements that are connected to the gate lines and the data lines and turn on in response to the gate-on voltage to transmit the data voltages; gate driving circuits connected to respective groups of gate lines and sequentially applying the gate-on voltage to the gate lines; a data driver applying the data voltages to the data lines; a duty ratio selector outputting a duty ratio selection signal informing a selected duty ratio; and a signal controller controlling the gate driver and the data driver based on the duty ratio selection signal, wherein the signal controller determines a time for the application of the impulsive data voltage based on the duty ratio selection signal.

Abstract: A display panel assembly capable of improving image display quality and a display apparatus having the display panel, wherein the display panel assembly includes a display panel and a transflective member. The display panel includes two substrates and a liquid crystal layer interposed between the two substrates. The transflective member is disposed under the display panel to transmit a backlight toward a front of the display panel and to reflect a front light having passed through the display panel back toward the front of the display panel. Therefore, the front light is partially reflected by the transflective member to increase a luminance of the display apparatus, thereby improving the image display quality.

Abstract: A pulsed flip-flop capable of adjusting a pulse width according to an operating voltage includes: a flip-flop operating in synchronization with a pulse signal; a pulse generating circuit generating the pulse signal in response to a clock signal; and a pulse width control circuit reducing a width of the pulse signal generated by the pulse generating circuit when the operating voltage is lower than a reference voltage.

Abstract: An internal reference voltage generating circuit that reduces a standby current and the number of pins of a semiconductor memory device, in which a reference voltage is provided to an input buffer that receives a signal through an input to which an on die transmitor resistor is connected, includes: a voltage dividing circuit outputting the reference voltage by a power voltage; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input and a voltage level of an end of the voltage dividing circuit, and controlling the on resistor value of the pull down driver according to a result of the comparison. The internal reference voltage generating circuit is operated while the memory controller inputs a signal into a mode register set (MRS) to enable the internal reference voltage generating circuit and the output signal of the MRS is activated.