Abstract: A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G2) in a fixed relationship to the semiconductor active area thereby defining a first source/drain region (R1) adjacent a first gate structure sidewall and a second source/drain region (R2) adjacent a second sidewall gate structure. The method also forms a lightly doped diffused region (801) formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure.

Abstract: A wireless communication system (10). The system comprises a user station (12). The user station comprises despreading circuitry (22) for receiving and despreading a plurality of slots received from at least a first transmit antenna (A121) and a second transmit antenna (A122) at a transmitting station (14). Each of the plurality of slots comprises a first channel (DPCH) comprising a first set of pilot symbols and a second channel (PCCPCH) comprising a second set of pilot symbols. The user station further comprises circuitry (50) for measuring a first channel measurement (&agr;1,n) for each given slot in the plurality of slots from the first transmit antenna and in response to the first set of pilot symbols in the given slot. The user station further comprises circuitry (50) for measuring a second channel measurement (&agr;2,n) for each given slot in the plurality of slots from the second transmit antenna and in response to the first set of pilot symbols in the given slot.

Abstract: A multiple block adder is provided wherein carry select adder (CSA) is used in the most significant bit (MSB) block, a carry increment adder (CIA) is used in the least significant bit block and a combination of carry increment adder (CIA) and carry lookahead adder (CLA) circuit is used in the middle block.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a multi-layer hard mask. The multi-layer hard mask comprises a hard masking layer overlying an etch stop layer. The etch stop layer is substantially more selective than the overlying masking layer with respect to an etch employed to remove the bottom electrode diffusion barrier layer. Therefore during an etch of the capacitor stack, an etch of the bottom electrode diffusion barrier layer results in a substantially complete removal of the hard masking layer. However, due to the substantial selectivity (e.g., 10:1 or more) of the etch stop layer with respect to the overlying masking layer, the etch stop layer completely protects the underlying top electrode, thereby preventing exposure thereof.

Abstract: An image processing apparatus (800) for a charge coupled device having hot/cold pixel and line noise filtering is disclosed which provides optical black and offset correction. The present invention teaches an offset and optical black correction circuit having a digital filter to obtain noise-free optical black correction for charge-coupled devices such that a digitally programmable bandwidth exists. The sum of the channel offset and optical black level is averaged for a given number of lines having a number of optical black cells per line and this sum passes through a digital filter. Moreover, the channel is digitally calibrated to obtain a user programmed ADC (810) output which corresponds to that average.

Abstract: This invention describes a unique high-speed implementation for overflow detection logic to be used in high performance shifter functions. The overflow logic makes use of parallelism in combining shift value decoding and mask generation logic with the logic necessary to propagate data. Designs for both 16-bit and 32-bit shifters are presented and performance improvement of the new designs over conventional overflow detection circuits is demonstrated.

Abstract: An improved spatial light modulator package comprising a spatial light modulator 1006 attached to a central region of a substrate 1004, a sealing ring 1002 on said substrate 1004 around the central region thereof, a window frame 402 attached to the sealing ring 1002, and a window 404 glued to the window frame 402. Gluing the window 404 to the window frame 402 avoids distortion of the glass that occurs when the window is heat bonded to the window frame, and avoids having to grind and polish the glass window after it is bonded to the window frame.

Abstract: A connector pad includes projections extending radially outwardly from an inner portion of the pad to help stabilize and reinforce the pad. The added stability allows the radial thickness of an inner portion of the pad to be reduced. This decreases the surface area of the pad and reduces the opportunity for capacitive build up to occur relative to an associated conductive plane in a circuit board.

Abstract: A gain boost circuit is provided in a differential amplifier including differentially connected first and second input transistors the drains of which are coupled to sources of first and second cascode transistors. A third cascode transistor has a source coupled to a drain of the first cascode transistor and a drain coupled to a bias current source. A gain boost amplifier has an output coupled to the gate of the third cascode transistor, a first input coupled to the drain of the first cascode transistor, and a second input coupled to the drain of the second cascode transistor.

Abstract: Bias current in output transistors of a class AB output stage is controlled by providing equal amplification to both an output of an input stage (2) of an amplifier and an output (17,18) of a class AB control circuit (46). A split input transistor circuit structure for a first side of the differential input stage (2) includes first (15) and second (16) input transistors with gates coupled to a first input (Vin+). A third input transistor (10) of the input stage has a gate coupled to a second input (Vin−). A split folded common gate cascode circuit includes first (25) and second (30) cascode transistors having their drains coupled to gates of the output transistors, respectively, and a third cascode transistor has a source coupled to a drain of the third input transistor.

Abstract: A wireless receiver (UST). The receiver comprises at least one antenna (ATU) for receiving a plurality of frames (FR) in a form of a plurality of paths. Each of the plurality of frames comprises a plurality of time slots (SLN), and each of the plurality of time slots comprises a plurality of symbols. Further, each of the plurality of paths has a corresponding sample position, wherein the plurality of symbols comprise a primary synchronization code symbol (PSC). The receiver further comprises circuitry (52) for correlating a primary synchronization code across a group of the plurality of symbols, and circuitry for identifying a plurality of path positions within the group. Each of the plurality of path positions corresponds to a respective one of a plurality of largest-amplitude paths represented within the group as detected in response to the circuitry for correlating.

Abstract: A method for generating a translation display includes receiving a source file (414) including a plurality of source elements (422) and a translation file (418) including a plurality of translation elements (426) corresponding to the source elements (422). The source and translation files (414 and 418) are partitioned into a plurality of partitions (458). Each partition (458) has a group of source elements (422) and a group of all translation elements (426) corresponding to the group of source elements (422). The corresponding source and translation groups are aligned for display.

Abstract: A bus bridge is defined to provide an interface between two AHB buses. These busses normally have separate requirements but both must provide high performance. The first is for transfer of data from CPU to memory and peripherals. The second is to support the transfer of a large amount of data by a single peripheral to local memory or other local peripherals. The AHB-to-HTB bus bridge provides a means for the interfacing these two separate AHB buses allowing communication between them and securing data integrity. The bus bridge of this invention is defined to be an AHB memory bus slave but a high performance data transfer bus master.

Abstract: A computer algebra system including algebraic expression transformations with a display of domain of definition constraints only when a domain of definition differs from that of an antecedent expression.

Abstract: A digital image two-step resizing of filtering an entire image followed by selective row and column deletions. The filtering may use a kernel generated as three samples from a continuous kernel.

Abstract: A method for measuring a test differential voltage across a first output and a second output of a transmitter integrated circuit device, the test differential voltage corresponding to a voltage across the first output and second output appearing while the device is providing an output while being subjected to a voltages applied across a resistor network connected to the differential outputs, the resistor network including first resistor having a value of Ra connected between the first output and a first voltage, a second resistor having a value of Rb connected between the second output and a second voltage, and a third resistor having a value of Rc connected between the first output and the second output.

Abstract: A leadframe for use in the assembly of integrated circuit (IC) chips, which has first and second surfaces and a base metal structure (606) with an adherent layer (607) of nickel having a rough, non-reflecting surface covering the base metal. This rough nickel enhances adhesion to molding compounds. An adherent layer (608) of smooth, reflective nickel selectively covers the first surface of the leadframe in areas intended for attachment of bonding wires and the IC chip. This smooth nickel facilitates the use of vision systems. A first adherent metal layer (609) is deposited in selected areas of the first leadframe surface for wire bond attachment, and a second adherent metal layer (610) is deposited to provide attachment to external parts.

Abstract: The present invention forms a nitrided dielectric layer without substantial harm to a semiconductor layer on which the dielectric layer is formed. The invention employs a multi-stage process in which dielectric sub-layers are individually nitrided before formation of a next dielectric sub-layer. The net result is a nitrided multi-layered dielectric layer comprised of a plurality of dielectric sub-layers wherein the sub-layers have been individually deposited and incorporated with nitrogen.

Abstract: A data processing system (e.g., microprocessor 30) for packing register data while storing it to memory and unpacking data read from memory while loading it into registers using single processor instructions. The system comprises a memory (42) and a central processing unit core (44) with at least one register file (76). The core is responsive to a load instruction (e.g., LDW_BH[U] instruction 184) to retrieve at least one data word from memory and parse the data word over selected parts of at least two data registers in the register file. The core is responsive to a store instruction (e.g., STBH_W instruction 198) to concatenate data from selected parts of at least two data registers into at least one data word and save the data word to memory. The number of data registers is greater than the number of data words parsed into or concatenated from the data registers. Both memory storage space and central processor unit resources are utilized efficiently when working with packed data.

Abstract: Systems and methods are provided for detecting a state change of a level shifter and actively driving the level shifter into the new state to facilitate the recovery of the level shifter. The system and method also provide logic for setting up the level shifter for the next transition. A transition of a high logic to low logic of a first internal node and a second internal node is monitored. The first internal node and the second internal node transition between opposing logic levels, such that one internal node is pulled low and the other internal node is pulled high. The monitor determines when one node is pulled low and actively drives the other node to a logic high to facilitate the recovery of the level shifter.