Abstract: An internal impedance of a battery (30) is automatically determined by operating a processor (13) to analyze current flowing through the battery to determine if a transient condition due to change of current is occurring and determining when the transient condition has ended. A voltage of the battery is measured while a steady current is being supplied by the battery. The present depth of discharge (DOD) of the battery is determined and a database is accessed to determine a corresponding value of open circuit voltage. The internal impedance is computed by dividing the difference between the measured voltage of the battery and the open circuit voltage at the present DOD by an average value of the steady current.

Abstract: Semiconductor device fabrication methods are provided in which a carbon-containing region is formed in a wafer to inhibit diffusion of dopants during fabrication. Front-end thermal processing operations, such as oxidation and/or anneal processes, are performed at high temperatures for short durations in order to mitigate out-diffusion of carbon from the carbon-containing region, such that carbon remains to inhibit or mitigate dopant diffusion.

Abstract: A circuit for detecting a serial signal comprises a first circuit (400) coupled to receive the serial signal (200) during a predetermined plurality of time periods of substantially equal duration. The first circuit is coupled to receive a first code (414). The first circuit is arranged to compare a part of the serial signal corresponding to each time period of the plurality of time periods to the first code, thereby producing a match signal. The first circuit accumulates the match signal from each of the each time period of the plurality of time periods.

Abstract: A leadframe for use in the assembly of integrated circuit (IC) chips, which has first and second surfaces and a base metal structure (606) with an adherent layer (607) of nickel having a rough, non-reflecting surface covering the base metal. This rough nickel enhances adhesion to molding compounds. An adherent layer (608) of smooth, reflective nickel selectively covers the first surface of the leadframe in areas intended for attachment of bonding wires and the IC chip. This smooth nickel facilitates the use of vision systems. A first adherent metal layer (609) is deposited in selected areas of the first leadframe surface for wire bond attachment, and a second adherent metal layer (610) is deposited to provide attachment to external parts.

Abstract: An image processing apparatus (800) for a charge coupled device having hot/cold pixel and line noise filtering is disclosed which provides optical black and offset correction. The present invention teaches an offset and optical black correction circuit having a digital filter to obtain noise-free optical black correction for charge-coupled devices such that a digitally programmable bandwidth exists. The sum of the channel offset and optical black level is averaged for a given number of lines having a number of optical black cells per line and this sum passes through a digital filter. Moreover, the channel is digitally calibrated to obtain a user programmed ADC (810) output which corresponds to that average.

Abstract: A method of improving shallow trench isolation (STI) gap fill and moat nitride pull back is provided by after the steps of growing a pad oxide, depositing a nitride layer on the pad oxide and the steps of moat patterning, moat etching and moat clean, the steps of growing thermal oxide, deglazing a part of a part of the moat nitride; depositing a thin nitride liner, etching the nitride to form a thin side wall nitride in the STI trench; and performing an oxide Hydroflouric (HF) acid deglazing before STI liner oxidating and depositing oxide to fill the trench.

Abstract: A connector pad includes projections extending radially outwardly from an inner portion of the pad to help stabilize and reinforce the pad. The added stability allows the radial thickness of an inner portion of the pad to be reduced. This decreases the surface area of the pad and reduces the opportunity for capacitive build up to occur relative to an associated conductive plane in a circuit board.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a multi-layer hard mask. The multi-layer hard mask comprises a hard masking layer overlying an etch stop layer. The etch stop layer is substantially more selective than the overlying masking layer with respect to an etch employed to remove the bottom electrode diffusion barrier layer. Therefore during an etch of the capacitor stack, an etch of the bottom electrode diffusion barrier layer results in a substantially complete removal of the hard masking layer. However, due to the substantial selectivity (e.g., 10:1 or more) of the etch stop layer with respect to the overlying masking layer, the etch stop layer completely protects the underlying top electrode, thereby preventing exposure thereof.

Abstract: A method and apparatus for modeling a neural synapse function in analog hardware whereby the multiplication function inherent to the operation of a neural synapse is computed by applying a voltage on the gate-source terminals and an independent voltage on drain-source terminals of a MOSFET further using the resultant drain current of the latter device in non-saturation mode as function implementing a computation essentially close to multiplication function between the aforesaid voltages. Analog circuit is provided, capable of generating an output current signal which is proportional in magnitude, within a certain range, to a function computing essentially a sum of weighted input signals—products of corresponding pair of current input signal, and voltage control signal applied to a plurality of inputs thus capable of constructing an artificial neuron model.

Abstract: A circuit relates to phase and frequency-locked loop circuits (PLL and FLL circuits) with a controllable tracking oscillator whose signal phase relationship or frequency, respectively, is influenced by an external parameter, a reference oscillator, as well as a phase or frequency comparator, the output signal of which is used to control the tracking oscillator in such a way that any phase or frequency errors are reduced. A circuit provides for an element for the measurement of the external parameter (such as a microprocessor) which is capable of receiving a signal representing the output signal of the phase or frequency comparator, and convert it into a measurement value that represents the present value of the external parameter. This external parameter can, for example, represent the ambient temperature or the supply voltage of the tracking oscillator.

Abstract: An improved spatial light modulator package comprising a spatial light modulator 1006 attached to a central region of a substrate 1004, a sealing ring 1002 on said substrate 1004 around the central region thereof, a window frame 402 attached to the sealing ring 1002, and a window 404 glued to the window frame 402. Gluing the window 404 to the window frame 402 avoids distortion of the glass that occurs when the window is heat bonded to the window frame, and avoids having to grind and polish the glass window after it is bonded to the window frame.

Abstract: A data processing system (e.g., microprocessor 30) for packing register data while storing it to memory and unpacking data read from memory while loading it into registers using single processor instructions. The system comprises a memory (42) and a central processing unit core (44) with at least one register file (76). The core is responsive to a load instruction (e.g., LDW_BH[U] instruction 184) to retrieve at least one data word from memory and parse the data word over selected parts of at least two data registers in the register file. The core is responsive to a store instruction (e.g., STBH_W instruction 198) to concatenate data from selected parts of at least two data registers into at least one data word and save the data word to memory. The number of data registers is greater than the number of data words parsed into or concatenated from the data registers. Both memory storage space and central processor unit resources are utilized efficiently when working with packed data.

Abstract: A display system (200) in which light from source (202) is focused onto a spinning color wheel (204). The spinning color wheel (204) spins at a constant rate and creates of beam of light that changes from one primary color to the next in rapid sequence. The primary colored beam of light impinges a spatial light modulator (206), which is often a DMD or LCD. A controller (208) receives an input video signal and determines the native frame rate of the image source. The controller (208) sends image data to the spatial light modulator (206) in synchronization with the color wheel (204)—image data representing the red portions of the image is sent during the period in which the red color filter is passing through the beam of light—at the native frame rate of the image source. The modulated light is focused onto an image plane (210) by projection lens (212) to form an image. The eye of the viewer integrates the sequential primary color images giving the perception of a single full-color image.

Abstract: A computer algebra system including algebraic expression transformations with a display of domain of definition constraints only when a domain of definition differs from that of an antecedent expression.

Abstract: This invention describes a unique high-speed implementation for overflow detection logic to be used in high performance shifter functions. The overflow logic makes use of parallelism in combining shift value decoding and mask generation logic with the logic necessary to propagate data. Designs for both 16-bit and 32-bit shifters are presented and performance improvement of the new designs over conventional overflow detection circuits is demonstrated.

Abstract: A method for generating a translation display includes receiving a source file (414) including a plurality of source elements (422) and a translation file (418) including a plurality of translation elements (426) corresponding to the source elements (422). The source and translation files (414 and 418) are partitioned into a plurality of partitions (458). Each partition (458) has a group of source elements (422) and a group of all translation elements (426) corresponding to the group of source elements (422). The corresponding source and translation groups are aligned for display.

Abstract: A method for measuring a test differential voltage across a first output and a second output of a transmitter integrated circuit device, the test differential voltage corresponding to a voltage across the first output and second output appearing while the device is providing an output while being subjected to a voltages applied across a resistor network connected to the differential outputs, the resistor network including first resistor having a value of Ra connected between the first output and a first voltage, a second resistor having a value of Rb connected between the second output and a second voltage, and a third resistor having a value of Rc connected between the first output and the second output.

Abstract: A bus bridge is defined to provide an interface between two AHB buses. These busses normally have separate requirements but both must provide high performance. The first is for transfer of data from CPU to memory and peripherals. The second is to support the transfer of a large amount of data by a single peripheral to local memory or other local peripherals. The AHB-to-HTB bus bridge provides a means for the interfacing these two separate AHB buses allowing communication between them and securing data integrity. The bus bridge of this invention is defined to be an AHB memory bus slave but a high performance data transfer bus master.

Abstract: Systems and methods are provided for detecting a state change of a level shifter and actively driving the level shifter into the new state to facilitate the recovery of the level shifter. The system and method also provide logic for setting up the level shifter for the next transition. A transition of a high logic to low logic of a first internal node and a second internal node is monitored. The first internal node and the second internal node transition between opposing logic levels, such that one internal node is pulled low and the other internal node is pulled high. The monitor determines when one node is pulled low and actively drives the other node to a logic high to facilitate the recovery of the level shifter.

Abstract: Bias current in output transistors of a class AB output stage is controlled by providing equal amplification to both an output of an input stage (2) of an amplifier and an output (17,18) of a class AB control circuit (46). A split input transistor circuit structure for a first side of the differential input stage (2) includes first (15) and second (16) input transistors with gates coupled to a first input (Vin+). A third input transistor (10) of the input stage has a gate coupled to a second input (Vin−). A split folded common gate cascode circuit includes first (25) and second (30) cascode transistors having their drains coupled to gates of the output transistors, respectively, and a third cascode transistor has a source coupled to a drain of the third input transistor.