Abstract: The voltage outputs of a charge coupled device (CCD) are examined to determine the hot pixels. A black pixel is determined to be a hot pixel if the voltage level associated with the black pixel exceeds the voltage level of an adjacent (e.g., previous) pixel by a threshold. If the present black pixel is determined to be a hot pixel, a previous black pixel is substituted for a present black pixel in the computation of the offset. However, if the first black pixel is determined to be a hot pixel, the second black pixel is used in lieu of the first black pixel. The offset is iteratively adjusted by an amount proportionate to an error determined based on the black pixels. The adjustment may be clipped by a threshold to avoid bands in the image.

Abstract: A differential circuit with linearity correction loop includes a main differential amplifier 30, and a correction amplifier 20 having inputs coupled to the outputs of the main differential amplifier 30 through feedback paths. The output signals from the correction amplifier 20 are combined with the inputs to the main amplifier 30 such that a negative feedback loop is formed around the differential circuit. This feedback loop provides stability with only a minor power increase.

Abstract: A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate, and both having a depletion region when reverse biased. The shallow regions are surrounded in part by an enhanced p-doping implant pocket. The transistor further has in these regions of enhanced p-doping another region of a p-resistivity higher than the remainder of the semiconductor. These regions extend laterally approximately from the inner border of the respective shallow region to the inner border of the respective recessed region, and vertically from a depth just below the depletion regions of source and drain to approximately the top of the channel stop regions.

Abstract: A method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a conductive structure over the semiconductor substrate (step 106 of FIG. 1); and forming a layer of high-dielectric constant material between the conductive structure and the semiconductor substrate (step 102 of FIG. 1), the layer of high-dielectric constant material is formed by supplying a gaseous silicon source and a second gaseous material which is comprised of a material selected from the group consisting of: Hf, Zr, La, Y, Sc, Ce and any combination thereof.

Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least portion a portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.

Abstract: A solderless test interface (10) includes a thin, flexible, electrically insulative sheet (20) having metal plated through-holes (24) formed in the pattern of the external ball contacts (54) of a semiconductor device (14). The termini (26, 30) of the holes (24) on the surface of the sheet (20) are also plated. The metal (40) is coated with a soft metal (42) which will cold-flow under force. The sheet is inserted between the ball contacts (54) and a test board (18). Force is applied to the test board and/or the device to engage and deform the soft metal (42) at the hole termini (26, 30) by its engagement with the balls (54) and pads (16) on the test board. The deformation ensures a low resistance electrical path between the balls and the pads during testing of the device.

Abstract: A device for generating electricity includes a first portion including a first wall defining a first fluid passage and a second portion including a second wall defining a second fluid passage. A generator is coupled between the first and second portions and is capable of generating electricity in response to flow of a fluid from the first fluid passage to the second fluid passage through the generator. The generator is capable of generating electricity sufficient to power one or more electronic devices coupled to the generator. The flow of the fluid is associated with activity of a biological system of a user, for example, cardio-pulmonary activity of the user.

Abstract: A method and apparatus for routing messages in a wireless network. Transmissions from all devices are synchronized. Each device is equipped with a routing unit that checks incoming messages for integrity, discards “corrupt” messages, compares non-corrupt messages to the last transmitted message, and applies a set of rules to determine when and what the device should next receive or transmit. The synchronized transmissions and integrity checking process detect true collisions, which occur when multiple transmitters have attempted to send different messages to the same receiver. The comparing process ensures that messages are transmitted only if not previously transmitted, thereby avoiding loop problems.

Abstract: This invention has enabled a new, simple nanoporous dielectric fabrication method. In general, this invention uses a polyol, such as glycerol, as a solvent. This new method allows both bulk and thin film aerogels to be made without supercritical drying, freeze drying, or a surface modification step before drying. Prior art aerogels have required at least one of these steps to prevent substantial pore collapse during drying. Thus, this invention allows production of nanoporous dielectrics at room temperature and atmospheric pressure, without a separate surface modification step. Although not required to prevent substantial densification, this new method does not exclude the use of supercritical drying or surface modification steps prior to drying. In general, this new method is compatible with most prior art aerogel techniques. Although this new method allows fabrication of aerogels without substantial pore collapse during drying, there may be some permanent shrinkage during aging and/or drying.

Abstract: A method for improving high-&kgr; gate dielectric film (104) properties. The high-&kgr; film (104) is subjected to a two step anneal sequence. The first anneal is a high temperature anneal in a non-oxidizing ambient (106) such as N2 to densify the high-&kgr; film (104). The second anneal is a lower temperature anneal in an oxidizing ambient (108) to perform a mild oxidation that heals the high-&kgr; film and reduces interface defects.

Abstract: A dot product operator (30) uses adder trees (10) of L-1 adders and no multiplication circuits, where L is the length of the parallel dot product operator. Exclusive-or gates 12 provide the function of multiplication by ±1, with the carry-in ports of adders (14, 16, 18, 20, 32, 34, 36, 42) being used to form the two's complement, resulting in an extremely efficient design in terms of area and power.

Abstract: A semiconductor device having reduced self and mutual capacitance of bonded wires is provided by coating the wires with a foamed polymer effectively having a very low dielectric constant. Additional benefits are realized by electrically insulating the wires against short-circuiting, by cushioning, the wires with a low modulus sheath, and by protecting chip bond pad metallization.

Abstract: In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. When a packet is received by a shared high level data link controller, the data signal groups are processed and placed in a temporary storage unit. The address signal group of the received packet is applied to channel block unit where the digital signal processor subsystem, to which the packet is directed, is identified and an INTERRUPT signal corresponding to the identified digital signal processor subsystem is generated. The INTERRUPT signal is applied to a switch. The switch, which receives the signal groups from the temporary storage unit, directs the signal groups to a buffer memory in the channel associated with the identified signal processing subsystem.

Abstract: A spindle motor control circuit for controlling a motor; including a control circuit to control the motor during at least a low state, a pulse state and a high state, the motor braking during said low state, the control circuit receiving a flyback voltage from the motor during the pulse state and the control circuit receiving a reduced flyback voltage from the motor during the high state.

Abstract: A transport stream with embedded projector configuration data 208 being carried along with the video for use in digital cinema projector setup. The embedded configuration data consists of sub-packets 304 of setup data information for such parameters as gamma tables, color management system information, relative luminance level, format and range of the sampled data, 3D/2D presentation information, frame rate, image size, aspect ratio, font tables, and language provision. This approach assures that the projector 404 is setup properly and also permits on-the-fly changes to the projector's parameters, which may be used for artistic effects in the movie.

Abstract: An optical correlator (10) that uses a spatial light modulator (11) to illuminate a pattern of on and off pixels into a length of an optical fiber (12). The spatial light modulator (11) is optically coupled to the length of fiber (12) so that the illumination enters the fiber along that length. The optical fiber (12) also carries light representing a bitstream of data. At the optical fiber, the illumination from the spatial light modulator interacts with the illumination of the optical bitstream. A detector (14) is optically coupled to the same length of fiber (12) and detects the resulting optical response to determine if a correlation exists.

Abstract: A method and structure for controlling the surface properties in the dielectric layers in a thin film component can be provided for improving the trimming process of thin film element. A metal fill is configured with a uniform fill pattern beneath an array of thin film resistors, and can comprise a plurality of smaller features or peaks providing a finer fill pattern that improves the control of the topology of the dielectric layers. The fill pattern can be configured in various manners, such as fill patterns parallel to the thin film resistor, fill patterns perpendicular to the thin film resistor, or fill patterns comprising a checkerboard-like configuration.

Abstract: A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.

Abstract: According to the electrical modeling system and method provided by the present invention, the electronic structure to be modeled is segmented into an ordered sequence of segments, each segment is electrically analyzed individually, and the resulting data is collated, or integrated back again whereby the model output is preferably created in a format generally suitable for electrical models of integrated circuits. Examples of electronic structures which can be modeled by the system and method of the invention include leadframes, packages, complete devices, and electronic devices assembled on motherboards.

Abstract: A sense amplifier that is capable of sensing small differential voltage between two inputs with full voltage range includes a first inverter 305 and 306; a second inverter 307 and 308 cross coupled with the first inverter; a first transmission gate 301 coupled between a reference node REF and an input of the first inverter; a second transmission gate 302 coupled between a data node RD and an input of the second inverter; a pull-up enable switch 303 coupled between a high side voltage source node VDD, and the first and second inverters; and a pull-down enable switch 304 coupled between a low side voltage source node, and the first and second inverters.