Abstract: A method of improving shallow trench isolation (STI) gap fill and moat nitride pull back is provided by after the steps of growing a pad oxide, depositing a nitride layer on the pad oxide and the steps of moat patterning, moat etching and moat clean, the steps of growing thermal oxide, deglazing a part of a part of the moat nitride; depositing a thin nitride liner, etching the nitride to form a thin side wall nitride in the STI trench; and performing an oxide Hydroflouric (HF) acid deglazing before STI liner oxidating and depositing oxide to fill the trench.

Abstract: A display system (200) in which light from source (202) is focused onto a spinning color wheel (204). The spinning color wheel (204) spins at a constant rate and creates of beam of light that changes from one primary color to the next in rapid sequence. The primary colored beam of light impinges a spatial light modulator (206), which is often a DMD or LCD. A controller (208) receives an input video signal and determines the native frame rate of the image source. The controller (208) sends image data to the spatial light modulator (206) in synchronization with the color wheel (204)—image data representing the red portions of the image is sent during the period in which the red color filter is passing through the beam of light—at the native frame rate of the image source. The modulated light is focused onto an image plane (210) by projection lens (212) to form an image. The eye of the viewer integrates the sequential primary color images giving the perception of a single full-color image.

Abstract: A circuit relates to phase and frequency-locked loop circuits (PLL and FLL circuits) with a controllable tracking oscillator whose signal phase relationship or frequency, respectively, is influenced by an external parameter, a reference oscillator, as well as a phase or frequency comparator, the output signal of which is used to control the tracking oscillator in such a way that any phase or frequency errors are reduced. A circuit provides for an element for the measurement of the external parameter (such as a microprocessor) which is capable of receiving a signal representing the output signal of the phase or frequency comparator, and convert it into a measurement value that represents the present value of the external parameter. This external parameter can, for example, represent the ambient temperature or the supply voltage of the tracking oscillator.

Abstract: A method and apparatus for modeling a neural synapse function in analog hardware whereby the multiplication function inherent to the operation of a neural synapse is computed by applying a voltage on the gate-source terminals and an independent voltage on drain-source terminals of a MOSFET further using the resultant drain current of the latter device in non-saturation mode as function implementing a computation essentially close to multiplication function between the aforesaid voltages. Analog circuit is provided, capable of generating an output current signal which is proportional in magnitude, within a certain range, to a function computing essentially a sum of weighted input signals—products of corresponding pair of current input signal, and voltage control signal applied to a plurality of inputs thus capable of constructing an artificial neuron model.

Abstract: An integrated circuit (42) provides drive signals to a piezo element (48) of a milli-actuator device (20) in a mass data storage device (10). The integrated circuit (42) includes a circuit (61) for selectively operating the integrated circuit (42) in either a voltage or a charge mode of operation. A first amplifier circuit (44) can be compensated for a variable number of piezo elements in the charge mode of operation by adjustable output impedance adjusting elements (124, 126, 138-141) that are switchably connectable into the amplifier circuit (44).

Abstract: A cache architecture (16) for use in a processing includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) defines a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core, hit/miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20).

Abstract: A flexible carrier tape system, suitable for housing components and for winding on a reel in high density, is disclosed, comprising an elongated base strip having a plurality of longitudinally spaced cavities with side walls having a step-like groove near the surface around the cavity, comprising further an elongated cover strip having a width matching the width of the cavity including the widths of the grooves, the cover strip sealed onto the base strip so that the cover strip rests on the step-like grooves. In one embodiment, the sealed cover strip forms a substantially uniform plane with the upper surface of the base strip. The thickness consumed by each tape winding becomes a minimum so that a high density of components can be stored and transported.

Abstract: A processor is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A coefficient data pointer is provided for accessing coefficient data for use in a multiply-accumulate (MAC) unit. Monitoring circuitry determines when the coefficient data pointer is modified (step 1104). When an instruction is executed (step 1102) that requires a coefficient datum from memory in accordance with the coefficient data pointer, a memory access is inhibited (step 1108) if the coefficient data pointer has not been modified since the last time a memory fetch was made in accordance with the coefficient data pointer and the previously fetched coefficient datum is reused.

Abstract: A decoder for code excited LP encoded frames with both adaptive and fixed codebooks; erased frame concealment uses muted repetitive excitation, threshold-adapted bandwidth expanded repetitive synthesis filter, and jittered repetitive pitch lag.

Abstract: A gain boost circuit is provided in a differential amplifier including differentially connected first and second input transistors the drains of which are coupled to sources of first and second cascode transistors. A third cascode transistor has a source coupled to a drain of the first cascode transistor and a drain coupled to a bias current source. A gain boost amplifier has an output coupled to the gate of the third cascode transistor, a first input coupled to the drain of the first cascode transistor, and a second input coupled to the drain of the second cascode transistor.

Abstract: A circuit 10 is provided that comprises a source resistance transistor 12 connected to a common node 14. A word line driver circuit 18 receives current if it is the word line driver selected from the VDD supply voltage through the source resistance transistor 12. The gate of source resistance transistor 12 is connected to a bond pad 22 which can be alternatively connected to the VDD supply voltage through a bond pad 24 or to ground potential through a bond pad 26. The effective threshold voltage of a transistor 18 within driver 16 can be adjusted depending upon how the gate of transistor 12 is connected. In this manner, a circuit can be adjusted to compensate for process variation or to be more optimum for a selected application by adjustment of the effective threshold voltage of selected transistors.

Abstract: A Sigma-Delta Analog-to-Digital Converter (ADC) having efficient dithering that removes the idle channel tones of the sigma-delta converter is disclosed herein. These idle channel tones are reduced or removed by stretching the threshold window of the multi-level quantizer. A dithering sequence is added by stretching the thresholds window randomly. The randomly stretched window destructs the periodicity of sigma-delta ADC modulator's output sequence and, thus, removes the idle channel tones. Compared with conventional methods, the Sigma-Delta ADC in accordance with the present invention has less SNR penalty and is simple to implement. Moreover, the sigma-delta ADC in accordance with the present invention has a higher allowed input dynamic range and higher signal-to-noise-plus-distortion-ratio (SNDR) than conventional modulator dithering schemes.

Abstract: A projection lens that uses a TIR surface as both an angular filter and fold mirror. A first lens element 602 is placed very close to the TIR prism assembly 604. Because the lens is so close, it gathers both off state and state light from the modulator. Off state light from the DMD follows path 606 while on state light follows path 608. A total internal reflection surface 610 receives both the on state and the off state light. Because the off state light strikes the TIR surface at an angle less than the Brewster's angle, the off state light passes through the TIR prism and is removed from the projection path. The on state light strikes the TIR surface at an angle greater than Brewster's angle and is reflected by the TIR surface through the remaining projection lens components.

Abstract: An output circuit for improved ESD protection (FIG. 2) comprising a pMOS pull-up output transistor connected between a signal (I/O) pad 220 and Vdd power supply 240, the pull-up transistor located in a n-well 203 and having at least one gate 210, the gate connected to internal circuitry 230. A dummy pMOS transistor connected in parallel with the pull-up transistor, the dummy transistor also located in the n-well 203, whereby both the pull-up transistor and the dummy transistor participate in protection against an ESD event. The dummy transistor having at least one gate 251, this gate connected through a resistor 260 to the Vdd power supply 240. The n-well 203 connected to the Vdd power supply 240.

Abstract: A multiplexer containing multiple cells sharing a common output line. The cells select one of multiple input bits. The output line is first charged to a first logical value (e.g., 0), and one of the cells drives the output line to a second logical value (1) if the corresponding input bit does not equal the first logical value. The remaining cells may not affect the output line. Due to such an implementation, the number of transistors may be reduced.

Abstract: A Virtual Frame Buffer control system and method for cascading several display controllers on one LCD panel. The Virtual Frame Buffer is composed of all the memory in all the controller/memory/source driver chips (in a tiled pattern) for the associated processor to read and write in. The control system also includes hardware clipping controls in each of the controller/memory/source driver chips. The Virtual Frame Buffer and hardware clipping control placement substantially reduces programming problems associated with prior art solutions for cascading LCD controller/memory/source driver devices.

Abstract: A tool and method is described to decide partial wafer sizes to process multiple random sizes of wafers in pick and place equipment for wafermap operation. The tool identifies the wafer and gets wafermap data. The position of one or more cutters is displayed. The position of the cutters relative to the wafer is displayed. The tool generates and displaying the results of the type of dies in each partial that would result from a cut according to said displayed position of the cutters.

Abstract: A transconductance-setting circuit (10, 20) and method. The circuit (10, 20) includes a first transconductor (14) coupled to a reference voltage (Vref) adapted to produce a current output (Ibias). A reference current source (Iref) is coupled to the first, transconductor (14), and a feedback loop (16) is coupled to the first transconductor (14) and the reference current source (Iref). The feedback loop (16) is adapted to reduce error in the current output (2i) and set the transconductance gm of the first transconductor (14) to a value proportional to the ratio of the reference current and the reference voltage. An auxiliary transconductor (22) is coupleable to the first transconductor (14), and control circuitry (30, 40) is adapted to control the coupling of the auxiliary transconductor (22) to the first transconductor (14) based on the current output (2i).

Abstract: A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus has changed logic state. If a bit has changed state, the comparison logic asserts an enable signal which causes the clock logic to clock the register. Accordingly, data from the bus is not clocked through the register unless the data has actually changed state and the comparison logic itself determines whether different data is present on the bus.

Abstract: A 64-state binary convolutional code is disclosed for a high-speed physical layer (PHY) of a communication network. The proposed code provides improved performance in terms of signal to noise ratio (SNR) and multi-path rejection than previously known codes. The proposed system, which includes binary convolutional codes with scrambling in a packet-based system, is referred to herein as “packet binary convolutional coding” (PBCC). The substantial increase in performance that may be achieved by PBCC makes it an ideal solution for high performance forward error correction (FEC) in a high-speed PHY.