Abstract: An optic connector jack is provided with a punch-down fiber optic cable termination. The jack is made up of a housing with a connector mating interface, for connection to a plug connector, and a cradle for receiving a fiber optic cable. The cradle has at least one U-shaped punch-down blade for securing each fiber optic cable with respect to the housing. A crimping plate overlies the cradle and mates to the housing for securing each fiber optic cable in the cradle. The U-shaped punch-down blade has an open top portion, a closed bottom portion, and an inside diameter about equal to a fiber optic cable diameter. The U-shaped punch-down blade has an interior blade edge, the interior blade edge securing a fiber optic cable by slicing into at least a part of the fiber optic cable circumference. In one aspect, the jack includes a lens for each fiber optic cable.

Abstract: A fiber optic cable is provided with a cable section including at least one length of fiber optic line having a first end and a second end. A first and second plug each have a mechanical body shaped to selectively engage and disengage a jack housing. Each plug has a microlens with a planar surface to engage the fiber optic line end and a convex surface to transceive light in a first collimated beam with a jack optical interface. The fiber optic cable ends are formed in a focal plane of a corresponding plug microlens.

Abstract: A system and method are provided for transporting Plesiochronous Digital Hierarchy (PDH) tributaries. The method accepts a plurality of PDH tributaries; generates a serial data stream of interleaved PDH tributaries; generates a serial control stream of signals for recovering the PDH tributaries; and, generates a clock signal for timing the data and control streams. The serial data stream of interleaved PDH tributaries is loaded into the payload of a data frame structure. Likewise, the serial control stream is loaded into the payload of a control frame structure. The data bytes of the serial data stream and the control bytes of the serial control stream are both transmitted at the same data rate. That is, there is a control byte generated for each data byte. Thus, the control bytes in the control frame structure are aligned with corresponding data bytes in the data frame structure.

Abstract: A system and method are provided for determining a frequency ratio in a phase-locked loop (PLL) circuit feedback path. The method accepts a reference signal having a predetermined first frequency and a PLL output signal having a non-predetermined second frequency. The reference signal cycles are counted, creating a first binary count. Likewise, the PLL output signal cycles are counted, creating a second binary count. The second binary count is sampled at an interval responsive to the first binary count, and a right-shifted second binary count is supplied as a ratio of the second frequency divided by the first frequency. More explicitly, the sampling is performed when a first binary count sampling threshold of 2n first frequency cycles is reached. Then, the radix point in the second binary count is shifted n number of radix places to the left.

Abstract: An optical-electrical processing jack is provided. The optical processing jack includes an optical jack with a jack housing having walls and an orifice for mechanically and optically engaging an optical plug housing. A signal bridge, with a bridge element, transceives optical signals between the optical plug and a backcap processing module. The backcap processing module includes a backcap housing with walls, attached to the jack housing and an optical element. The optical element has an optical interface to transceive an optical signal via the signal bridge, and convert optical signals and electrical signals transceived via an electrical interface. In one aspect, the bridge element is a lens with a first surface to transceive an optical signal with the optical plug, and a second surface to transceive the optical signal with the optical element optical interface. For example, the optical element is a photodiode or laser source.

Abstract: Fiber optic cable jacks and plugs are provided. In one aspect, a cable is made from at least one length of fiber optic line having a first end and a second end. A first plug includes a one-piece mechanical body with a cable interface to engage the fiber optic line first end, and a microlens to transceive light with the cable interface. The first plug is shaped to engage a first jack housing. A second plug includes a one-piece mechanical body with a cable interface to engage the fiber optic line second end, and a microlens to transceive light with the cable interface. The second plug is shaped to engage a second jack housing. The mechanical bodies have inner walls that form an air gap cavity interposed between the microlens convex surface and an engaging jack optical interface.

Abstract: A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired.

Abstract: A reflector tool and a method are provided for three-dimensional integrated circuit (IC) failure analysis. An IC (die) has top and bottom surfaces, a perimeter, and a first side. The IC is electrically connected to a current sensing amplifier. The first side of the IC is scanned in the X plane with an infrared laser beam while changes in IC current flow are sensed. The sensed current changes are cross-referenced to the location of the infrared laser beam in the X plane. In one aspect, a plurality of scans are performed on the first side in the X plane, with at a corresponding plurality of steps in the Y plane, so that current changes can be cross-referenced to locations in the X and Y planes. Using this 2-D analysis through the IC side, a human operator or software program can determine defects in the IC.

Abstract: A successive time-to-digital converter (STDC) method is provided for supplying a digital word representing the ratio between a phase-locked loop PLL frequency synthesizer signal and a reference clock. The number of frequency synthesizer clock cycles per reference clock cycle is counted. A first difference is measured between a reference clock period and a corresponding frequency synthesizer clock period. In response to the first measurement, a second difference is measured between a delayed reference clock period and the corresponding frequency synthesizer clock period, where the second difference is less than the first difference. A third difference is measured as a time duration between the delayed reference clock period and the corresponding delayed frequency synthesizer clock period. The first and third difference measurements and the count of the number of frequency synthesizer clock cycles per reference clock cycle are used to calculate a digital error signal supplied to the frequency synthesizer.

Abstract: A socketless integrated circuit (IC) contact connector is provided with an electrically conductive support post. An electrically conductive spring has a first end connected to the post, and a second end. An electrically conductive first wire has a first end connected to the spring second end, and a second end. An electrically conductive loop with a loop neck is connected to the first wire second end. Typically, the loop is formed in the first wire second end. The spring and loop work in cooperation to engage an IC contact.

Abstract: System and methods are provided for optical-magnetic Kerr effect signal analysis. In one aspect, a test fixture is supplied having parallel conductive lines, with an input of a first line adjacent a resistively loaded output of a second line and a resistively loaded output of the first line adjacent an input of the second line. An optically transparent test region is interposed between the conductive lines, and a metallic reflector underlies the test region. A signal reference is supplied to the input of the first line and a signal under test is supplied to the input of the second line. A light beam having a first angle of polarization is focused through the test region onto the reflector. The intensity of the reflected light is measured and the similarity between the signal under test and the reference signal can be determined in response to the measured light intensity.

Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: A germanium (Ge) photodiode array on a glass substrate is provided with a corresponding fabrication method. A Ge substrate is provided that is either not doped or lightly doped with a first dopant. The first dopant can be either an n or p type dopant. A first surface of the Ge substrate is moderately doped with the first dopant and bonded to a glass substrate top surface. Then, a first region of a Ge substrate second surface is heavily doped with the first dopant. A second region of the Ge substrate second surface is heavily doped with a second dopant, having the opposite electron affinity than the first dopant, forming a pn junction. An interlevel dielectric (ILD) layer is formed overlying the Ge substrate second surface and contact holes are etched in the ILD layer overlying the first and second regions of the Ge substrate second surface. The contact holes are filled with metal and metal pads are formed overlying the contact holes.

Abstract: A system and method are provided for efficiently switching a loop bandwidth using stored values in a digital filter of a phase-locked loop system. In a first timeslice, an input signal is digitally filtered using base coefficients multiplied by stored filter output and input values from previous timeslices. The filter output value is used to acquire the input signal frequency in a first bandwidth. In response to changes in the input signal frequency, the input signal is digitally filtered in a predetermined number of first intermediate period timeslices using transient coefficients multiplied by stored filter output and input values from previous timeslices. As a result, the first filter output value is maintained within a predetermined range. In a second timeslice, the input signal is digitally filtered using base coefficients multiplied by stored filter output and input values from previous timeslices to acquire the input signal frequency in a second bandwidth.

Abstract: One aspect of the invention is a method for identifying at least one property of data. An example of the method includes receiving data, and making assessments regarding the data. The method also includes applying at least one behavioral operator, and outputting results. The method further comprises receiving feedback concerning system performance. Additionally, the method includes adjusting at least one parameter based on the feedback received concerning system performance, wherein the at least one parameter is a parameter of a machine learning method.

Abstract: A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency.

Abstract: One aspect of the invention is a method for assigning categorical data to a plurality of clusters. The method may include identifying a plurality of categories associated with the data. The method also may include, for each category in the plurality of categories, identifying at least one element associated with the category. The method also may include specifying a number of clusters to which the data may be assigned. The method additionally may include assigning at least some of the data, wherein each assigned datum is assigned to a respective one of the clusters. The method further may include, for at least one of the clusters, determining, for at least one category, the frequency in data assigned to the cluster of at least one element associated with the category. Further, the invention may provide for detecting outliers, anomalies, and exemplars in the categorical data.

Abstract: A fiber optical connector microlens is provided with a self-aligning optical fiber cavity. The microlens includes a convex first lens surface and a second lens surface. A fiber alignment cavity is integrally formed with the second lens surface to accept an optical fiber core. A lens body is interposed between the first and second lens surfaces, having a cross-sectional area with a lens center axis, and the fiber alignment cavity is aligned with the lens center axis. In a first aspect, the fiber alignment cavity penetrates the lens second surface. In a second aspect, an integrally formed cradle with a cradle surface extends from the lens second surface, and a channel is formed in the cradle surface, with a center axis aligned with the lens center axis. The fiber alignment cavity includes a bridge covering a portion of the channel.

Abstract: A system and method are provided for channel equalization using a combination of frequency and phase compensation. The method receives a serial data stream input, and parallel processes the data stream input through a first and second path. The first path has a first frequency response, and the second path has a second frequency response, higher than the first frequency response. Signals are combined from the first and second paths, creating a frequency compensated signal. Then, the frequency compensated signal is parallel processed through a third path having a first time delay, and a fourth path having a fourth time delay, greater than the third time delay. The signals from the third and fourth paths are combined, created a phase compensated signal. In one aspect, the phase compensated signal is amplified, creating a voltage limited output signal.

Abstract: A system and method are provided for detecting the frequency acquisition of a synthesized signal in a non-synchronous communications receiver. The method accepts a non-synchronous communication signal having an input data signaling frequency, and compares the input data signaling frequency to a synthesized signal frequency. In response to the comparing, a difference signal pulse is generated. More explicitly, the difference signal is generated at a rate responsive to the difference between the input data signaling frequency and the synthesized signal frequency. The method counts synthesized signal pulses occurring simultaneously with the difference signal pulse. If the counted synthesized signal pulses exceed a threshold (before the disappearance of the difference signal pulse), it is determined that the input data signaling frequency is about equal to the synthesized signal frequency, and a lock signal is generated.