Abstract: A heat-insulating walling includes an outer casing that is vacuum-tight as far as possible and with an inner lining being vacuum-tight as far as possible and spaced from the latter. The inner lining and the outer casing are connected to one another, vacuum-tight, by a connecting profile. The connecting profile has an at least approximately U-shaped cross section and has a diaphragm-like base. The connecting profile, together with the outer casing and the inner lining, surrounds an interspace filled with heat-insulation material. The U-shaped connecting profile can engage with its legs over the outer casing and the inner lining. The legs can be vacuum-tightly secured to the inner lining and the outer casing.

Abstract: The wearing part, such as a cutting insert, is made from hard metal or cermet. A hard-material coating is applied on the base material. The coating includes a single-layer or multilayer mixed-oxide coat, predominantly comprising Al2O3, in which defined proportions of titanium oxide and boron oxide are dissolved or homogeneously distributed extremely finely. The wearing part is distinguished by a high wear resistance, which improves the service life, and a fine-grained structure and uniformity of the coat and by a highly economic application of the coat.

Abstract: The circuit configuration converts an input signal into a binary output signal. The circuit has at least one comparator, at least one demodulation unit, and at least one clock unit. The demodulation unit has two or more capacitors and two or more switches controlled by the clock unit. The switches connect the capacitors of the demodulation unit to the comparator, and the comparator compares an input signal demodulated by the demodulation unit with a reference value and forms from that the binary output signal.

Abstract: An integrated circuit includes a self-test device which is provided for executing a self-test of the integrated circuit and which has a control output. A program memory is connected to the self-test device for storing at least one test program supplied from outside the integrated circuit. The test program is run by the self-test device during execution of a self-test. The self-test device controls loading of a respective test program to be run into the program memory from outside the integrated circuit through the control output thereof.

Abstract: A semiconductor memory has a data signal path and a control device in order to supply functional elements of the data signal path with control signals. Programmable delays are connected into the signal lines providing the control signals, so that the time relationships between the control signals can be set reversibly via a soft set register or irreversibly via fuses. This enables simple adaptation of the internal control signal timing to fluctuations in the fabrication process or after conversion of the configuration to a new fabrication process.

Abstract: The apparatus and the method serve to adjust an air flow, which varies sheet transport, in a printing machine. The apparatus has an air flow regulating device. An operating parameter of the air flow that varies the sheet transport serves as a controlled variable. The controlled variable may be the air flow rate or the static air pressure of the air flow.

Abstract: The invention relates to a method for protecting data during a self-test of a microcontrollers, in which all of the circuit elements within the microcontroller can be tested, where the course of the self-test cannot be altered via the external pins, and no intermediate results are passed to the outside via the pins. The invention also relates to an configuration in the form of an integrated circuit which can be used to implement the method, and to correspondingly equipped microcontrollers.

Abstract: A connection for a feed line at a feed pump pumping fuel out of a fuel tank, includes a nonreturn valve disposed in a horizontal portion of a connection stub. The connection stub is held on the feed pump by a latching device. The connection permits a particularly compact configuration of the feed pump.

Abstract: A method for controlling the information exchange between at least one central computer and a subscriber via a control system. Following a request from the subscriber, the control system receives the data relevant to the subscriber from the central computer in a first control phase. In a second control phase, information transmitted from the subscriber is processed and transmitted to the central computer. The first and the second control phases are defined by a single control program.

Abstract: An apparatus for measuring angle-dependent diffraction effects includes a coherent radiation source, a device for deflecting the coherent radiation in different directions, a spherical or aspherical mirror or mirror segments configured to correspond to a spherical or aspherical mirror, and a detector unit for measuring the intensity of the radiation diffracted at a specimen. The radiation deflected in different directions is reflected by the mirror configuration in such a way that the coherent beam is deflected onto the specimen with different angles of incidence in a temporally successively sequential manner. For this purpose, the angle of incidence of the measuring beam is altered continuously or in small steps. The intensities of the direct reflection (zero-order diffraction) and also of the higher orders of diffraction that may occur are measured. This evaluation allows conclusions to be drawn regarding the form and material of the periodic structures examined.

Abstract: A method for the fabrication of a gate stack, in particular in very large scale integrated semiconductor memories, uses a combination of a damascene process and a CMP process to produce a gate stack which includes a polysilicon section, a silicide section and a covering-layer section thereabove. The gate stack can be fabricated by using conventional materials, has a very low sheet resistance of <1 ohm/unit area and may carry self-aligning contact sections.

Abstract: An integrated memory including memory cells in a plurality of memory cell blocks, each memory cell block being assigned at least one dedicated data line and a register circuit that can be written from outside the memory. At the start of a test operation, data is stored in the register circuits as reference data. During an access cycle, in each case in each of the memory cell blocks, a respective memory cell or a group of memory cells is selected, a respective read amplifier is activated and, in each of the register circuits, a comparison between the data read out and the reference data is carried out. As a result, the time required for the test operation of the memory is made comparatively low.

Abstract: A circuit has a control signal input, a control signal output, a delay element for generating a delay duration, and a control logic circuit. The latter controls the delay element and switches a change in the state at the control signal input to the control signal output in a manner delayed by the delay element, if a minimum time interval between state changes at the control signal input is undershot. The circuit is employed in DRAMs for controlling the active times of the voltage generators present in DRAMs.

Abstract: A trench MOS-transistor includes a body region strengthened by an implantation area that faces the drain region to increase the avalanche resistance.

Abstract: In a method for manufacturing an integrated memory circuit, a semiconductor substrate having a front side and a rear side is provided first. The semiconductor substrate is processed on the front side and on the rear side to produce memory cells on the front side and memory cells on the rear side of the semiconductor substrate. Finally, defective memory cells on one side of the semiconductor substrate are replaced by operational memory cells on the other side of the semiconductor substrate by connecting the operational memory cells of the one side of the semiconductor substrate to an input/output circuit of the memory circuit. By loading the semiconductor substrate on both sides, it is possible to either considerably reduce the rejection rate of memory chips or to strongly reduce the chip area of a memory chip or to increase the number of memory cells per specified chip area.

Abstract: A method for resynchronizing a clock signal, includes the steps of defining a presettable clock signal, dividing a first clock signal having a first frequency with a programmable digital frequency divider to produce a second clock signal having a second frequency, measuring the second clock signal with a digital control circuit, and programming a programmable digital frequency divider with the digital control circuit, such that the second clock signal corresponds to the presettable clock signal.

Abstract: A method of aligning sheets prior to transferring them to a sheet-processing machine includes feeding a respective sheet, by a first sheet edge thereof, against a stop; gripping the sheet by at least one sheet holder, and displacing the sheet holder at least approximately transversely to the stop in a direction towards a first control region; and onwardly moving the sheet holder, while the sheet is held thereby, over a given first distance, after a second sheet edge has reached the first control region; and a device for performing the method.

Abstract: A water lance blower for cleaning heat installations includes a water lance moveably mounted with a mouth thereof at or in a hatch. The water lance can blow a jet of water through the heating installation, through which flames and/or flue gases are guided, to wall regions accessible from the hatch, during operation. The water lance is provided with at least one sensor for detecting at least one predeterminable measurement value for monitoring the quality of the water jet. A method for operating the water lance blower includes detecting and evaluating at least one parameter characteristic of the quality of the water jet as a measurement value during operation of the water lance blower. The method permits an evaluation of the cleaning effect of the water lance blower during operation and, if required, influencing of the same.

Abstract: A vertical non-volatile semiconductor memory cell and an associated manufacturing method in which a trench extension, which has a third dielectric layer and a filler material, is formed underneath the vertical semiconductor memory cell with its first dielectric layer, its charge storage layer, its second dielectric layer and its control layer. In this way, the data retention properties and a coupling factor are improved.

Abstract: The invention relates to a semiconductor module having a plurality of signal paths for carrying external signals that each contain a setup and hold circuit on the basis of a latch circuit with a full latch and a logic circuit. The latch circuit contains at a beginning of the signal path upstream of the logic circuit a hold latch. The hold latch responds to the leading edge of a fast clock signal derived from the clock signal of the external signal, for the early latching of the external signal and for the decoupling of the hold time from the setup time. The full latch is disposed downstream of the logic circuit for the final latching of the external signal or of a signal derived from the latter.