Abstract: The present invention relates to a memory cell arrangement and a fabrication method for this memory cell arrangement. In this case, the memory cells (15a, 15b, 15c) arranged regularly on a semiconductor wafer each have a trench capacitor (20a, 20b, 20c) formed in the semiconductor substrate (10), and a selection transistor (30a, 30b, 30c) formed above the trench capacitor (20a, 20b, 20c), and also a self-aligned selection transistor (30a, 30b)—memory trench contact (40a, 40b)—trench insulation (52) arrangement.

Abstract: A method for releasable contact-connection of a plurality of integrated semiconductor modules on a wafer, each of which having a plurality of interconnected supply voltage terminals, includes the steps of providing a contacting card for applying external electrical signals to the semiconductor modules with contact elements for releasable electrical connection to terminal pads of the semiconductor modules, aligning the contacting card with the wafer, producing a releasable contact between terminal pads of the plurality of semiconductor modules and the contact elements of the contacting card, checking the contact quality for each of the semiconductor modules by applying a voltage to at least one of the supply voltage terminals of the semiconductor module through the contacting card, measuring the voltage present at a further one of the supply voltage terminals through the contacting card, and using the measurement result to assess whether or not the semiconductor module has correct contact.

Abstract: The present invention is based on an use of the already existing actuator bottom as a deformation element for a direct measurement of braking force, and on its geometric configuration in order to measure a force in a way which is largely independent of temperature and free of hysteresis. Accordingly, a force sensor is integrated into an actuator for generally or transmitting a force in the force flux. The actuator bottom is transverse to the force flux.

Abstract: An integrated magnetoresistive semiconductor memory system, in which n memory cells that contain two magnetic layers each separated by a thin dielectric barrier, and associated word lines and bit lines that cross one another are vertically stacked in n layers. The system further contains a decoding circuit for selecting one of the n memory layers. The decoding circuit, on both ends of a word line or a bit line, is provided with one configuration each that contains n layer selecting transistors for selecting one of the n memory layers, and with a line selection transistor for selecting the respective horizontal word line or bit line on which a voltage is to be impressed.

Abstract: A method is provided for fabricating a useful layer containing at least one semiconductor layer, in which the useful layer is separated from a carrier. In this case, the useful layer is applied to the carrier and an auxiliary carrier is applied to that side of the useful layer that is remote from the carrier by a connecting layer at a joining temperature. Afterward, the carrier is stripped away at a temperature that is greater than or equal to the joining temperature and is less than the melting point of the connecting layer. At least a part of the useful layer together with the auxiliary carrier is removed from the carrier.

Abstract: A device for locking a first housing part and a second housing part to one another includes a locking element inserted into an opening in the first housing part. The locking element is configured to be movable between a locking position and an unlocking position. The locking element, if in the locking position, connects the first housing part to the second housing part in a form-locking and/or a force-locking manner. The locking element, if in the unlocking position, releases a connection between the first housing part and the second housing part. A blocking element is connected to the locking element for blocking the locking element from being adjusted at least in the locking position. A multi-part housing is also provided.

Abstract: The invention relates to a process for producing amplified negative resist structures in which, following exposure and contrasting of the resist in a developing step, the resist structure is simultaneously developed and silylated. This substantially simplifies the production of amplified resist structures.

Abstract: Data are transmitted in a telecommunications system from a first private branch exchange to a second private branch exchange. The data include wanted data, for example voice information, and control data for controlling a private branch exchange. The control data include information about service attributes of the private branch exchanges. The data are interchanged in the form of data packets via a computer network.

Abstract: A semiconductor memory having memory cells, each memory cell includes a selection transistor and a trench capacitor. The selection transistor is formed in the form of a vertical transistor. In such a case, two word lines are separated only by a connecting channel that enables an electrically conductive connection between a trench filling of the trench capacitor and a bit line.

Abstract: A digital GMSK filter for use for frequency modulation of a carrier signal in a GMSK transmission system is described. The GMSK filter uses a large number of individual current sources, whose current values are individually weighted. The current sources are driven via a control logic module using a shift register with a thermometer code, such that this results in a total current with a Gaussian characteristic, which is converted across a resistor to a voltage and drives a voltage controlled oscillator (VCO). The filter provides exact implementation of the sample values, virtually without any quantization error, and requires only a small chip area for its implementation.

Abstract: A transistor configuration for a bandgap circuit is configured in the form of an npn transistor. An insulated p-type well, which is surrounded by a buried n-type well, is used as a base terminal. The n-type well constitutes the emitter terminal. A negatively doped region, which acts as a collector terminal, is formed in the p-type well. The structure that is used exists in DRAM processes, and it can therefore be used to form an npn transistor as a footprint diode in bandgap circuits.

Abstract: A process for the deposition of thin layers by chemical vapor deposition includes adding an effective amount of nitroxyl radicals of the formula to a gas stream including the materials to be deposited. In this formula, R1 and R2 are identical or different alkyl, alkenyl, alkynyl, acyl, or aryl radicals, with or without heteroatoms. R1 and R2 can also together form a structure —CR3R4—CR5R6—CR7R8—CR9R10—CR11R12—, where R3, R4, R5, R6, R7, R8, R9, R10, R11, R12 are again identical or different alkyl, alkenyl, alkynyl, acyl, or aryl radicals, with or without heteroatoms.

Abstract: A wafer holder has a set of minimum contact wafer support members predefining support member contacting portions on a planar wafer surface of a wafer. The wafer chuck has a wafer support region for contacting the planar wafer surface. The wafer support region of the chuck includes recesses configured at predefined positions corresponding to support member contacting portions of the lower wafer surface. The wafer handling system further includes a wafer transport device including a rotational position adjusting device for adjusting the rotational position of a wafer that is transported between the wafer holder and the wafer chuck. Thereby, elevations on the lower wafer surface, like scratches or deposited material which are produced by the contact between the support members and the wafer, are encapsulated by the recesses of the wafer chuck. A method for moving a wafer between a wafer holder and a wafer chuck is also provided.

Abstract: A method and an apparatus for exposing photosensitive material, in particular for exposing a printing form, in which a surface to be exposed of the photosensitive material is scanned by at least one light beam. The light beam is emitted by a light source and, before striking the photosensitive material, is optionally modulated, interrupted and/or deflected. An exposure head is provided and moved at a constant distance from the surface in relation to the latter and to the light source in order to scan the surface of the photosensitive material with the light beam. In order to make the exposure head as light as possible, after the light beam has emerged from the light source substantially parallel to the surface to be exposed, the light beam is deflected through a gaseous medium toward the exposure head and there should be reflected onto the surface.

Abstract: A DRAM memory cell having an isolation transistor formed from a bipolar transistor.

Abstract: An integrated dynamic memory contains a control circuit for controlling a refresh mode in which the memory cells undergo refreshing of their contents. A controllable frequency generator serves for setting a refresh frequency. A temperature sensor circuit detects a temperature of the memory and outputs a first reference value, and an externally writable circuit is provided for outputting a second reference value. The temperature sensor circuit and the externally writable circuit are alternatively connectible to the control input of the frequency generator for setting the refresh frequency. If the externally writable circuit has been written, the second reference value, which corresponds to a temperature, is fed to the frequency generator; otherwise, the first reference value is supplied. In this manner, users of the memory that are unable to measure temperature can expediently optimize the power consumption that is necessary for standby mode and reduce it at low temperatures.

Abstract: A circuit configuration for driving a programmable link, for example a fuse, is specified, having a drive circuit for driving the fuse in a manner dependent on a signal present at the data input, and also a volatile memory, whose output is preferably directly connected to the data input of the drive circuit. A circuit configuration for particularly fast and simple programming of fuses, in particular electrically programmable fuses, is thereby specified.