Abstract: A semiconductor static memory cell with two cross-coupled inverters and two transmission gates for coupling two bit lines uses all minimum size (gate length and gate width) MOSFETs to achieve minimum area. This minimum dimension is rendered possible by using a higher threshold voltage for the transmission gate MOSFET than the threshold voltage of pull-down MOSFET of the inverter. Different threshold voltages are obtained with selective ion implantation, different gate oxide thicknesses and/or different gate doping.

Abstract: The surface of an integrated circuit, which uses reactive ion etching to pattern metal interconnection, is protected with two insulating layers on the surface. The first layer is a conventional silicon dioxide. The second layer is a photosensitive polymer which is the same as the material used for subsequent metalization of interconnection using the reactive ion etching technique. When the second layer is used, the reactive ion etching cannot attack the silicon dioxide.

Abstract: The electrode of a storage capacitor of a DRAM cell lies diagonally along the memory cell. The diagonal layout makes the length of the capacitor longer than either the x-dimension or the y-dimension of the memory cell, thus increasing the storage capacitance.

Abstract: In a "flat cell" read-only memory with a matrix of memory cells, each memory cell is a MOSFET of either a low threshold voltage, which can be turned on when accessed, or a high threshold voltage which cannot be turned on when accessed. Each memory cell is connected between two adjacent columns of local bit lines. These local bit lines are alternately connected to a upper bank selection switch which is connected to a main bit line, and a lower bank selection switch, which is connected to a main virtual ground line. Since these local bit lines are fabricated with diffusion layers which are resistive, the path length, hence the resistance, to access any memory cell in the matrix from the main bit line to the main virtual ground is made the same by this alternate, interdigital local bit line layout. Thus, the access time is made uniform.The layouts of two adjacent banks are mirrored, so that the bank selection switches of two adjacent banks can share a common selection line.

Abstract: An image sensor chip is mounted on a printed wiring frame over a substrate, which is plated with a spider web of plated conductors connecting the IC through via holes to the bottom of the substrate as output terminals. After wiring bonding the IC to the plated conductor, the package is sealed. A wall is erected around the image sensor chip and is covered with a transparent glass. A lens may be placed in the middle of the cover for focusing. The structure is amenable to mass production. A large number of printed wiring frames are arranged as a matrix on a common substrate. The frames are sealed column by column or sealed all at once. After sealing, the common substrate are diced into individual packages. The image sensor package may mounted with integrated circuit chips as peripheral circuits. The image sensor chips may be sealed with transparent glue and the integrated circuit chip may be sealed with opaque glue.

Abstract: A flat bed image scanner uses a contact image sensor to scan a document. The distance between the contact image sensor and the glass window, over which the document is placed, is minimized and held constant by inserting a lubricating element between the contact image sensor and the glass window. The lubricating element may comprise two pads placed at the two ends of the contact image sensor. The lubricating element can also be integrated structurally with the contact image sensor. The material of the lubricating element can be nylon or some other kinds of plastic. The lubricating element may also comprise two rollers placed at the two ends of the contact image sensor.

Abstract: This invention provides a flat-edge scanner capable of scanning a thick book without any distortion at the protruding binding edge. The binding edge of the book is placed at the corner of a scanning glass window and the frame supporting the glass window so that the book can lie snugly over the window. The scanning window area is extended to the edge of the frame supporting the scanning window. All the optical system and the driving mechanism lie inside the boundary of the scanning window to increase the scanning range.

Abstract: A dust-collecting padding is placed at the leading edge of the scan window of a scanner. When this dust-collecting padding is in contact with the document to be scanned, the dust particles on the document are collected by the dust-collectng padding, thus maintaining the cleanliness of the document and the scan window. The focal point of the scanning light, where the document is read, can be adjusted to be located away from the surface of the glass window, and thus any dust particles lying on the glass surface are off focus and do not adversely affect the quality of scanning much.

Abstract: This invention provides a flat-bed scanner capable of scanning a thick book without any distortion at the protruding binding edge. The scanning window forms an obtuse angle with the frame of the scanner supporting the scanning window. The obtuse angle allows the binding edge of the book to rest snugly over the window. The slanted structure of the frame also makes room for the image reading head to scan to the very edge of the page of the document.

Abstract: A semiconductor static memory cell with two cross-coupled inverters and two transmission gates for coupling two bit lines uses all minimum size (gate length and gate width) MOSFETs to achieve minimum area. This minimum dimension is rendered possible by using a higher threshold voltage for the transmission gate MOSFET than the threshold voltage of pull-down MOSFET of the inverter. Different threshold voltages are obtained with selective ion implantation, different gate oxide thicknesses and/or different gate doping.

Abstract: An automatic document feeding device has a document feeding roller which feeds a document from a stack to a conveying roller which conveys the document for further processing. The document feeding roller has intermittent motion which feeds the conveying roller with three different speeds: first, at a first speed for feeding the document; then, at a speed faster than the first speed as dragged by the document; and finally, a temporary stop. The temporary stop provides sufficient interspace between the successive documents so that a correct pagination signal is generated. The intermittent motion is provided by a power transmitting component which is coupled to the document feeding roller to speed it up when engaged and is decoupled during the stop interval.

Abstract: The memory cells of a read-only memory are connected in parallel between adjacent bus-bit lines. The selection of tile sub-bit lines is through a selector logic decoder. The decoder has many rows of MOSFETs connected in series. Only one of MOSFETs in a row between an adjacent bit line bus and a virtual ground bus is active and controllable by a sub-word line selection signal with other MOSFETs non-conducting and connected between two adjacent sub-bit lines. These active MOSFETs in different rows are connected in series. One of these active MOSFETs is coupled to a main bit line, and another of these active MOSFETs is coupled to a virtual ground. When the active MOSFET is open, the main bit line signal and the virtual signal appear between the corresponding memory cells between these two corresponding sub-bit lines and are sensed. With this structure, the accessed memory cell is coupled between the main bit line and the virtual ground line through a number of series MOSFETs.

Abstract: A row select driver circuit is used to energize each pixel row sequentially of a liquid crystal display. The output of each row select driver circuit is connected to a corresponding pixel row line and to a succeeding row select driver circuit as an activating input. All the row select circuits are integrated with thin-film transistors and deposited on the same glass substrate as the pixels. The number of leads connected to the assembly is much less than the number of pixel rows, including six overlapping clock signals (three each for odd-numbered rows and even-numbered rows), a shift-in signal, a positive power supply terminal and at least one ground. In one example, the number of leads is reduced from 240 to 10.

Abstract: A unified zero-reset phase is used in a dual-slope analog-to-digital converter (ADC) to: (1) derive a correction voltage to cancel any error due to offset and/or residue voltages in the components of the ADC in the subsequent integration phase and the de-integration phase; (2) reset the output of the integrator in the ADC to zero quickly when there is a overflow condition due to excessive analog input signals. The combined function is accomplished by negative feedback from the output of the comparator to the input of the buffer. The negative feedback resets the integrator output to zero quickly under overflow condition. The correction voltage is stored in the integrating capacitor and a coupling capacitor to the integrating amplifier.

Abstract: Parallel processing architecture is used for an adder and its "look-ahead" zero-flag generator, which generates a flag signal for the most significant bit of the sum of the adder. The look-ahead zero-flag is generated with combinatorial logic circuits, which are fed from the addends and augents of the different bits for the adder and then decoded. The combinatorial logic circuits may comprise AND gates and XOR gates in a gate-array, and the decoder may be a programmable logic array (PLA). The computation time for the zero-flag thus generated is shorter than the computation time for the sum of the adder.

Abstract: The polysilicon bottom electrode of a stacked fin structure storage capacitor for a DRAM cell is self-aligned with the buried contact to the diffusion of a MOSFET. A silicon nitride layer and a sacrificial oxide (sac) umbrella overhangs the buried contact. Using the sac oxide as a mask, the silicon nitride layer is undercut until a part of the polysilicon buried contact is exposed. Then another polysilicon layer is deposited to contact the buried contact and to form the bottom electrode of the capacitor. Thus the bottom electrode and the buried contact are self-aligned. Again, using the sac oxide as a mask, the bottom electrode is etched laterally to form fin-shape electrode. Then, the bottom electrode is deposited with a capacitor dielectric and a top electrode to form the storage capacitor.

Abstract: A row select driver circuit is used to energize each pixel row sequentially of a liquid crystal display. The output of each row select driver circuit is connected to a corresponding pixel row line and to a succeeding row select driver circuit as an activating input. All the row select driver circuits are integrated with thin-film transistors and deposited on the same glass substrate as the pixels. The number of leads connected to the assembly is much less than the number of pixel rows, including two sets of overlapping clock signals (three each for odd-numbered rows and even-numbered rows offset by one scanning line time) with different pulsewidths and periods twice as long as the scanning line time, a clock signal with a period as long as the scanning line time, a shift-in signal, a positive power supply terminal and at least one ground.

Abstract: A charge pumping circuit generates a negative voltage equal in magnitude to the positive supply voltage. A non-overlapping clock is used to set the voltage across a first capacitor equal to the positive supply voltage through a MOS switch. This stored voltage is then transferred to a second capacitor through a second MOS switch to generate a negative voltage at one terminal of the second MOS switch. The use of MOS switches eliminates the threshold voltage drop if MOS diodes were used to charge the first capacitor or to transfer the voltage from the first capacitor to the second capacitor.

Abstract: The output buffer using an LDD NMOS is protected with an SCR at the output pad against electrostatic discharge (ESD). An abrupt (non-LDD) junction NMOS is used as the equivalent npn transistor in the pnpn SCR structure in a dedicated n-well. The non-LDD NMOS has a lower avalanche breakdown voltage than the LDD NMOS buffer, and triggers the SCR to turn on before the avalanche breakdown of the LDD transistor. This non-LDD NMOS lowers the trigger voltage and diverts the ESD current from flowing through the buffer to avoid damage to the buffer.Besides the n-well for forming the protective SCR, auxiliary n+diffusions and n-wells are placed outside the n-well for to form drains of another non-LDD NMOS, which are connected to the positive power supply. These non-LDD NMOS act as npn transistor and are turned on when high voltage ESD pulses appears at the I/O pad or any power supply terminal to shunt the ESD current to ground, thus avoiding latch-up between the power supply terminals.

Abstract: A thin film transistor structure and fabrication method for active matrix liquid crystal display. The structure is a self-aligned coplanar/staggered one. The feature of this structure is the self-aligned source and drain electrode to minimize the stray capacitance between the gate and the drain and the source. The source and drain electrodes are obtained by exposing negative photoresist on top of the transistor by incident light from the back of the transparent substrate using the gate electrode as a mask.