Abstract: A low power repair circuit for a memory matrix is achieved by using two cross-coupled 2-input CMOS OR-gates to form a precharged flip-flop, using two PMOS as drivers. The first OR-gate has a load device comprising a number of parallel branches, each having an NMOS switch in series with a fuse. There are twice as many branches as there are addresses in the predecoder for the memory matrix. Two such branches correspond to an address signal and its complement. The parallel branches are connected to ground through an enable switch and are pulled-down when the enable switch is closed by an enable signal. The fuses of the branches are cut according the address of the faulty word line. The gates of the NMOS switches in are connected to the addresses of the word line predecoder. The output of the first OR gate is precharged to be high.

Abstract: The electrode of a storage capacitor of a DRAM cell lies diagonally along the memory cell. The diagonal layout makes the length of the capacitor longer than either the x-dimension or the y-dimension of the memory cell, thus increasing the storage capacitance.

Abstract: A liquid crystal display device having a sealing material close to display area while maintaining a uniform liquid crystal cell gap is disclosed. The liquid crystal display comprises two transparent electrode substrates having a trench near the display area to stop the sealing material overflowing to display pixels. Thus, the effective display area of a liquid crystal display device is increased by dispensing a sealing material to a trench area at a predetermined position surrounding the display area. A spacer used in the sealing material is larger in size than that used in the display area to compensate the depth of the trench. After the liquid crystal is injected into the space surrounded by the substrates and a sealing material, a uniform liquid crystal cell gap over the entire display area is obtained.

Abstract: A surface mount semiconductor laser diode package has a substrate on which the laser diode is mounted. The top electrode of the laser diode is wire-bonded to the top end of a plated-through conduit through the substrate, and the bottom end of the plated-through conduit is connected to a circuit contact plated at the bottom surface of the substrate. The bottom electrode of the laser diode is flip-chip mounted to the top end of another plated-through conduit, and bottom end of the second plated-through conduit is connected to a second circuit contact. Each laser diode is covered with a transparent lid or a lid with a lens. For mass production, a large number of the laser diodes arranged in a matrix formation are mounted on a common substrate. Walls are erected around each laser diode. A transparent cover is placed over the walls. All the plated-through conduits at the edges of the laser diodes in a same column are aligned and sawed through together.

Abstract: An array antenna is steered by changing the time delays of a local oscillator signal feeding a number of mixers, each fed by an individual antenna element. The beat frequency thus produced can be made in-phase by compensating time delays of different antenna elements in the array with different delays from the local oscillator. The delays from the local oscillator are obtained with optical fibers of variable lengths.

Abstract: Optical signal produced by a semiconductor electroabsorption modulator is passed through an optical discriminator to increase the optical and electrical modulation response of the device and decrease the output chirp for distortionless transmission through dispersive optical fiber.

Abstract: The display area of a liquid crystal display cell is increased by placing conductive epoxy within the boundary which seals the liquid crystal to connect the top glass plate with the bottom glass plate, in contrast with the conventional method of making the electrical connection outside the display area. The conductive epoxy is dispensed in areas not occupied by the liquid crystal patterns. The conductive epoxy can be in the form of particles of spheres or rods serving as spacers for maintaining the gap dimension between the two glass plates. The conductive epoxy can also be integrated with the boundary sealing epoxy or fill a notch cut in the boundary sealing epoxy.

Abstract: A flat package for integrated circuit chip has a substrate with plated through holes. The top flange of a plated through hole is interconnected to a terminal of the IC chip. The bottom flange of the through hole has a cavity recessed into the substrates. A solder is placed between a circuit contact on a mother board and the bottom flange. Upon heating, the solder rises to fill the cavity, to make connection between the terminal on the IC chip and the contact on the mother board.

Abstract: A semiconductor wafer is planarized by first mapping the flatness profile and then etching the wafer according to the flatness profile. Mapping is accomplished by scanning the wafer with a light beam. The flatness information is obtained by a phase detector comparing the phase of the reflected light beam and a reference light, and is then stored in a memory. The etching is implemented with scanning chemical ion beam etching, in which a reactive gas etches the wafer from spot to spot according to the instantaneous volume of reacting gas or the potential at the wafer, and is controlled by the data stored in the memory. The method can be used to planarize both semiconductor and metal.

Abstract: An array antenna is steered by moving a set of optical fibers of different optical length between a number of light signal sources and an array of antennas. By changing the lengths of the optical paths of the different light signals sources, the wave front can be steered. The light signal traverses three sections of optical delay lines with at least one selectable optical length. In the first section, light signal from a point source travels through a first optical delay line and a lens to diverge and collimate the light beam with increased cross section. The collimated light beam is focused by second lens and incident one second optical line of selectable optical length. The light beam exiting from the other end of the second optical line is collimated again by a third lens to face a third optical line. The collimated light exiting from the second optical line is focused again by a fourth lens to feed the third optical line, which is connected at the other end to one element of the antenna array.

Abstract: The number of external column driver chip can be reduced to one in an active matrix liquid crystal display with column input multiplexing driving scheme. At least two sample and hold circuits are used for each column with alternate sampling and holding periods. Video signals are sampled and held at least twice during one line scanning time. These sample and hold circuits are all integrated in the driver chip.

Abstract: The collecting tray of a ink-jet printer is equipped with a guard to prevent the paper immediately after exiting from the printer to fall to the bottom of the tray. The guard is much narrower than the width of the tray so that the guard tilts the paper. A succeeding sheet of paper pushes the tilted paper until the tilted paper is pushed beyond the end of the guard and falls to the bottom of the tray after a time delay for the ink to dry.

Abstract: The frequency of an integrated oscillator is held constant by using temperature compensation to compensate for the component variations due to temperature variations. A voltage controlled oscillator, which has temperature dependent components, is compensated with a temperature dependent control voltage. The frequency of many kinds of oscillators such as a relaxation oscillators and ring oscillators can be held constant when the operating current is held constant. The operating current is often derived from a current source, which is a voltage to current converter with a current equal to the ratio of a control voltage to a resistance. Since semiconductor resistance has a positive temperature coefficient is used to obtain a temperature invariant current source. The positive temperature coefficient is obtained with the difference junction voltage of two forward-biased pn junction voltages. The magnitude can be controlled by junction areas of the two junctions. The magnitude can also be amplified.

Abstract: An array antenna is steered by moving a set of optical filters of different optical lengths between a number of light signal sources and an array antenna elements. By changing the lengths, hence the time delays, of a plurality of the signal paths between the light signal source and the antenna array elements, the wave front can be steered. Each delay path comprises a selected fiber optic line and a fixed electrical delay line. In one embodiment the fiber optical lines assume a parabolic distribution in time delay. In another embodiment, the fiber optical lines assume a cosinusoidal distribution in time delay. Signals are fed to the fiber optic path through a laser diode and exit from the path through a photo-diode. The fiber optic lines are mounted on a rotatable disk, with two ends diametrically located at two different radii.

Abstract: A stand-alone, real-time voice recognition system, which converts an analog voice signal into serial digital signal, then preprocesses in parallel the digital signal to detect the end-point, and output fixed multi-order prediction coefficients. In this recognition system, these multi-order prediction coefficients are stored as the reference pattern in the training mode. In recognition mode, these multi-order prediction coefficients are adapted by dynamic time warping method, which is modified by a symmetric form. This symmetric form is implemented with a one-dimensional circular buffer for dynamic programming matching instead of the traditional two-dimensional buffer to save memory space. Finally, these adapted coefficients are compared with reference pattern to output the result of recognition.

Abstract: A semiconductor static memory cell with two cross-coupled inverters and two transmission gates for coupling two bit lines uses all minimum size (gate length and gate width) MOSFETs to achieve minimum area. This minimum dimension is rendered possible by using a higher threshold voltage for the transmission gate MOSFET than the threshold voltage of pull-down MOSFET of the inverter. Different threshold voltages are obtained with selective ion implantation, different gate oxide thicknesses and/or different gate doping.

Abstract: The surface of an integrated circuit, which uses reactive ion etching to pattern metal interconnection, is protected with two insulating layers on the surface. The first layer is a conventional silicon dioxide. The second layer is a photosensitive polymer which is the same as the material used for subsequent metalization of interconnection using the reactive ion etching technique. When the second layer is used, the reactive ion etching cannot attack the silicon dioxide.

Abstract: In a "flat cell" read-only memory with a matrix of memory cells, each memory cell is a MOSFET of either a low threshold voltage, which can be turned on when accessed, or a high threshold voltage which cannot be turned on when accessed. Each memory cell is connected between two adjacent columns of local bit lines. These local bit lines are alternately connected to a upper bank selection switch which is connected to a main bit line, and a lower bank selection switch, which is connected to a main virtual ground line. Since these local bit lines are fabricated with diffusion layers which are resistive, the path length, hence the resistance, to access any memory cell in the matrix from the main bit line to the main virtual ground is made the same by this alternate, interdigital local bit line layout. Thus, the access time is made uniform.The layouts of two adjacent banks are mirrored, so that the bank selection switches of two adjacent banks can share a common selection line.

Abstract: The electrode of a storage capacitor of a DRAM cell lies diagonally along the memory cell. The diagonal layout makes the length of the capacitor longer than either the x-dimension or the y-dimension of the memory cell, thus increasing the storage capacitance.

Abstract: An image sensor chip is mounted on a printed wiring frame over a substrate, which is plated with a spider web of plated conductors connecting the IC through via holes to the bottom of the substrate as output terminals. After wiring bonding the IC to the plated conductor, the package is sealed. A wall is erected around the image sensor chip and is covered with a transparent glass. A lens may be placed in the middle of the cover for focusing. The structure is amenable to mass production. A large number of printed wiring frames are arranged as a matrix on a common substrate. The frames are sealed column by column or sealed all at once. After sealing, the common substrate are diced into individual packages. The image sensor package may mounted with integrated circuit chips as peripheral circuits. The image sensor chips may be sealed with transparent glue and the integrated circuit chip may be sealed with opaque glue.