Abstract: In an integrated circuit having an on-chip power supply, a voltage maintenance circuit includes a decoupling capacitor connected between the output node and ground, a supplementary capacitor connected between a supplementary node and ground and a controllable transistor connected between the two capacitor nodes, so that when the output voltage drops below a threshold a reference circuit turns on the controllable transistor, thereby supplying extra charge to the output node and restoring it to its design voltage more quickly than the power supply could.

Abstract: A method is provided for forming a vertical transistor memory cell structure with back-to-back FET cells which are formed in a planar semiconductor substrate with a plurality of deep trenches having vertical FET devices and a plurality of capacitors each located in a separate trench that is formed in the semiconductor substrate. Bilateral outdiffusion strap regions are formed extending into a doped semiconductor well region in the substrate. There are confronting pairs of outdiffusion strap regions extending from adjacent deep benches into the doped well region. An isolation diffusion region is formed in the doped well separating the confronting isolation diffusion regions by extending therebetween.

Abstract: A semiconductor torsional micro-electromechanical (MEM) switch is described having a conductive movable control electrode; an insulated semiconductor torsion beam attached to the movable control electrode, the insulated torsion beam and the movable control electrode being parallel to each other; and a movable contact attached to the insulated torsion beam, wherein the combination of the insulated torsion beam and the control electrode is perpendicular to the movable contact. The torsional MEM switch is characterized by having its control electrodes substantially perpendicular to the switching electrodes. The MEM switch may also include multiple controls to activate the device to form a single-pole, single-throw switch or a multiple-pole, multiple-throw switch. The method of fabricating the torsional MEM switch is fully compatible with the CMOS manufacturing process.

Abstract: A three-dimensional micro- electromechanical (MEM) varactor is described wherein a movable beam and fixed electrode are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the “chip side” while the fixed bottom electrode is fabricated on a separated substrate “carrier side”. Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and “flipped over”, aligned and joined to the “carrier” substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used.

Abstract: A process for preventing spurious intersections in a polygon due to rounding by using proximity-based rounding. A vertex of a polygon is identified which is located within a unit integer box through which an edge of the polygon passes that does not have the vertex as an endpoint. The identified vertex is embedded on the edge which passes through the same unit integer box. Then the vertices are rounded to integer coordinates. In one embodiment of the invention, the proximity-based rounding is performed on an output polygon from a Boolean operation in a design rule checking algorithm.

Abstract: A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.

Abstract: A system and method is disclosed for simultaneously searching and refreshing a memory array of a dynamic content addressable memory (DCAM). According to the disclosed invention, the information stored in a row of DCAM cells being refreshed is transferred from the memory array into sense amplifiers, during a read phase of a refresh operation. A search for a matching entry can then be performed, with respect to the information that is transferred to the sense amplifiers. To determine if there is a match, search information is simultaneously compared to the information that has been transferred to the sense amplifiers and to the information that is stored in other rows of DCAM cells of said memory array. Finally, the refresh of that row is completed by restoring the information from the sense amplifiers to that row of DCAM cells.

Abstract: A multiple finger off chip driver (OCD) has a single level translator for each of a plurality of PFET fingers and NFET fingers which allow the impedance of the OCD to be varied to match the impedance of a driven load. A plurality of PFET and NFET finger selection devices are used to select various combinations of output FETS and ballast resistor finger combinations to drive an output signal at a desired impedance level. The ballast resistors are scaled in ohmic value to the size of the output finger it is connected to. In this configuration, a constant ratio of FET impedance to ballast resistance is maintained in each drive stage (finger). By selecting various combinations of fingers various driver impedances can be selected.

Abstract: A method and system for analyzing the dynamic behavior of an electrical circuit to determine whether a voltage level provided by a power supply network drops below a predetermined voltage level during operation of the electrical circuit is described. In a first step, a design data set representing pertinent technical specifications of an electrical or an integrated circuit are read in order to extract location information and value of switching and non-switching capacitance. Next, the circuit and technology propagation speeds are inputted therein. The length for specifying the size of a portion of a circuit area is determined wherein the electrical circuit is formed. Next, the circuit area is divided into a plurality of partitions of a specified size, and the switching capacitance and the non-switching capacitance are separately summarized for each partition. The voltage level drop is then calculated for each partition.

Abstract: A calibration system for a Phase Locked Loop (PLL) includes a phase/frequency detector coupled to the output of a voltage controlled oscillator (VCO) and to a source of a reference frequency. A charge pump is connected to receive an error signal from the phase/frequency detector and provide a voltage to a low pass filter. The low pass filter provides a filtered error signal to the VCO and to a comparator system. The comparator system provides a comparator output signal indicating when the polarity of the error signal exceeds a positive limit or a negative limit. A calibration means continuously provides incremental calibration inputs to the VCO, after a time delay. Thus the frequency of the VCO in the PLL is continuously corrected to compensate for frequency drift, and avoid jitter caused by an excessive rate of response to calibration inputs.

Abstract: A three-dimensional micro- electromechanical (MEM) varactor is described wherein a movable beam and fixed electrode are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the “chip side” while the fixed bottom electrode is fabricated on a separated substrate “carrier side”. Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and “flipped over”, aligned and joined to the “carrier” substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used.

Abstract: A Deep Trench (DT) capacitor in a semiconductor substrate has an isolation collar formed on trench sidewalls above the DT bottom. An outer plate is formed below the collar. Capacitor dielectric is formed on DT walls below the collar. An node electrode is formed in the DT, recessed below the DT top. The collar is recessed in the DT. A combined poly/counter-recrystallizing species cap is formed over the node electrode with a peripheral strap. The cap may be formed after formed a peripheral divot of a recessed collar, followed by forming an intrinsic poly strap in the divot and doping with a counter-recrystallization species, e.g. Ge, into the node electrode and the strap. Alternatively, the node electrode is recessed followed by codeposition of poly and Ge or another counter-recrystallization species to form the cap and strap.

Abstract: A method for correcting proximity effects on a mask used in a lithographic process is described. Proximity effects are recognized to be low-pass filter in nature and full advantage of this fact is taken. Shapes having a high radius of curvature are replaced with mask patterns having smaller radii of curvature, rendering the image less susceptible to low-pass filtering effects while achieving a high fidelity printing on the mask. This approach provides better control to the mask designer to handle critical dimensions of the shapes on the mask.

Abstract: A DRAM array having a DRAM cell employing vertical transistors increases electrical reliability and reduces bitline capacitance by use of an asymmetric structure in the connection between the wordline and the transistor, thereby permitting the use of a wider connection between the wordline and the transistor electrode and using the wordline as an etch stop to protect the transistor gate during the patterning of the wordlines.

Abstract: As the silicon-on-insulator field effect transistor (SOI FET) CMOS technology continues migrating towards thinner SOI thicknesses to reduce the parasitic capacitance and improve the short channel effects, it is known that the body resistance of body contacted MOSFETs increases correspondingly. The problem is compounded for strong halo and weak wells device designs for T-shaped or L-shaped BC-MOSFETs. The invention provides a structure and a method that includes an additional well level implant for n-type and p-type devices in selected parts of the extended gate region. A new mask increases the channel doping at the extended gate region to prevent that region from fully depleting and increasing the carrier concentration for lower resistance. Since the physical gate dimensions are usually narrower than the mask dimensions, the mask is slightly offset from the extended gate edge to avoid excessive encroachment into the intrinsic device channel region.

Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse.

Abstract: Digital latency shift communication problems from a driver chip to a receiver chip are overcome by scheduling a data output latency, a data input latency, a data output command, and/or a data output command, such that data outputted by the driver chip is received by the receiver chip at the correct time. A digital shift detection circuit detects the offset of the actual latencies from predetermined latencies. The offset of the latency is fed back to the scheduling circuit to override the predetermined latencies and/or command inputs that control the chip. The offset can be directly back-fed to the chip driver or chip receiver to compensate for digital shifts. Digital shift detection is achieved by measuring actual latencies with a manufacturing stand-alone tester, or with a built-in tester integral to the system. The digital shift detection predicts the conditions that create a digital shift by way of a mathematical model.

Abstract: A method of forming a self-aligned gettering region within an SOI substrate is provided. Specifically, the inventive method includes the steps of forming a disposable spacer on each vertical sidewall of a patterned gate stack region, the patterned gate stack region being formed on a top Si-containing layer of an SOI substrate; implanting gettering species into the top Si-containing layer not protected by the disposable spacer and patterned gate stack region; and removing the disposable spacer and annealing the implanted gettering species so as to convert said species into a gettering region.

Abstract: A method of fabricating and the structure of a micro-electromechanical switch (MEMS) device provided with self-aligned spacers or bumps is described. The spacers are designed to have an optimum size and to be positioned such that they act as a detent mechanism for the switch to minimize problems caused by stiction. The spacers are fabricated using standard semiconductor techniques typically used for the manufacture of CMOS devices. The present method of fabricating these spacers requires no added depositions, no extra lithography steps, and no additional etching.

Abstract: A power supply noise compensation amplifier has an input for connection to a power supply. The amplifier includes a differential amplifier circuit for providing an instantaneous amplified signal in response to power supply noise, and produces an output signal with an instantaneous opposite polarity from the power supply noise so a noise sensitive circuit connected to the noise compensation amplifier has a compensated power supply signal which enables it to produce a reduction in the amplitude of the noise signal at the output thereof. The differential amplifier circuit includes a differential pair of coupled transistor circuits including a leading transistor circuit and a lagging transistor circuit.