Abstract: A method for resolving overlaps in the cell placement (placement legalization) during the physical design phase of an integrated chip design is described. This problem arises in several contexts within the physical design automation area including global and detailed placement, physical synthesis, and ECO (Engineering Change Order) mode for timing/design closure The method involves capturing a view of a given placement, solving a global two-dimensional area migration model and locally perturbing the cells to resolve the overlaps with minimal changes to the given placement. The method first captures a two-dimensional view of the placement including blockage-space, free-space and the given location of cells by defining physical regions. The desired global area migration across the physical regions of the placement image is determined such that it satisfies area capacity-demand constraints.

Abstract: A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail bit detection to activate a given bank. The pass/fail bit detection is prompted only for a selected domain and is disabled when it addresses other domains. By altering the domain selection, it is possible to enable a redundancy allocation for any domain regardless of the multi-bank operation. The method may preferably be realized by using a dynamic exclusive-OR logic with true and complement expected data pairs. When combined with simple pointer logic, the selection of domains may be generated internally, simplifying the built in self-test and other test control protocols, while at the same time tracking those that fail.

Abstract: A tetrahedralization and triangulation method used with the proximity based rounding method to satisfy topological consistency of tetrahedralization with the bounded precision of a digital computer is described. Tetrahedralization is applied to a VLSI design, and more specifically for solving Maxwell's equation to extract parasitic capacitances and 3-D optical proximity correction applications. The exactness of solving Maxwell's equation and finite element analysis depends on the correctness of the topological properties of the tetrahedralization. Among the important aspects of the correctness of the topological properties is the absence of spurious intersection of two or more tetrahedra. In a typical digital computer, numbers are represented using finite sized words. Round-off errors occur when a long number is represented using the finite word size. As a result, tetrahedralization loses its topological consistency.

Abstract: A generalized method for optimizing the global placement of a VLSI chip across multiple cost metrics, such as total wire length, timing, congestion, and signal integrity is described. The method relies upon a “look ahead” technique, combined with any generic cost function that can be used to set placement directives. These placement directives include net weights and cell spreading. The method of performing the placement involves the iterative reuse of the process of successive partitioning. This iterative reuse establishes the capability of looking ahead to determine what is to happen. Based on the look ahead, it is possible to evaluate the qualities of the placement about to be generated. The method proceeds through the placement from while maintaining the current state of the placement along with the look-ahead state of the placement.

Abstract: A method of verifying the placement of sub-resolution assist features (SRAFs) in a photomask layout is described. SRAFs are added to the photomask layout to enhance the process window for semi-isolated and isolated features. Rules are provided to automatically place the SRAFs into the layout. When deficiencies are detected in the assist feature design or in the automated SRAF placement program, the placement of SRAFs requires verification. The method verifies the correct placement by defining a unique image property linked to the accurate placement of the assist features, and combines it with in-situ image simulation of the individual layout.

Abstract: A structure and method are provided for a conductor line stack of an integrated circuit. The conductor line stack includes a layer of a first material such as heavily doped polysilicon or a metal silicide. A layer of a second material such as a metal is formed over the layer of first material, the layer of second material having an upper portion and a lower portion. A pair of first spacers is disposed on sidewalls of the upper portion, wherein the lower portion has width defined by a combined width of the upper portion and the pair of first spacers. A pair of second spacers is formed on sidewalls of the first spacers, the lower portion and the layer of first material. The conductor line stack structure is well adapted for formation of a borderless bitline contact in contact therewith.

Abstract: A multi-port memory architecture utilizing an open bitline configuration for the read bitline is described. The memory is sub-divided into two arrays (A and B) consisting of memory gain cells arranged in a matrix formation, the cells having two general ports or separate read and write ports to enable simultaneous a read and write operation. Each memory array includes a reference wordline coupled to reference cells. When the reference cell is accessed, the read bitline (RBL) discharges to a level at half the value taken by a cell storing a 0 or 1. Each pair of RBLB in the same column of the two arrays is coupled to a differential sense amplifier, and each write bitline (WBL) in the two arrays is linked to write drivers WBLs in the two arrays are driven to the same voltage and at the same slew rate. The WBL swing in each array creates coupling noise by the bitline-to-bitline capacitors.

Abstract: A method for reducing the switching activity during both scan-in and scan-out operations of an integrated circuit with reduced detrimental effect on test pattern effectiveness and test time is described. The method makes use of a sample set of patterns to determine the probabilities of same and opposite relationships between stimulus and result values, and uses these probabilities to determine memory element pair compatibilities. Scan chains are ordered preferentially by connecting adjacently compatible memory elements, and inversions are inserted between selected memory element pairs based on those probabilities. Unspecified stimulus bits are filled in to reduce the switching activity based on the scan chain ordering and inversions.

Abstract: A method is described to improve the data transfer rate between a personal computer or a host computer and a neural network implemented in hardware by merging a plurality of input patterns into a single input pattern configured to globally represent the set of input patterns. A base consolidated vector (U?*n) representing the input pattern is defined to describe all the vectors (Un, . . . , Un+6) representing the input patterns derived thereof (U?n, . . . , U?n+6) by combining components having fixed and ‘don't care’ values. The base consolidated vector is provided only once with all the components of the vectors. An artificial neural network (ANN) is then configured as a combination of sub-networks operating in parallel. In order to compute the distances with an adequate number of components, the prototypes are to include also components having a definite value and ‘don't care’ conditions. During the learning phase, the consolidated vectors are stored as prototypes.

Abstract: A concurrent refresh mode is realized by allowing a memory array to be refreshed by way of a refresh bank select signal, while concurrently enabling a memory access operation in another array. The refresh address management is greatly simplified by the insertion of row address counter integrated within each array. In the preferred embodiment, any combination of a plurality of the memory arrays is refreshed simultaneously while enabling a memory access operation. This concurrent mode also supports a multi-bank operation.

Abstract: A system and method for correcting wiring congestion in a placed and partially or fully globally-routed VLSI chip design while avoiding adding new timing or electrical violations or other design constraints. Globally-congested areas are identified along with determining terminated and non-terminated wires in the congested areas. The process includes optimizing the identified congestion areas, incrementally rerouting affected nets, testing the resultant design legality and congestion metrics, and committing or reversing the optimizations and reroutings. The optimizations further includes the movement of logic cells and decomposition, recomposition or any other modification of logic cell structures (possibly combined with cell movement) to move terminated wires to less congested grid edges, rearrangement of commutative connections within or between cells, or addition of buffers to cause reroutes of feedthrough wires.

Abstract: A system and method is disclosed for simultaneously testing columns and column redundancies of a semiconductor memory by temporarily adding an additional parallel signal bit to an input/output data bus associated therewith, the additional parallel signal bit providing greater bandwidth during test mode operation. The input/output data bus has n parallel signal bits which normally carry column data, but the additional parallel signal bit does not normally carry either column data or column redundancy data. The additional parallel signal bit may normally carry a clock signal such as an echo clock associated with the data placed on the data bus.

Abstract: A three-dimensional micro electro-mechanical (MEMS) variable capacitor is described wherein movable comb electrodes of opposing polarity are fabricated simultaneously on the same substrate are independently actuated. These electrodes are formed in an interdigitated fashion to maximize the capacitance of the device. The electrodes are jointly or individually actuated. A separate actuation electrode and a ground plane electrode actuate the movable electrodes. The voltage potential between the two electrodes provides a primary mode of operation of the device. The variation of the sidewall overlap area between the interdigitated fingers provides the expected capacitance tuning of the device. The interdigitated electrodes can also be attached on both ends to form fixed-fixed beams. The stiffness of the electrodes is reduced by utilizing thin support structures at the ends of the electrodes. The three dimensional aspect of the device avails large surface area.

Abstract: A method for evaluating the quality of an image, for extracting a luminance gradient displayed on a display device and for evaluating local luminance unevenness caused therein. The method includes the steps of: subdividing the image to be used as an evaluation object into a plurality of pixels; acquiring a first luminance information by calculating the difference between the sum of luminance values of predetermined pixels and the luminance value of a predetermined pixel, the predetermined pixels forming a first pixel group surrounding the predetermined pixel; acquiring a second luminance information by calculating the difference between the sum of luminance values of predetermined pixels and the luminance value of the predetermined pixel, the predetermined pixels constituting a second pixel group; acquiring a third luminance information by adding the first luminance information and the second luminance information; and evaluating the luminance of a screen photographed based on the third luminance information.

Abstract: An object of the present invention is to provide an apparatus and method for ensuring a uniform orientation of liquid crystal molecules of an alignment layer by irradiation with ion beams. An apparatus of the present invention comprises a grid 11a having a plurality of ion ejection holes 30 of various sizes. The size of the ion ejection hole 30 varies depending on an ion density. The size of the ion ejection hole 30 increases with decrease in the ion density.

Abstract: Accurate gradation display on an OLED display device is effectuated by reducing a kickback voltage based on parasitic capacitance of a switching TFT without increasing a capacitance of a capacitor which retains a voltage to be supplied to a driving TFT. A capacitor for maintaining on-and-off states of a driving TFT which drives an OLED is charged by a switching TFT. The capacitor is connected to a scan line, which drives a switching TFT located in a preceding stage in accordance with a scanning order. After being charged by the switching TFT, a reference potential on the capacitor is raised to compensate for a drop in a gate voltage of the driving TFT attributable to parasitic capacitance of the switching TFT, in accordance with a signal from the scan line.

Abstract: A two-port dynamic random access memory (DRAM) cell consisting of two transistors and two trench capacitors (2T and 2C DRAM cell) connecting two one transistor and one capacitor DRAM cell (1T DRAM cell) is described. The mask data and cross-section of the 2T 2C DRAM and 1T DRAM cells are fully compatible to each other except for the diffusion connection that couples two storage nodes of the two 1T DRAM cells. This allows a one-port memory cell with 1T and 1C DRAM cell and a two-port memory cell with 2T and 2C DRAM cell to be fully integrated, forming a true system-on chip architecture. Alternatively, by halving the capacitor, the random access write cycle time is further reduced, while still maintaining the data retention time. The deep trench process time is also reduced by reducing by one-half the trench depth.

Abstract: A memory architecture that utilizes single-ended dual-port destructive write memory cells and a local write-back buffer is described. Each cell has separate read and write ports that make it possible to read-out data from cells on one wordline in the array, and subsequently write-back to those cells while simultaneously reading-out the cell on another wordline in the array. By implementing an array of sense amplifiers such that one amplifier is coupled to each read bitline, and a latch receiving the result of the sensed data and delivering this data to the write data lines, it is possible to ‘pipeline’ the read-out and write-back phases of the read cycle. This allows for a write-back phase from one cycle to occur simultaneously with the read-out phase of another cycle.

Abstract: A micro-electro mechanical switch having a restoring force sufficiently large to overcome stiction is described. The switch is provided with a deflectable conductive beam and multiple electrodes coated with an elastically deformable conductive layer. A restoring force which is initially generated by a single spring constant k0 upon the application of a control voltage between the deflectable beam and a control electrode coplanar to the contact electrodes is supplemented by adding to k0 additional spring constants k1, . . . , kn provided by the deformable layers, once the switch nears closure and the layers compress. In another embodiment, deformable, spring-like elements are used in lieu of the deformable layers.

Abstract: An integrated circuit real-time data tracing apparatus for analyzing microprocessor based computer systems for monitoring, in real-time, parameters sufficient to define the load and store operations information that the embedded core controller may assert, and process information during events. Integral on this single chip apparatus is a data trace unit designed to access control, address, and data signal lines required to monitor the embedded core controller's activities; perform data tracing independent of instruction tracing; synchronize with an instruction trace stream; allow for selection of multiple ranges for data tracing; report lost events to a FIFO array; and, output strobe signals to give a cycle accurate indication of when an event has been captured.