Abstract: The present invention relates to a combustion temperature sensor, and, more particularly, to a combustion temperature sensor that measures infrared radiation emitted at several preselected wavelengths from a flame and/or a flame's hot gas at a turbine inlet location and applies the energy signals. to a calculation model to yield temperature.

Abstract: The output circuit of the present invention which produces an external signal at a first voltage from an internal signal at a reduced second voltage and which outputs the external signal from an output terminal, comprises: first and second MOS transistors having drains connected to the output terminal, and having gates connected to a control signal line; a third MOS transistor having a source connected to a power source of the first voltage, and having a drain connected to a source of the first MOS transistor; a fourth MOS transistor having a source connected to a ground, having a drain connected to a source of the second MOS transistor, and having a gate connected to an internal signal line; a voltage changer, which changes the voltage of the internal signal, connected to the gate of the third MOS transistor; a first capacitor connected between a gate of the first MOS transistor and a gate of the third MOS transistor; and a second capacitor connected between a gate of the second MOS transistor and a gate of

Abstract: A method of producing an integrated circuit having a plurality of electronic components by the steps of: a) forming plurality of components with connection points in a substrate plate; b) forming a connection support of conducting tracks; c) transferring the substrate plate onto the connection support connecting the connection points with the conducting tracks; d) forming at least one separation trench in the substrate plate, surrounding a portion of substrate having at least one electronic component, in a way that separates it from the other components in the plate; and e) filling the trenches with a dielectric material.

Abstract: A silicon substrate including an impurity doped thereinto is raised in temperature to a predetermined annealing temperature, and then the temperature of the silicon substrate reaching the annealing temperature is decreased at variable speeds such that the temperature is decreased at a high speed initially and a low speed latterly. The temperature of the silicon substrate is decreased at such a speed as the impurity with a reduced solid solubility due to the decreased temperature is not acted upon by thermal energy to disconnect the impurity from the silicon substrate.

Abstract: To reduce leakage current from a current source transistor in a charge pump circuit of a PLL circuit, the charge pump circuit is activated according to an up signal or a down signal generated according to whether the phase of a clock output from VCO is faster or slower than that of a reference clock for generating current for charging or discharging an LPF that supplies input to VCO of the disclosed PLL circuit. The charge pump circuit is composed of a first current source transistor for generating current for charging LPF, a first switching transistor for connecting the first current source transistor to a power source according to an up signal, a second current source transistor for generating current for discharging LPF and a second switching transistor for grounding the second current source transistor according to a down signal, and bias is applied to the first and second current source transistors when the charge pump circuit is inactivated.

Abstract: A dielectric film formed on a porous valve metal body is contacted with an oxidizing agent and dried. Then, by contacting the dielectric film with a monomer solution for forming an electrolyte layer of electroconductive polymer, a electrolyte layer of a solid electrolytic capacitor is formed by an oxidative polymerization reaction. An oxidative polymerization retarding agent, which delays the oxidative polymerization reaction, is added to at least one of the solutions, an oxidant solution and a monomer solution. The oxidative polymerization retarding agent delays the oxidative polymerization reaction when it contacts with the oxidant and monomer. As a result, the permeation of the monomer for forming an electroconductive polymer layer into small pores increases, and the covering rate of the electroconductive polymer in small pores increases, which improves the capacitance appearance factor and the equivalent series resistance in high frequency region.

Abstract: Cationically hardening masses are described, which can be stored and handled as single-component masses and comprise at least one difunctional cationically polymerizable compound; a photo-initiator for the cationic hardening based upon diaryliodonium salts; at least one compound containing an hydroxyl group; a compound releasing radicals when heated and having a half-life of one hour at a temperature of less than 100° C.; a photo-initiator forming radicals or of a photo-sensitizing agent for diaryliodonium salts; and from 0 to 60 parts by mass of modifier. The compounds are used for bonding, casting, sealing and coating of substrates.

Abstract: In the liquid crystal display, a first backlight and a second backlight are provided and lightened simultaneously. Among all the lamps constituting the backlight, those lamps outputting oscillation waves in one phase are made equal or nearly equal in number to those lamps outputting oscillation waves in the phase opposite to the phase mentioned above.

Abstract: An arrived call receiving system including a caller's number automatic recognition unit for extracting and recognizing a phone number included in an arrived call, an automatic answering unit for confirming by the caller whether the recognized phone number is correct and recognizing a reply from the caller, as well as conducting necessary processing according to the contents of the recognized reply, a caller's information storage unit and a caller's information data base for storing the phone number of the caller obtained by the caller's number automatic recognition unit, and a caller automatic call-up unit for reading the phone number of the caller stored in the caller's information data base to automatically call up the caller according to instructions of an operator.

Abstract: A structure for reinforcing a printed circuit board in a low cost preventing failures such as solder cracks and lands stripped off the printed circuit board is disclosed. The printed circuit board having a rectangular shape is mounted with electronic components. On the inner wall surfaces of a housing, a plurality of pillar-shaped supports are formed so as to protrude at predetermined positions. Both edges of the printed circuit board in a longitudinal direction are fitted into respective ones of grooves formed in a pair of reinforcing members. Each reinforcing member has a rib integrally formed in a direction perpendicular to the opening direction of the groove. The reinforcing members are fixed by screws to the respective ones of the supports.

Abstract: There is provided a method for forming a Shallow Trench Isolation (STI) easy to suppress an occurrence of the debot even when the micro-scratch is present. A silicon oxide film made of an organic Spin-On-Glass (SOG) film is formed on a surface of a silicon oxide film in which a micro-scratch is generated by Chemical Mechanical Polishing (CMP). Such anisotropic etching is conducted that an etching rate for a silicon oxide film may be equal to that for the silicon nitride film, to remove the silicon nitride film and then remove by wet etching a pad oxide film, to nevertheless prevent a debot from occurring.

Abstract: A lot supply system includes a plurality of processing units, a supply unit, a plurality of counters, and a supply controller. The processing units output a lot supply request and perform a predetermined process for a lot supplied to them. The supply unit supplies a lot stored in it to requesting processing units in response to the lot supply request from the processing units. The counters count product lots supplied to the requesting processing units at least in units of the requesting processing units. When counts of the counters reach preset values set in units of the requesting processing units, the supply controller supplies measurement lots stored in advance to the requesting processing unit and initializes counts of the counters. A lot supply method is also disclosed.

Abstract: In a method of designing a test facile semiconductor integrated circuit with scan paths, a method of designing an optimum assigning arrangement of scan paths. For minimizing an area of interconnection wiring of scan paths among the logic blocks, the average number of flip-flops to be subjected to a scan path test, expressed another word as a scan path length, is calculated at first. Combinations and division of the logic blocks on which a scan path is assigned are calculated for all number of scan paths. Wiring length of interconnection among the logic blocks for each assigning combination of total scan paths is calculated to select the shortest wiring length interconnection among logic blocks as the optimal scan paths assigning arrangement.

Abstract: A bipolar transistor has a lightly doped n-type single crystal silicon layer epitaxially grown in a recess formed in a heavily doped n-type impurity region after a selective growth of a thick field oxide layer, a base region, an emitter region and a collector contact region are formed in surface portions of the lightly doped n-type single crystal silicon layer, and the single crystal silicon layer is not affected by the heat during the growth of the thick field oxide layer, and has a flat zone constant in dopant concentration regardless of the thickness thereof.

Abstract: A semiconductor device that operates at high speed using a low voltage power source, in which the output of each gate in the standby state is stable, and which has a delay time that is not affected by the frequency of the input signal. TrQ1 to TrQ8, which form multiple stages of the inverters are designed to have a low threshold voltage in order to accomplish low voltage operation. When input node A is at “L” in the standby state, TrQ2, Q3, Q6, and Q8 which cut-off are connected to high threshold voltage TrQn1 and Qp1. In the standby state, power cutting TrQn1 and Qp1 cut off in accordance with chip selecting signals CS, /CS, thereby blocking the flow of sub-threshold current to TrQ1˜Q8. Since TrQ1, Q4, Q5 and Q8 are not cut off at this time, the output potential of each inverter is stable.

Abstract: A foundation element in the form of a rigid monolithic prefabricated frame which includes at least two opposite containing side walls and cross-members interconnecting the two side walls so as to form a casting through-cavity between these two walls. The frame is intended to be located on the ground with the interposition of adjustable support devices and is intended to receive a hardenable fluid binder material poured into its through-cavity and adapted to spread onto the ground between this and the side walls and to fill the cavity, encapsulating the cross-members and the iron rods or other connecting members for connecting a superstructure element. Also provided are prefabricated structures including prefabricated tunnels, with foundation elements formed by means of the said prefabricated frames.

Abstract: A layout compaction method adapted to be embodied in computer program product and adapted for compacting a circuit layout having a plurality of layers on which moving objects form layer patterns, wherein the moving objects comprising components and wires. The method assumes a graph problem under condition which prevent the compacted result from violation of the design rule, and then, solves the graph problem to determine a moving order, a moving direction, and a moving distance of each component for moving the components to thereby perform the compacting the circuit layout. After that, the method moves each component according to the moving order, the moving direction and the moving distance to obtain a compacted circuit layout.

Abstract: Even input bit lines, a first latch circuit group and a second latch circuit group are provided in a logical circuit. The first latch circuit group has a plurality of latch circuits which simultaneously latch a plurality of signal bits propagating the even input bit lines, respectively, in a first timing. The second latch circuit group has a plurality of latch circuits which simultaneously latch a plurality of signal bits propagating the even input bit lines, respectively, in a second timing. The output ends of a plurality of latch circuits are wired-OR to a first node, the plurality of latch circuits latching signal bits which propagate one half of the even input hit lines. The output ends of a plurality of latch circuits are wired-OR to a second node, the plurality of latch circuits latching signal bits which propagate remaining one half of the even input bit lines. The first and the second nodes, are wired-OR to a third node.