Patents Represented by Attorney IP & T Group LLP

Find this attorney in the Justia Lawyer Directory

  • Nonvolatile memory device for preventing a source line bouncing phenomenon
    Patent number: 8184482
    Abstract: A nonvolatile memory device includes a memory cell array configured to include cell strings coupled between respective bit lines and a source line, a unilateral element coupled to the source line, and a negative voltage generation unit coupled to the unilateral element and configured to generate a negative voltage.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: May 22, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Cheul Hee Koo
  • Semiconductor memory device and method for operating the same
    Patent number: 8184500
    Abstract: A semiconductor memory device includes a plurality of banks, a first bank selection driving control signal generation unit configured to generate a plurality of first bank selection driving control signals corresponding to the plurality of banks in response to an active command signal and an address signal, a second bank selection driving control signal generation unit configured to generate a plurality of second bank selection driving control signals corresponding to the plurality of banks in response to one of a read command signal and a write command signal and in response to the address signal, and an internal voltage driver configured to selectively drive a plurality of internal voltage terminals corresponding to the plurality of banks in response to the plurality of first bank selection driving control signals and the plurality of second bank selection driving control signals.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: May 22, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Choung-Ki Song
  • Semiconductor memory apparatus
    Patent number: 8179737
    Abstract: A semiconductor memory apparatus includes an internal circuit configured to be driven by current flowing between first and second voltage nodes, and a current control unit configured to control an amount of the current in response to an operational-speed information signal.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: May 15, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Jin Byeon
  • Semiconductor device
    Patent number: 8179179
    Abstract: A semiconductor device includes a reset signal generator configured to change the number of activated signals among a plurality of reset signals according to a frequency of an external clock, a plurality of mixing control signal generators configured to generate a plurality of first and second mixing control signals, and a clock mixer configured to generate a mixing clock by mixing a first driving clock and a second driving clock, wherein the first driving clock is generated by driving a positive clock of the external clock according to the plurality of first mixing control signals, and the second driving clock is generated by driving a negative clock of the external clock according to the plurality of second mixing control signals.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: May 15, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Su Park, Hoon Choi
  • Page buffer circuit and nonvolatile memory device
    Patent number: 8179722
    Abstract: A page buffer circuit comprises a sense amplification unit configured to compare a reference voltage and a bit line voltage of a bit line of a selected memory block and to increase a voltage level of a sense node by a difference between the reference voltage and the bit line voltage, wherein the bit line voltage is subject to being changed according to a program state of a selected memory, and a number of latch circuits configured to latch program verification data according to the voltage level of the sense node.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: May 15, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hwang Huh
  • Method of operating nonvolatile memory device
    Patent number: 8174903
    Abstract: A method of operating a nonvolatile memory device, including a memory cell array, which further includes a drain select transistor, a memory cell string, and a source select transistor coupled between a bit line and a source line, where the method includes precharging the bit line, setting the memory cell string in a ground voltage state, coupling the memory cell string and the bit line together and supplying a read voltage or a verification voltage to a selected memory cell of the memory cell string, and coupling the memory cell string and the source line together in order to change a voltage level of the bit line in response to a threshold voltage of the selected memory cell.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: May 8, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jung Chul Han, Seong Je Park
  • Bit line precharge circuit and a semiconductor memory apparatus using the same
    Patent number: 8174916
    Abstract: A bit line precharge circuit includes a precharge signal generation unit configured to generate first and second precharge signals that are enabled at different timing points by receiving a bit line equalizing signal; a first precharge unit configured to connect a pair of bit lines to each other in response to the first precharge signal and supply a bit line precharge voltage to the pair of bit lines; and a second precharge unit configured to supply the bit line precharge voltage to the bit line in response to the second precharge signal.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: May 8, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyung Sik Won
  • Nonvolatile memory device and method of operating the same
    Patent number: 8174896
    Abstract: A nonvolatile memory device comprises a page buffer unit, a counter, a program pulse application number storage unit, and a program start voltage setting unit. The page buffer is configured to output a 1-bit pass signal when a cell programmed to exceed a reference voltage, from among target program cells included in a single page, exists. The counter is configured to count a number of program pulses applied to determine a program pulse application number. The program pulse application number storage unit is configured to store a number of program pulses applied until the 1-bit pass signal is received during a program operation for a first page. The program start voltage setting unit is configured to set a program start voltage for a second page based on the stored program pulse application number.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: May 8, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyu Hee Lim, Seong Je Park, Jung Chul Han
  • Program method of flash memory device
    Patent number: 8174894
    Abstract: A program method of a flash memory device includes inputting a first data and a second data to a page buffer coupled to memory cells including an even page and an odd page, pre-programming a first memory cell of the odd page using the first data, programming a second memory cell of the even page using the second data, and programming the pre-programmed first memory cell using the first data.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: May 8, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ju In Kim
  • Fuse circuit and redundancy circuit
    Patent number: 8174862
    Abstract: A fuse circuit or a redundancy circuit is capable of detecting a fuse with a crack. The fuse circuit includes a fuse block configured to drive an output node through a current path including a fuse in response to a fuse enable signal, and a voltage detection block configured to detect a voltage level of the output node based on a critical voltage adjusted according to a test mode signal, thereby generating a fuse condition signal.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: May 8, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Choung-Ki Song, Han-Sub Shin
  • Semiconductor device and method for driving the same
    Patent number: 8171358
    Abstract: A semiconductor device and a method for driving the same rapidly detect failure of a through-semiconductor-chip via and effectively repairing the failure using a latching unit assigned to each through-semiconductor-chip via. The semiconductor device includes a plurality of semiconductor chips that are stacked, and a plurality of through-semiconductor-chip vias to commonly transfer a signal to the plurality of semiconductor chips, wherein each of the semiconductor chips includes a multiplicity of latching units assigned to the through-semiconductor-chip vias and the multiplicity of latching units of each of the semiconductor chips constructs a boundary scan path including the plurality of through-semiconductor-chip vias to sequentially transfer test data.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: May 1, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang-Hoon Shin, Hyung-Dong Lee, Jeong-Woo Lee, Hyang-Hwa Choi
  • Apparatus and method for generating resistance calibration code in semiconductor integrated circuit
    Patent number: 8169232
    Abstract: A resistance calibration code generating apparatus includes a code calibration unit configured to calibrate and output code values of a resistance calibration code during predetermined cycles of a calibration clock, which are determined by a code calibration time control command, and a calibration clock generating unit configured to output the calibration clock using a code calibration command.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: May 1, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Jin Byeon
  • Semiconductor memory device and method for generating bit line equalizing signal
    Patent number: 8169837
    Abstract: A bit line equalizing signal generator of a semiconductor memory device uses a supply voltage and a pumping voltage in stages during a period where a bit line equalizing signal is enabled, thereby enhancing an equalizing speed and an active speed while minimizing power consumption. The semiconductor memory device includes a bit line equalizing signal generating unit configured to drive an output terminal with the supply voltage during a first activation period at the beginning of the period where the bit line equalizing signal is enabled, and to drive the output terminal with the pumping voltage higher than the supply voltage during a second activation period following the first activation period, thereby outputting the bit line equalizing signal, and a bit line equalizing unit configured to equalize a bit line pair in response to the bit line equalizing signal.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: May 1, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chang-Ho Do
  • Skew detector and semiconductor memory device using the same
    Patent number: 8169842
    Abstract: A skew detection circuit includes a data sensing block configured to sense a first data that is transferred earliest and a last data that is transferred latest among a plurality of data which are transferred through different transfer paths, and generate a sensing result signal; and a detection signal generation block configured to compare an output signal of the data sensing block with a certain time, and generate a skew detection signal.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: May 1, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seong-Jun Lee
  • Semiconductor device with buried bit lines and method for fabricating the same
    Patent number: 8169020
    Abstract: A semiconductor device includes a substrate having trenches, buried bit lines formed in the substrate, and including a metal silicide layer and a metallic layer, wherein the metal silicide layer contacts sidewalls of the trenches and the metallic layer is formed over the sidewalls of the trenches and contacts the metal silicide layer.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: May 1, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yun-Seok Cho
  • Semiconductor memory device
    Patent number: 8164963
    Abstract: A semiconductor memory device includes: a first strobe signal generation unit configured to generate a first rising strobe signal in response to a rising DLL clock signal; a second strobe signal generation unit configured to generate a second rising strobe signal in response to a falling DLL clock signal, the second rising strobe signal having an opposite phase to the first rising strobe signal and being activated at the same timing as the first rising strobe signal; a third strobe signal generation unit configured to generate a first falling strobe signal in response to the falling DLL clock signal; and a fourth strobe signal generation unit configured to generate a second falling strobe signal in response to the rising DLL clock signal, the second falling strobe signal having an opposite phase to the first falling strobe signal and being activated at the same timing as the first falling strobe signal.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: April 24, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee-Jin Byun
  • Semiconductor memory device with ferroelectric device and refresh method thereof
    Patent number: 8164941
    Abstract: A semiconductor memory device with a ferroelectric device comprises a channel region, a drain region and a source region formed in a substrate, a ferroelectric layer formed over the channel region, and a word line formed over the ferroelectric layer. A different channel resistance is induced to the channel region depending on a polarity state of the ferroelectric layer, a data read operation is performed by a cell sensing current value differentiated depending on the polarity state of the ferroelectric layer while a read voltage is applied to the word line and a sensing bias voltage is applied to one of the drain region and the source region, and a data write operation is performed by a polarity of the ferroelectric layer changed depending on a voltage applied to the word line, the drain region and the source region.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: April 24, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hee Bok Kang, Suk Kyoung Hong
  • Vertical channel type non-volatile memory device and method for fabricating the same
    Patent number: 8163617
    Abstract: A method for fabricating a vertical channel type non-volatile memory device including forming a source region, alternately forming a plurality of interlayer dielectric layers and a plurality of conductive layers for a gate electrode over a substrate with the source region formed therein, forming a trench exposing the source region by etching the plurality of interlayer dielectric layers and the plurality of conductive layers for a gate electrode, and siliciding the conductive layers for a gate electrode and the source region that are exposed through the trench.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: April 24, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jung-Ryul Ahn
  • Magnetoresistive memory cell using floating body effect, memory device having the same, and method of operating the memory device
    Patent number: 8159871
    Abstract: A magnetoresistive memory cell includes an MTJ device and a select transistor. The select transistor includes a first conduction-type semiconductor layer, a gate electrode formed by disposing a gate insulating layer on top of the semiconductor layer, and first and second diffusion regions formed in the semiconductor layer to be spaced apart from each other and to have a second conduction type. A part of the semiconductor layer between the first and second diffusion regions is formed as an electrically floating body region. By using a high-performance select transistor with a floating body effect, high integration of a magnetoresistive memory device may be achieved.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: April 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Woong Chung
  • Method for forming active pillar of vertical channel transistor
    Patent number: 8158529
    Abstract: A method for forming an active pillar of a vertical channel transistor includes forming a hard mask pattern on a substrate, etching vertically the substrate using the hard mask pattern as an etch barrier to form an active pillar, and etching horizontally to remove by-product remaining on the exposed substrate, the hard mask pattern and the active pillar and at the same time to reduce line width of the hard mask pattern and the active pillar, wherein a unit cycle in which the vertical etching and the horizontal etching are each performed subsequently once, respectively, is performed repeatedly at least two times or more. According to the present invention, an active pillar having vertical profiles on its sidewalls and having height and line width (or diameter) required in a highly integrated vertical channel transistor can be provided.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: April 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Myung-Ok Kim