Patents Represented by Attorney IP & T Group LLP

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  • Non-volatile memory device and method for fabricating the same
    Patent number: 8198156
    Abstract: A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: June 12, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Nam-Jae Lee
  • Semiconductor device and fabrication method thereof
    Patent number: 8198171
    Abstract: A method for fabricating a semiconductor device includes: providing a substrate; forming a plurality of trenches by etching the substrate; forming a first isolation layer by filling the plurality of the trenches with a first insulation layer; recessing the first insulation layer filling a first group of the plurality of the trenches to a predetermined depth; forming a liner layer over the first group of the trenches with the first insulation layer recessed to the predetermined depth; and forming a second isolation layer by filling the first group of the trenches, where the liner layer is formed, with a second insulation layer.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: June 12, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyung-Hwan Kim
  • Reference wafer for calibration and method for fabricating the same
    Patent number: 8198626
    Abstract: A reference wafer maintains laser accuracy and calibrates a camera and a laser of a semiconductor equipment. The reference wafer includes a first anti-reflection layer, an adhesive layer, a light absorption layer and a second anti-reflection layer that are stacked over a substrate, a light reflection layer formed over the second anti-reflection layer, and a protection layer formed over the light reflection layer.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: June 12, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyun-Chul Lee, Jung-Taik Cheong, Gue-Hong Song, Ky-Hyun Han
  • Bi-directional multi-drop bus memory system
    Patent number: 8195855
    Abstract: A bus system includes a plurality of stubs; a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules; a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs, wherein the first and the second serial loads are determined to be impedance matched at each transmission line terminal of the stubs.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: June 5, 2012
    Assignees: Hynix Semiconductor Inc., Seoul National University Industry Foundation
    Inventors: Deog-Kyoon Jeong, Suhwan Kim, Woo-Yeol Shin, Dong-Hyuk Lim, Ic-Su Oh
  • Semiconductor device, memory system, and method for controlling termination of the same
    Patent number: 8193829
    Abstract: A semiconductor device includes a plurality of first input units configured to receive a command, a second input unit configured to receive a termination command, a termination control unit configured to be enabled by the termination command and decode the command to control a termination operation, and a termination unit configured to be controlled by the termination control unit and terminate an interface pad.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: June 5, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Choung-Ki Song
  • Method of forming metal lines of semiconductor device
    Patent number: 8193088
    Abstract: A method of forming metal lines of a semiconductor device includes forming an etch stop layer over a semiconductor substrate over which underlying structures are formed, forming an insulating layer over the etch stop layer, etching the etch stop layer and the insulating layer to form trenches through which the underlying structures are exposed, shrinking the insulating layer by using a thermal treatment process in order to widen openings of the trenches, and filling the trenches with a conductive material.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: June 5, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Suk Joong Kim
  • Page buffer of nonvolatile memory device and method of performing program verification operation using the same
    Patent number: 8194464
    Abstract: A page buffer of a nonvolatile memory device comprises a sense unit coupled between the sense node and the bit lines of a memory cell array, comprising a number of memory cells, and configured to precharge the bit lines to different voltage levels in response to a page buffer sense signal of a first or second voltage level, a MUX unit configured to output the page buffer sense signal of the first or second voltage level in response to a control signal according to a value of program data, a flag latch configured to temporarily store the program data and to output the control signal to the MUX unit, and a main latch configured to sense the voltage levels of the bit lines via the sense node and to perform a program verification operation.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: June 5, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hwang Huh, Myung Cho
  • Fuse circuit of semiconductor device and method for monitoring fuse state thereof
    Patent number: 8193851
    Abstract: A fuse circuit of a semiconductor device includes a plurality of fuse set units configured to compare an input address with address information programmed according to a fuse cutting state and a test control unit configured to enable one or more fuse set units selected based on a number of times that a selection signal is enabled in a test mode.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: June 5, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung-Lo Kim
  • Semiconductor memory device and method for operating the same
    Patent number: 8194476
    Abstract: A semiconductor memory device includes a voltage detector configured to detect a level of an external power supply voltage and an internal voltage generator configured to generate an internal voltage in response to an active signal and drive an internal voltage terminal with a driving ability corresponding to an output signal of the voltage detector. A method for operating the semiconductor memory device includes detecting a level of an external power supply voltage, based on a first target level, to output a detection signal; and generating an internal voltage in response to an active signal, and driving an internal voltage terminal with a driving ability corresponding to the detection signal.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: June 5, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Khil-Ohk Kang
  • Semiconductor device and method for operating the same
    Patent number: 8193844
    Abstract: A semiconductor device includes an internal source clock generation unit configured to output first and second internal source clocks, a clock phase correction unit configured to correct a phase difference between the first and second internal source clocks according to a detection result, and to output first and second phase-corrected internal source clocks, a clock delay unit configured to delay the first and second phase-corrected internal source clocks and to generate first and second delay locked loop (DLL) clocks, and a clock output unit configured to mix phases of the first and second DLL clocks to output a DLL clock, and to output a feedback clock to reflect an actual delay condition of an external source clock path in the first or second DLL clock.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: June 5, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young-Suk Seo
  • Semiconductor memory device
    Patent number: 8189417
    Abstract: A semiconductor memory device uses a magnetic tunnel junction device (MTJ) and includes a memory cell connected between a first driving line and a second driving line and configured to store data having a data state that is determined based on a direction of a current flowing through the first and the second driving lines, and a current controlling block configured to control a supply current provided to the first and second driving lines in response to temperature information in a writing operation.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Young-Hoon Oh, Sung-Yeon Lee
  • Page buffer circuit
    Patent number: 8189392
    Abstract: A page buffer circuit comprises a first sensing unit configured to sense a voltage of a bit line and change a voltage of a first sense node, a data conversion unit configured to sense a voltage level of the first sense node and change a voltage level of a second sense node or to couple the second sense node and the first sense node, and first and second latch units coupled in common to the second sense node.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Soo Park
  • Page buffer circuit of nonvolatile memory device and method of operating the same
    Patent number: 8189394
    Abstract: The page buffer of a nonvolatile memory device utilizing a double verification method using first and second verification voltages when performing a program verification operation includes a first latch unit including a first latch configured to store input data and results of a program operation and a first verification operation using the first verification voltage, and a second latch unit including a second latch configured to have a higher latch trip point than the first latch and to store a result of a second verification operation using the second verification voltage, which is less than the first verification voltage, when the first verification operation is performed.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyun Jong Jin, Jin Haeng Lee
  • Semiconductor memory device
    Patent number: 8189425
    Abstract: A semiconductor memory device includes a burst pulse generation unit configured to store a burst length information signal in response to a first control signal and output the burst length information signal as a burst pulse signal in response to a second control signal; and an input/output(I/O) control unit configured to generate the first and second control signals in response to a read pulse signal and a latency signal, respectively.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Heat-Bit Park, Jae-Il Kim
  • Three-dimensional nonvolatile memory device and method for fabricating the same
    Patent number: 8188517
    Abstract: A three-dimensional nonvolatile memory device includes: a plurality of channel structures extending in parallel in a first direction and comprising a plurality of channel layers that are alternatively stacked with a plurality of interlayer insulating layers over a substrate; a plurality of memory cells stacked along sidewalls of the channel structures and arranged in the first direction and a second direction crossing the first direction; and a plurality of word lines extending in parallel in the second direction and connected to the memory cells arranged in the second direction.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Eun-Seok Choi
  • Non-volatile memory device and method for fabricating the same
    Patent number: 8187938
    Abstract: A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Se-Yun Lim, Eun-Seok Choi, Young-Wook Lee, Won-Joon Choi, Ki-Hong Lee, Sang-Bum Lee
  • Integrated circuit
    Patent number: 8189308
    Abstract: An integrated circuit includes an input/output pad for signal exchange with an external circuit, an electrostatic discharge (ESD) protection unit coupled to the input/output pad and configured to form an ESD path between a first voltage line and a second voltage line, a first drive transistor coupled between the first voltage line and the input/output pad, a first driving control unit coupled to a gate of the first drive transistor and configured to control the first drive transistor, a first dummy drive transistor coupled between the first voltage line and the input/output pad, and a first auxiliary driving control unit configured to supply the first voltage to a gate of the first dummy drive transistor in a normal operation mode, and float the gate of the first dummy drive transistor in a non-operation mode in which no power is supplied.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dong-Ju Lim
  • Method for fabricating semiconductor device
    Patent number: 8187952
    Abstract: A method for fabricating a semiconductor device includes etching a semiconductor substrate using a hard mask layer as a barrier to form a trench defining a plurality of active regions, forming a gap-fill layer to gap-fill a portion of the inside of the trench so that the hard mask layer becomes a protrusion, forming spacers covering both sides of the protrusion, removing one of the spacers using a doped etch barrier as an etch barrier, and etching the gap-fill layer using a remaining spacer as an etch barrier to form a side trench exposing one side of the active region.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Uk Kim, Sang-Oh Lee
  • Nonvolatile memory device and method of programming the same
    Patent number: 8184483
    Abstract: A nonvolatile memory device includes a memory cell array, including a first memory cell group configured to store data and a second memory cell group configured to store operation information, including first and second program start voltages, a page buffer unit, including page buffers each configured to store program data for memory cells or store data read from the memory cells, and a control unit configured to, when a program operation is first performed after power is supplied, count a number of program pulses until a verification operation using a first verification voltage is a pass, compare the counted number and a first number of program pulses, select either the first or second program start voltages according to a result of the comparison, and control the program operation to be performed using the selected program start voltage until the power is off.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: May 22, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Min Oh
  • Semiconductor device and method for operating the same
    Patent number: 8184496
    Abstract: A semiconductor device includes a sensing unit configured to sense whether a value of a programming sensing node is within a predefined range, a fuse connected to the programming sensing node, a programming voltage supplying unit configured to supply a programming voltage to the programming sensing node, and a transferring unit configured to transfer the value of the programming sensing node in response to the sensing result of the sensing unit.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: May 22, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jin-Youp Cha, Sang-Jin Byun