Patents Represented by Attorney IP & T Group LLP

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  • Architecture of highly integrated semiconductor memory device
    Patent number: 8159898
    Abstract: A semiconductor memory device includes: a first row control circuit region corresponding to a first memory bank; a first column control circuit region corresponding to the first memory bank; a second row control circuit region corresponding to a second memory bank and disposed adjacent to the first row control circuit region; and a second column control circuit region corresponding to a third memory bank and disposed adjacent to the first column control circuit region.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: April 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seok-Cheol Yoon
  • Sensing characteristic evaluating apparatus for semiconductor device and method thereof
    Patent number: 8159891
    Abstract: A sensing characteristic evaluating apparatus for a semiconductor device includes a test current supply unit configured to supply a test current to an input/output line during a test mode for evaluating a sensing characteristic, and a sensing amplifying circuit configured to receive the test current from the input/output line, to compare and amplify a sensing input voltage corresponding to the test current with a reference voltage, and to output an amplified voltage as a sensing output voltage.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: April 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Taek-Seung Kim
  • Nonvolatile memory device and method of testing the same
    Patent number: 8159892
    Abstract: A nonvolatile memory device includes a storage unit configured to store pattern data selected based on a test command set, and a control unit configured to consecutively perform a program operation on a number of pages in response to the pattern data to obtain programmed pages, consecutively perform a read operation on the programmed pages, and provide information about a bit line coupled to a fail memory cell and about a number of fail bit lines checked as a result of the read operation.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: April 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Tai Kyu Kang
  • Method of operating nonvolatile memory device
    Patent number: 8154948
    Abstract: A method of operating a nonvolatile memory device includes supplying a variable voltage of a first voltage level to a selected page buffer and supplying the variable voltage to a first bit line, coupled to a selected memory cell selected for data reading, for a first time period, cutting off the supply of the variable voltage to the first bit line, after the first time period, and precharging the first bit line to a second voltage level through a sense node of the selected page buffer, which is in a precharge state, evaluating a voltage of the first bit line, after the precharging of the first bit line, so that the voltage of the first bit line is shifted according to a program state of the selected memory cell, and sensing the voltage of the evaluated first bit line and latching data in the selected memory cell.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: April 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Beom Ju Shin
  • Method for fabricating capacitor
    Patent number: 8153486
    Abstract: A method for fabricating a capacitor includes forming an etch stop layer, a first isolating insulation layer, and a floating layer over a substrate including storage node contact plugs to form a resulting substrate structure; etching the floating layer, the first isolating insulation layer, and the etch stop layer to form a plurality of open regions; forming a conductive layer over the substrate structure; forming a second isolating insulation layer over the conductive layer, the second isolating insulation layer filling upper portions of the open regions; etching portions of the remaining floating layer to form a floating pattern; performing a storage node isolation process in a manner that the floating pattern is exposed to form a plurality of storage nodes having sidewalls supported by the floating pattern; and removing the etched first isolating insulation layer.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: April 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seok-Ho Jie
  • Method of reading nonvolatile memory device and nonvolatile memory device for implementing the method
    Patent number: 8154919
    Abstract: A nonvolatile memory device includes a read margin critical value calculation unit configured to calculate a critical value of a read margin between a read voltage and a threshold voltage of a specific cell, an interference value calculation unit configured to calculate an interference value affecting the threshold voltage of the specific cell, a comparison unit configured to compare the critical value and the interference value and to output a result of the comparison, and a data selection unit configured to output either first data, read from the specific cell using a first read voltage, or second data, read from the specific cell using a second read voltage, based on the result outputted from the comparison unit.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: April 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang Kyu Lee, Seung Jae Chung
  • Method for fabricating semiconductor device using spacer patterning
    Patent number: 8153519
    Abstract: A method for fabricating a semiconductor device includes depositing and stacking a hard mask layer and a sacrificial layer over an etch target layer forming a mask pattern with holes defined therein over the sacrificial layer, forming first pillars filling the holes; removing the mask pattern, forming second pillars by using the first pillars as an etch barrier and etching the sacrificial layer, forming spacers surrounding sidewalls of each second pillar, removing the second pillars, etching the hard mask layer by using the spacers as etch barriers to form a hard mask pattern, and forming a hole pattern by using the hard mask pattern as an etch barrier and etching the etch target layer.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: April 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae-Seon Yu
  • Method for fabricating semiconductor device with buried gates
    Patent number: 8153489
    Abstract: A method for fabricating a semiconductor device, including forming a trench by etching a semiconductor substrate, forming a gate insulation layer over a surface of the trench, forming a gate conductive layer over the gate insulation layer, performing a first recess process by etching the gate conductive layer, forming a protection pattern over the gate insulation layer, and performing a second recess process by etching the gate conductive layer.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: April 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Pil-Geun Song
  • Semiconductor device
    Patent number: 8149036
    Abstract: A semiconductor device includes a phase division unit, a clock delay unit, a duty cycle correction clock generation unit, and a duty cycle correction voltage generation unit. The phase division unit is configured to divide a phase of a source clock to generate a first division clock. The clock delay unit is configured to delay the first division clock by a delay amount corresponding to a voltage level of a duty cycle correction voltage to output a second division clock. The duty cycle correction clock generation unit is configured to generate a duty cycle correction clock whose logic level changes at respective edges of the first division clock and the second division clock. The duty cycle correction voltage generation unit is configured to generate the duty cycle correction voltage whose voltage level changes depending on a duty cycle of the duty cycle correction clock.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: April 3, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young-Suk Seo
  • Semiconductor memory device with pulse width determination
    Patent number: 8149636
    Abstract: A semiconductor memory device includes a reset signal generating unit configured to generate a reset control signal by delaying a column command signal by an amount of time varying proportional to an operational frequency. A pulse width determination unit is configured to determine a pulse width of a column selection signal in response to the column command signal and the reset control signal. An address decoding unit is configured to generate the column selection signal corresponding to a corresponding column address in response to an output signal of the pulse width determination unit.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: April 3, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Bo-Yeun Kim
  • Semiconductor memory device
    Patent number: 8149633
    Abstract: A semiconductor memory device is provided which includes a voltage detecting unit configured to compare a target voltage level with a fed-back internal voltage to output a detection signal in a normal mode, a driving unit configured to selectively drive an internal voltage terminal to a first or second power supply voltage according to an operation mode in response to the detection signal, and an enable control unit configured to control the driving unit in response to a control signal corresponding to the operation mode.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: April 3, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Khil-Ohk Kang
  • CAM cell memory device
    Patent number: 8144493
    Abstract: A code address memory (CAM) cell memory device comprises a first storage unit comprising a first nonvolatile memory cell configured to output a power source voltage in response to a read voltage, and a second storage unit comprising a second nonvolatile memory cell configured to output a ground voltage in response to the read voltage.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: March 27, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Hoon Ahn
  • Method of operating nonvolatile memory device
    Patent number: 8144521
    Abstract: A method of operating a nonvolatile memory device comprising cell strings each comprising memory cells coupled in series between a drain select transistor and a source select transistor, including precharging a sense node to thereby precharge a bit line coupled to the cell string for a program or data read operation; and simultaneously resetting a cell channel in a state in which the drain select transistor is turned off, the source select transistor is turned on, and the memory cells are turned on by applying a first voltage to a number of word lines coupled to the memory cells during a first time period, wherein the first time period is less than a bit line precharge time period.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: March 27, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Soo Park
  • Internal negative voltage generation device
    Patent number: 8143937
    Abstract: An internal negative voltage generation device includes a first internal negative voltage generation block configured to generate a first internal negative voltage which is lower than a ground voltage; a second internal negative voltage generation block configured to generate a second internal negative voltage according to the first internal negative voltage, the second internal negative voltage being higher than the first internal negative voltage and lower than the ground voltage; and an initial driving block configured to additionally drive a second internal negative voltage terminal to the first internal negative voltage during an initial set time interval of an active operation time interval.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: March 27, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chang-Ho Do
  • Semiconductor memory apparatus and method for operating the same
    Patent number: 8144542
    Abstract: A semiconductor memory apparatus includes a clock input unit configured to receive a system clock and a data clock, a data clock phase regulation unit configured to regulate a frequency of the data clock, and delay the data clock by a delay varied in accordance with a training information signal, and a clock phase comparison unit configured to compare a phase of an output clock of the data clock phase regulation unit with a phase of the system clock, and generate the training information signal according to a result of the comparison.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: March 27, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kwang-Jin Na
  • Delay locked loop
    Patent number: 8143925
    Abstract: A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: March 27, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung-Joon Ahn, Jong-Chern Lee
  • Pulse control device
    Patent number: 8143927
    Abstract: A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: March 27, 2012
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Kyoung-Nam Kim, Tae-Yun Kim
  • Latency control circuit, semiconductor memory device including the same, and method for controlling latency
    Patent number: 8144531
    Abstract: A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a delay value for delaying the input signal based on a latency value of the input signal and the path information, and a delayer configured to delay the input signal by a delay corresponding to the delay information.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: March 27, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hae-Rang Choi, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
  • Internal supply voltage generating circuit and method for generating internal supply voltage
    Patent number: 8143940
    Abstract: An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: March 27, 2012
    Assignee: Hynic Semiconductor Inc.
    Inventors: Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
  • Semiconductor memory device and method for generating output enable signal
    Patent number: 8144530
    Abstract: A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: March 27, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyung-Soo Kim, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park